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Rto Based Vehicular Adhoc Network
Rto Based Vehicular Adhoc Network
Introduction
transmitte signals from a sign board which are installed by RTO at road side it will
transmitte signals which will contain necessary information and it will be catch by the
receiver which is going to be installed that the user end that means in the car or any other
vehicle.
Functionality
In this project the sign board which are install at the roads side by the RTO in that sign
board there will be transmitter which will trasmitte frequency or digital signals
continuously and that signals will be catched by the receiver installed in the vehicle as
and when the signals are catched by the receiver it will raise an alarm or a warning
displaying the necessary message. For example if the road is one way and the car driver
does not know that this road is one way and the driver is entering into that one way road
then the receiver will catch the signals from the sign board and tell the receiver that you
are entry in a one way traffic so please avoid doing this other wise you will be fined or
the desired message will be displayed so the driver will come to know that he or she is
entering into the restricted area so he or she can be save by not entering in that area e sign
board and it will display the message to the receiver in this way it will work and all the
provide communications among nearby vehicles and between vehicles and nearby fixed
The main goal of VANET is providing safety and comfort for passengers. To this end a
special electronic device will be placed inside each vehicle which will provide Ad-Hoc
Network connectivity for the passengers. This network tends to operate without any infra-
structure or legacy client and server communication. Each vehicle equipped with VANET
device will be a node in the Ad-Hoc network and can receive and relay others messages
through the wireless network. Collision warning, road sign alarms and in-place traffic
view will give the driver essential tools to decide the best path along the way.
There are also multimedia and internet connectivity facilities for passengers, all provided
within the wireless coverage of each car. Automatic payment for parking lots and toll
Most of the concerns of interest to MANets are of interest in VANets, but the details
differ. Rather than moving at random, vehicles tend to move in an organized fashion. The
interactions with roadside equipment can likewise be characterized fairly accurately. And
finally, most vehicles are restricted in their range of motion, for example by being
In addition, in the year 2006 the term MANet mostly describes an academic area of
research, and the term VANet perhaps its most promising area of application.
technologies such as WiFi IEEE 802.11 b/g, WiMAX IEEE 802.16, Bluetooth, IRA,
ZigBee for easy, accurate, effective and simple communication between vehicles on
can be enabled as well methods to track the automotive vehicles is also preferred.
InVANET helps in defining safety measures in vehicles, streaming communication
such as Dedicated Short Range Communications (DSRC) which is a type of WiFi. Other
candidate wireless technologies are Cellular, Satellite, and WiMax. Vehicular Ad-hoc
Transmitter
(Controller)
Applications
Traffic control
Safety
Extended communication
Infotainment
Transmitting Data Memory 89c51
Microcontroller
Decoder Unit
Logical Unit
TX Unit
BLOKDIAGRAM OF TX
Transmitting data :-
It is the data which regulates the speed of the vehicle passing from the
restricted zone.
Memory :-
In this block the transmitted data will be stored. And the signals will be
Microcontroller :-
Decoder unit :-
This block will decode the signals given to it and will transfer the signal to
TX Unit :-
Encoder Microcontroller lc
RX d
BLOKDIAGRAM OF RX
RX Unit :-
This unit will receive the decoded signal from the transmitter and will
Encoder Unit:
This unit will encode the decoded signals received from the transmitter
Microcontroller Unit :-
section. Shows the exact position along with restricted speed in LCD display.
Advantages
Self organization and Management
Information sharing
No limitation network
Disadvantages
Rapidly Changing network topologies.
Constant maintenance.
Future Scopes
There is a plethora of ideas
1. 89c51 Microcontroller.
2. LCD Display.
3. Connecter.
4. Resister.
5. Capacitors.
6. Crystal.
7. Relays.
8. PCB Plate.
9. Power Supply.
SHIFT KEY MODULATION
modulation.
carrier wave is changed in accordance with the intensity (i.e. amplitude) of the
signal. The resultant wave is called modulated wave or radio wave and contains
the audio signal. Therefore, modulation permits the transmission to occur at high
reasons :
(i) Practical antenna length : Theory shows that in order to transmit a
velocity
Frequency
3 x 108
= --------------- meters
frequency (Hz)
they are transmitted directly into space, the length of the transmitting
say 1000 KHz is used to carry the signal, we need an antenna length
The greater the frequency of the wave, the greater the energy
carrier wave with audio signal and permit the transmission to occur at
shift key modulation for picture signal. Therefore, our attention in the
in this chapter shall be confined to the first two most important types
of modulation.
modulator.
The following points are worth noting in amplitude shift key modulation :
(i) The amplitude of the carrier wave changes according to the intensity of
the signal.
(ii) The amplitude variations of the carrier wave is at the signal frequency
fs.
(iii) The frequency of the amplitude modulated wave remains the same i.e.
microprocessor CPU: ALU, PC, SP, and registers. It also has added the other
features needed to make a complete computer: ROM, RAM Parallel I/O, serial
one that is meant to read data, perform limited calculations on that data, and
control its environment based on those calculations. The prime use of a micro-
stored in ROM and that does not change over the lifetime of the system.
The design approach of the microcontroller mirrors that of the micro-
sign accomplishes this goal by having a very flexible and extensive repertoire of
enables large amounts of memory and I/O to be connected to address and data
bus pins on the integrated circuit package. Much of the activity in the
microprocessor has to do with moving code and data to and from external
memory to the CPU. The architecture features working registers that can be
programmed to take part in the memory access process, and the instruction set
is aimed at expediting this activity in order to improve throughput. The pins that
The microcontroller design uses a much more limited set of single- and
double-byte instructions that are used to move code and data from internal
memory to the ALU. Many instructions are coupled with pins on the integrated
circuit package; the pins are "programmable"that is, capable of having several
The microcontroller is concerned with getting data from and to its own pins
the architecture and instruction set are optimized to handle data in bit and byte
size.
The digital o/p is now fed to a 40 pin micro controller IC AT 89C 51. It is a
low power, high performance CMOS, 8 bit microcomputer with 4 K bytes of Flash
Programmable and Erasable Read Only Memory (PEROM). The device is
compatible with the industry standard MCS 51TM instruction set and pin out.
bit CPU with Flash on a monolithic chip, the Atmel AT 89C51 is a powerful
128 bytes of RAM, 32 I/O lines, two 16. Bits timer / counters, a five vector two
level interrupt architecture, a full duplex serial port, on chip oscillator and clock
circuitry.
BLOCK DIAGRAM OF A MICROCONTROLLER
Accumulator
I/O
Port
Register (s)
Internal Interrupt
RAM Internal Circuits
ROM
Port
Clock
Stack Pointer Circuit
Program Counter
PIN CONFIGRATION OF 89C51
Port 1 Bit 0 +5 V
Port 2 Bit 0
Ground
(Address 8)
89C51 Architecture
Latch
PSW RAM I/O
Logic Unit
Port 0
A0-A7
D0-D7
A A
Latch
Port 1
I/O
P DPTR
DPH
Latch
C ROM
DPL
Port 2
I/O
A8-A15
I/O
Interrupt
Latch
Counter
Port 3
Serial Data
Byte/ Bite Special RD WR
EA System Function
ALE Timing Addresses Registers
PSEN System
XTAL1
IE
XTAL2 Interrupts Register
RESET Timer IP
Bank 3
PCON
Data Buffers Register
Memory Control SBUF
Bank 2
Vcc
SCON
GND
TCON
Register
Bank 1 TMOD
TLO
THO
Register
TLI
Bank 0
TH1
Internal RAM Structure
Architecture of 89C51
BIBLIOGRAPHY: -
www.energymeter.com
www.atmel.com