Extended Summary 本文は pp.

176–183

Improvement of Pulse Pattern for Space Vector Modulated Matrix

Converters
Kichiro Yamamoto Member (Kagoshima University)
Katsuji Shinohara Member (Kagoshima University)
Tatsuya Mori Student Member (Kagoshima University)

Keywords: matrix converter, space vector modulation, pulse pattern

Novel modulation which consists of conventional space vector is lower value. Figures 4 and 5 demonstrate frequency spectra for
modulation (SVM) and carrier signal modulation for matrix con- each waveform in Figs. 2 and 3. Proposed SVM can reduce the har-
verters is proposed. monic components except around carrier frequency.
Conventional indirect SVM for matrix converters decides duties
of dγ and dδ for rectifying stage and duties of dα , dβ and d0 for invert- Table 1. Specification for simulation
ing stage. And then, the duties are combined to generate new duties
for the entire matrix converter by products of the corresponding du-
ties. Moreover, the switching pattern for the entire matrix converter
is decided by the phases of input voltage vector and output voltage
command vector and the duties for the matrix converter.
Proposed novel SVM calculates duties dminX , dmidX and dmaxX ,
where dminX is a duty for the switch between the input phase whose
phase voltage is minimum value and the output phase X, dmidX a
duty for the switch between the input phase whose phase voltage is
medium and X and dmaxX a duty for the switch between the input
phase whose phase voltage is maximum and X. The subscript X is
u or v or w, where u, v and w stand for the output phases.
The duties dminX , dmidX and dmaxX are compared to the triangle
(a) Output voltage reference 173 V (b) Output voltage reverence 50 V
carrier (Fig. 1) and the switching pattern for the matrix converter is
decided. The pattern generated by proposed SVM has the following Fig. 2. Output line to line voltage waveforms (conventional SVM)
features;
• Zero output voltage vector is realized by connecting all of out-
put phases to the input phase voltage with medium value.
• Only one of the output phases is switched for an output voltage
pattern change.
• The switching numbers within a sampling period are eight.
• There is no switching between the input phase voltage with
minimum value and the voltage with maximum value. (a) Output voltage reference 173 V (b) Output voltage reverence 50 V
• Zero output voltage is not used when the output phase voltage Fig. 3. Output line to line voltage waveforms (proposed SVM)
command is higher value and the maximum input line to line
voltage is not used when the voltage command is lower value.
Conventional and proposed SVM were compared by the simula-
tion program PSIM and conditions and parameters for the simula-
tion are listed in Table 1. Figures 2 and 3 show simulated waveforms
of output line to line voltage. From the figures, it is clear that pro-
posed SVM does not use zero output voltage when the output phase
voltage command is higher value and does not use the maximum (a) Output voltage reference 173 V (b) Output voltage reverence 50 V
input line to line voltage (dashed line) when the voltage command
Fig. 4. Frequency spectra of output line to line voltage
(conventional SVM)

(a) Output voltage reference 173 V (b) Output voltage reverence 50 V

Fig. 5. Frequency spectra of output line to line voltage
Fig. 1. Method of PWM pattern generation (proposed SVM)

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