Semiconductor Failure Analysis

Semiconductor Failure analysis (FA) is the process of determining how or why a semiconductor
device has failed often performed as a series of steps known as FA techniques. Device failure is
defined as any non-conformance of the device to its electrical and/or visual/mechanical
specifications. Failure analysis is necessary in order to understand what caused the failure and how
it can be prevented in the future.

Electrical failure can either be functional or parametric. Functional failure refers to the inability of a
device to perform its intended function. Parametric failure refers to the inability of a device to meet
the electrical specifications for a measurable characteristic (such as leakage current) that does not
directly pertain to functionality. Thus, a parametric failure may be present even if the device is still
functional or able to perform its intended function.

For example, a DAC that can convert digital data into the correct analogue voltage but draws
excessive supply current is a parametric failure, but one that does not convert data at all is a
functional failure. A device is said to be failing catastrophically if it is grossly failing all parametric and
functional test blocks.

Failure analysis starts with failure verification. It is important to validate the failure of a sample prior
to failure analysis in order to conserve valuable FA resources. Failure verification is also done to
characterize the failure mode. Good characterization of the failure mode is necessary to make the
FA efficient and accurate.

After failure verification, the analyst subjects the sample to various FA techniques step by step,
collecting attributes and other observations along the way. Non-destructive FA techniques are done
before destructive ones. Also, the results of these various FA techniques must be consistent or
corroborative. Any inconsistency in results must be resolved before proceeding to the next step. For
example, a pin that exhibits a broken wire during X-ray inspection but also shows an acceptable
curve trace during curve tracing cannot happen, so this inconsistency must be resolved by verifying
which of the two results is correct.

In general, the results of the various FA techniques would collectively point to the real failure site. The
FA process is finished once there is enough information to make a conclusion about the location of
the failure site and cause or mechanism of failure.
 Optical Microscopy
Optical microscopy, or light microscopy, refers to the inspection of the sample at higher
magnification using an instrument known as an optical or light microscope. During optical or light
microscope inspection, the specimen is positioned perpendicularly to the axis of the objective lens.
Light is then shown on the sample, which reflects some light back to the lens. The image seen in the
microscope depends not only on how the specimen is illuminated and positioned, but on the
characteristics of the specimen as well.

Fig.1. A high-end microscope with an image capture

System (left) and an ordinary optical microscope (right)

A basic light microscope has the following parts: 1) a lamp to illuminate the specimen; 2) a nose
piece to hold 4-5 objectives used in changing the viewing magnification; 3) an aperture diaphragm to
adjust the resolution and contrast; 4) a field diaphragm to adjust the field of view; 5) an eye piece to
magnify the objective image (usually by 10X); and 6) a stage for manipulating the specimen.

Optical microscopes are commonly classified as either low-power or high-power microscopes. Low-
power microscopes are those which typically magnify the specimen at 5X to 60X, although some can
magnify up to 100X. High-power microscopes, on the other hand, typically magnify the specimen at
100X to 1000X.

There are three modes by which optical microscopy are commonly conducted, namely, bright field
illumination, dark field illumination, and interference contrast.

Bright field illumination is the normal mode of viewing with an optical microscope. This mode
provides the most uniform illumination of the sample. Under this mode, a full cone of light is focused
by the objective on the sample. The image observed results from the various levels of reflectivitys
exhibited by the compositional and topographical differences on the surface of the sample.

Under dark field illumination, the inner circle area of the light cone is blocked, such that the sample is
only illuminated by light that impinges on its surface at a glancing angle. This scattered reflected light
usually comes from feature edges, particulates, and other irregularities on the sample surface. Dark
field illumination is therefore effective in detecting surface scratches and contamination.

Interference contrast makes use of polarized light that is divided by a Wollaston prism into two
orthogonal light packets. These slightly displaced light packets hit the specimen at two different
points and return to the prism through different paths. The differences in the routes of the reflected
packets will produce interference contrasts in the image when the packets are recombined by the
prism upon their return.
 Decapsulation / Decapping / Delidding
Decapsulation is a failure analysis step performed to open a plastic package to facilitate
the inspection, chemical analysis, or electrical examination of the die and the internal features of the
package. If the package being opened is hermetic, then the process is referred to as 'Delidding' or
'decapping.' The techniques used for Decapsulation are very different from those of Delidding and
decapping.

De-lidding/de-capping is a purely mechanical process. It may refer to the prying of the combo lid off a
ceramic package, or the application of opposite torques to the top and bottom parts of the ceramic
DIP to break the seal glass, or the cutting of the weld around a metal can.

On the other hand, the more widely used plastic Decapsulation techniques are explained
immediately below.

Manual Chemical Etching

Manual chemical etching consists of manually dispensing some acid on the surface of a package to
remove the plastic material covering the die. Red fuming nitric acid (HNO3) or sulfuric acid (H2SO4)
is often used for this purpose. A cavity is first milled on the top surface of the package. Red fuming
nitric acid heated to about 85-140 deg C or sulfuric acid heated to 140 deg C is then repeatedly
dropped into the cavity to remove the plastic material covering the die. When the die has been
exposed adequately, the unit is rinsed with acetone then with D/I water, before being blow-dried
carefully.

Manual etching may also refer to the process of soaking the package entirely in a beaker of sulfuric
acid heated to about 140 deg C. This process will totally destroy the unit, leaving behind the silicon
die and bits and pieces of undissolved metal piece parts. This is only used for die backside
inspection for cracks.

Plasma Etching

Plasma etching may also be used to expose the die of a plastic package. Plasma etching removes
plastic by making it react with a gas which can easily be vented out. This requires expensive plasma
etching machines but is very clean and selective. It also takes longer compared to other techniques.

Fig. 1. Photo of a Jet Etcher

 Cross-sectioning
Cross-sectioning or micro sectioning is a failure analysis technique for mechanically exposing a
plane of interest in a die or package for further analysis or inspection. It usually consists of sawing,
grinding, polishing, and staining the specimen until the plane of interest is ready for optical or
electron microscopy. The conventional method of micro sectioning requires the encapsulation of the
specimen in plastic to give it stability, support, and protection. A relatively newer technology utilizes
specific tools and procedures to allow non-encapsulated micro sectioning.

Conventional micro sectioning starts with sample preparation. This consists of cleaning, mounting,
and encapsulation of the sample in polyester or epoxy resin. Sometimes, a sample is sawed to
reduce its size prior to encapsulation. This is usually done to fit the specimen perfectly into the mold,
as well as to reduce the grinding needed during actual sectioning.

The positioning of the specimen in the mold during encapsulation is critical. It must be chosen well to
minimize the sawing and grinding needed to expose the plane of interest. The resin is usually poured
inside a vacuum impregnator to minimize bubbles or air pockets, which affect the quality of the micro
sectioned sample. The sample is then allowed to cure at ambient pressure. Quick-cure resins are not
recommended for specimens suspected of delaminations or micro cracks, since the rapid curing of
the resin can heal these defects.

Grinding is done after the specimen has been cut to its optimum size. A typical grinder/polisher has a
platen (or a set of platens) over which the grinding material (SiC paper, polishing cloth, diamond
paste, etc.) is placed. Grinding is often started using a 120 or 240 Grit SiC paper. The grinding
process then progresses through 320, 400, and 600 Grit SiC paper. Each step should remove all the
scratches from the previous step. Rinse the specimen between each step. A properly ground
specimen will only have one surface plane.

Polishing follows grinding. Polishing is very similar to grinding, except that a Texmet, nylon, or silk
cloth with diamond or alumina paste or powder on the surface is used instead of SiC paper. Rough
polishing is usually done using 6- or 1-micron diamond particles. Fine polishing is usually done using
1-micron, then 0.3-micron, then 0.05-micron alumina particles. The total fine polish time should be
short, i.e., less than 30 seconds. All scratches on the cross-section surface should already have
been removed after this step.

Fig. 4. Examples of Grinders/Polishers

 Micro Thermography or Hot Spot Detection

Microthermography or Hot Spot Detection is a semiconductor failure analysis technique used to

locate areas on the die surface that exhibit excessive heating. Excessive heating indicates a high
current flow, which may be due to die defects or abnormalities like dielectric ruptures, metallization
shorts, and leaky junctions.

An inexpensive yet effective Hot Spot Detection technique consists of dropping liquid crystal on the
die surface of a biased device. The bias is chosen such that the defect site is allowed to conduct
enough current to generate the amount of heat needed to change the visual characteristics of the
liquid crystal. This technique is popularly known as the 'Liquid Crystal Technique.'

Liquid crystals undergo several phase changes as the temperature increases. At very low
temperatures, liquid crystals are solid and are said to be in its crystalline phase. At higher
temperature liquid crystals become liquid while retaining the 'crystalline' nature of its optical
properties, i.e., their elongated molecules tend to align parallel to each other.

There are two liquid crystal phases wherein the physical phase is liquid but the optical characteristics
are crystalline, namely, the 'smectic' phase and the 'nematic' phase. At even higher temperatures,
the liquid crystal goes into its 'isotropic phase,' wherein its molecules are randomly located and
randomly oriented.

Only two phases are important in liquid crystals that are commercially available for Hot Spot
Detection, i.e., the isotropic and the nematic phases. When in its isotropic phase, the liquid crystal
appears as a clear liquid, offering no distinctive optical characteristics because of the homogeneous
distribution of its molecules. When it is in its nematic phase, the liquid crystal has a milky
appearance and exhibits optical properties similar to those of crystal structures.

When viewed using an optical microscope equipped with a polarizing filter in the illumination path
and a cross polarized filter (analyzer) in the viewing path, thin films of liquid crystal in isotropic and
nematic phases appear very different. Isotropic films appear black, since the cross polarized light is
blocked by the analyzer.

On the other hand, nematic films appear to be rainbow-colored, since light reflected from nematic
films 'twist' such that they are able to pass through the analyzer. Hot spots raise the temperature of
the liquid crystal, making it appear black at that spot. The die surface of a well-prepared sample with
a hot spot will therefore appear as rainbow-colored, except for the hot spot which will appear as a
blackened area.
 SEM/TEM

Scanning Electron Microscopy (SEM)

Scanning electron microscopy is used for inspecting topographies of specimens at very high
magnifications using a piece of equipment called the scanning electron microscope. SEM
magnifications can go to more than 300,000 X but most semiconductor manufacturing applications
require magnifications of less than 3,000 X only. SEM inspection is often used in the analysis of
die/package cracks and fracture surfaces, bond failures, and physical defects on the die or package
surface.

During SEM inspection, a beam of electrons is focused on a spot volume of the specimen, resulting
in the transfer of energy to the spot. These bombarding electrons, also referred to as primary
electrons, dislodge electrons from the specimen itself. The dislodged electrons, also known as
secondary electrons, are attracted and collected by a positively biased grid or detector, and then
translated into a signal.

To produce the SEM image, the electron beam is swept across the area being inspected, producing
many such signals. These signals are then amplified, analyzed, and translated into images of the
topography being inspected. Finally, the image is shown on a CRT.

The energy of the primary electrons determines the quantity of secondary electrons collected during
inspection. The emission of secondary electrons from the specimen increases as the energy of the
primary electron beam increases, until a certain limit is reached. Beyond this limit, the collected
secondary electrons diminish as the energy of the primary beam is increased, because the primary
beam is already activating electrons deep below the surface of the specimen. Electrons coming from
such depths usually recombine before reaching the surface for emission.

Aside from secondary electrons, the primary electron beam results in the emission of backscattered
(or reflected) electrons from the specimen. Backscattered electrons possess more energy than
secondary electrons, and have a definite direction. As such, they cannot be collected by a secondary
electron detector, unless the detector is directly in their path of travel. All emissions above 50eV are
considered to be backscattered electrons.

Fig. 1. Example of a SEM photo of a

contaminated area on a lead frame; EDX
analysis is usually performed to identify
such contaminants
 EDX Analysis

EDX Analysis stands for Energy Dispersive X-ray analysis. It is sometimes referred to also as EDS or
EDAX analysis. It is a technique used for identifying the elemental composition of the specimen, or
an area of interest thereof. The EDX analysis system works as an integrated feature of a scanning
electron microscope (SEM), and cannot operate on its own without the latter.

During EDX Analysis, the specimen is bombarded with an electron beam inside the scanning electron
microscope. The bombarding electrons collide with the specimen atoms' own electrons, knocking
some of them off in the process. A position vacated by an ejected inner shell electron is eventually
occupied by a higher-energy electron from an outer shell. To be able to do so, however, the
transferring outer electron must give up some of its energy by emitting an X-ray.

The amount of energy released by the transferring electron depends on which shell it is transferring
from, as well as which shell it is transferring to. Furthermore, the atom of every element releases X-
rays with unique amounts of energy during the transferring process. Thus, by measuring the amounts
of energy present in the X-rays being released by a specimen during electron beam bombardment,
the identity of the atom from which the X-ray was emitted can be established.

The output of an EDX analysis is an EDX spectrum. The EDX spectrum is just a plot of how
frequently an X-ray is received for each energy level. An EDX spectrum normally displays peaks
corresponding to the energy levels for which the most X-rays had been received. Each of these
peaks are unique to an atom, and therefore corresponds to a single element. The higher a peak in a
spectrum, the more concentrated the element is in the specimen.

An EDX spectrum plot not only identifies the element corresponding to each of its peaks, but the type
of X-ray to which it corresponds as well. For example, a peak corresponding to the amount of energy
possessed by X-rays emitted by an electron in the L-shell going down to the K-shell is identified as a
K-Alpha peak. The peak corresponding to X-rays emitted by M-shell electrons going to the K-shell is
identified as a K-Beta peak. See Figure 1.

Figure 1: Elements in an EDX spectrum are identified based on the energy content of the X-rays
emitted by their electrons as these electrons transfer from a higher-energy shell to a lower-energy
one
 Focused Ion Beam
Focused Ion Beam (FIB) techniques are used in a variety of applications. In terms of failure
analysis, FIB techniques are commonly used in high magnification microscopy, die surface milling or
cross-sectioning, and even material deposition.

A FIB system works very similarly to a scanning electron microscope, except that it uses a finely
focused beam of gallium (Ga+) ions instead of the latter's use of electrons. This focused primary
beam of gallium ions is rastered on the surface of the material to be analyzed. As it hits the surface,
a small amount of material is sputtered, or dislodged, from the surface.

Fig. 1: Examples of Focused Ion Beam (FIB) Stations

The dislodged material may be in the form of secondary ions, atoms, and secondary electrons.
These ions, atoms, and electrons are then collected and analyzed as signals to form an image on a
screen as the primary beams scans the surface. This image forming capability allows high
magnification microscopy.

The higher the primary beam current, the more material is sputtered from the surface. If only high-
mag microscopy is intended, only a low-beam operation must be employed. High-beam operation is
used to sputter or remove material from the surface, such as during high-precision milling or cross-
sectioning of an area on the die.

Fig. 2: Cross-section of a DRAM cell produced by FIB

A FIB system can also bombard an area on the die with various gases as it performs primary beam
sputtering. Depending on the gases used, these gases can react with the primary beam to either
etch material from or deposit material onto the surface.
 Secondary Ion Mass Spectroscopy (SIMS)
Secondary Ion Mass Spectroscopy (SIMS) is a failure analysis technique used in the
compositional analysis of a sample. SIMS operates on the principle that bombardment of a material
with a beam of ions with high energy (1-30 keV) results in the ejection or sputtering of atoms from the
material. A small percentage of these ejected atoms leave as either positively or negatively charged
ions, which are referred to as 'secondary ions.'

The collection of these sputtered secondary ions and their analysis by mass-to-charge spectrometry
gives information on the composition of the sample, with the elements present identified through their
atomic mass values. Counting the number of secondary ions collected can also give quantitative
data on the sample's composition. Thus, SIMS works by analyzing material removed from the
sample by sputtering, and is therefore a locally destructive technique.

The yield of secondary ion sputtering, which affects SIMS sensitivity, depends on the specimen's
material, the specimen's crystallographic orientation, and the nature, energy, and incidence angle of
the primary beam of ions.

The proper choice of primary ion beam is therefore important in enhancing the sensitivity of
SIMS. Oxygen atoms are usually used for sputtering electropositive elements or those with low
ionization potentials such as Na, B, and Al. Cesium atoms, on the other hand, are better at
sputtering negative ions from electronegative elements such as C, O, and As. The detection limit of
SIMS is severely reduced with improper selection of the ion beam. Liquid metal ion sources are
used for high-resolution work, since these can provide smaller beam diameters.

Since the sputtered ions escape from shallow depths, the sputtering of the sample has to be
prolonged in order to extend the analytical zone of the sample into deeper regions of the bulk
material. Monitoring secondary ion emission in relation to sputtering time therefore allows depth
profiling of the sample's composition. Layers of up to 10,000 angstroms thick can be depth-profiled
using SIMS. Using SIMS as a depth-profiling tool is the dynamic mode of SIMS operation.

Figure 1: Example of a SIMS Spectrum

SIMS offers several advantages over other composition analysis techniques, namely: 1) the ability to
identify all elements, including H and He; 2) the ability to identify elements present in very low
concentration levels, such as dopants in semiconductors.

Of course, SIMS also has its own drawbacks as an analysis technique. Its range of beam diameter
(1-200 microns) is limited, with the sensitivity of the technique suffering as the beam diameter is
reduced, since fewer ions for analysis are sputtered from the material. It also suffers from
secondary mass interference problems and, as mentioned earlier, is a locally destructive technique.
 Die-related Failure Mechanisms and Attributes
Contact Migration

Contact migration refers to the diffusion of the metal atoms of a contact (usually Al or an alloy thereof)
into the silicon substrate. This phenomenon is due to the natural occurrence of interdiffusion between
two different interdiffusible materials in contact with each other, which are Al and Si in this case. This
phenomenon of interdiffusion occurs in both ways, i.e., Al diffuses into Si and Si diffuses into Al. This
is not current-related and must not be confused with electro migration, which is a different mechanism.

Junction spiking occurs when the amount of Al migration into the silicon substrate has reached the
point where in the Al has penetrated deep enough so as to short a p-n junction in its path. By that
time an Al spike is said to have shorted the junction, damaging the device permanently.

The reverse, wherein the Si atoms have entirely penetrated the Al layer above, may also happen and
can result in an open circuit as a result of voids in the metal contact. Silicon aggregates that have
diffused through the Al layer and reached the surface are known as. Silicon nodules are often
observed over the bond pads as small but numerous hillocks, and are known to cause wire bonding
problems as well.

Al migration is usually reduced by doping the Al with Si or Cu or both, forming an alloy that is more
resistant to Al-Si interdiffusion. A barrier metal such as TiW or Pt-Si may also be deposited between
the Al layer and the silicon substrate.

Dielectric Breakdown

Dielectric breakdown refers to the destruction of a dielectric layer, usually as a result of excessive
potential difference or voltage across it. It is usually manifested as a short or leakage at the point of
breakdown.

There are many types of dielectric in a typical die circuit, varying not only in purpose
but in chemical composition as well. The most commonly used dielectric is SiO2,
which is an oxide of silicon. The permanent breakdown of an oxide dielectric is also
usually referred to as 'oxide rupture' or 'oxide breakdown.' The most common cause
of dielectric breakdown in devices with no wafer fab problem is EOS/ESD, since this
can expose the dielectric layer to high voltages.

Non-EOS/ESD-related dielectric breakdowns may be classified into either an early life dielectric
breakdown (ELDB) or a time-dependent dielectric breakdown (TDDB), depending on when in the
device lifetime it occurs. Early life dielectric breakdown, usually occurring within the device's first year
of operation, is just a special case of early life failure (ELF) involving a dielectric layer. A dielectric
breakdown is usually classified as a TDDB if the device has been in operation for at least two years
already. These are just guidelines, because the point at which a dielectric breakdown occurs is not
just related to time, but to other factors as well. ELDB and TDDB failures are usually caused by a
defect in the dielectric layer, such as stray particles which decrease the effective thickness of the
dielectric making it prone to breakdown.

Since SiO2 is a very common dielectric material, its breakdown mechanism has been understood
over the years. SiO2 breakdown is believed to be due to charge injection, and may be broken down
into 2 stages. During the first stage, current starts to flow through the oxide as a result of the voltage
applied across it. High field/high current regions are then formed as charges are trapped in the oxide.
Eventually, these abnormal regions reach stage 2, a critical point wherein the oxide heats up and
allows a greater current flow. This results in an electrical and thermal runaway that quickly leads to
the physical destruction of the oxide.
Electrical Overstress (EOS)

Electrical Overstress, or EOS, refers to the destruction of the circuit because of excessive voltage,
current, or power. EOS damage is usually very obvious. Metal lines are discoloured,
burnt, or melted (see photo on the right). Thin-film resistors are severed, with the
severing usually showing up as straight, whitish lines. Transistors and diodes exhibit
metal migration from one terminal to another. The glassivation may even show
mechanical damage.

EOS is usually caused by improper application of excitation to the device, whether it's still being
tested in the manufacturing line or it is already in the field. Simple socketing violations such as device
miss-orientation and shifting can cause EOS damage, especially if the voltages intended for the
power supply pins will be applied to stress-sensitive or power-limited pins. Improper excitation
settings or voltage spikes in the excitation source are also common causes of EOS damage.

EOS damage is not always obvious though. Some EOS events leave no apparent physical
manifestation on the die surface at all. Such EOS events can still render the affected component non-
functional, even if no physical anomalies are observable. Weak EOS events may also occur, simply
shifting the parametric performance of the affected component, but nonetheless affecting the over-all
performance of the device.

Latch-up and Electrostatic Discharge (ESD) are special cases of EOS, and are discussed in more
detail as separate failure mechanisms in this reference.

Electrostatic Discharge (ESD)

Electrostatic Discharge, or ESD, is a single-event, rapid transfer of electrostatic charge

between two objects, usually resulting when two objects at different potentials come
into direct contact with each other. ESD can also occur when a high electrostatic field
develops between two objects in close proximity. An ESD event can damage a device
in many ways, e.g., conductor fusing, metal-resistor severing, junction damage,
dielectric/oxide ruptures, etc.

There are three (3) ESD models that are widely accepted in the industry today. These are the Human
Body Model (HBM), the Charged Device Model (CDM), and the Machine Model (MM). The HBM
simulates the electrostatic discharge of a person touching an IC at a different potential. The CDM
simulates the discharge of a device charged to either a positive or negative potential when it touches
a conductive surface that is at another potential. The MM simulates the discharge of a machine or a
tool when it comes into contact with a device at a different potential.

Gate Oxide Breakdown

In a MOS transistor, the electrical characteristics of the channel through which the carriers flow are
controlled by a gate. This gate is isolated from the channel by a thin layer of oxide. Gate oxide
breakdown is therefore simply the destruction of this dielectric layer. Gate oxide breakdown is also
sometimes referred to as gate oxide rupture, and often manifests as a short or leakage path from the
gate to the channel or substrate.

Gate oxide breakdowns are usually caused by (EOS) or electrostatic discharge (ESD), although
imperfections or defects in the gate oxide layer can also lead to its early life or time-dependent
breakdown. These defects may be in the form of mobile ions, stray particles, or insufficient coverage.
Hot Carrier Effects

The phrases 'hot carriers' and 'hot electrons' refer to highly energetic carriers that result from poor
design of the device, high source-drain voltages, and high channel electric fields in MOS devices.

A high voltage across the source and the drain of a MOS device will accelerate channel carriers into
the drain's depletion region, causing them to collide with lattice atoms that result in electron-hole
pairs. This phenomenon is known as impact ionization, with the displaced e-h pairs also gaining
enough energy to propel some of them towards the gate oxide of the device and trap them there. A
high gate voltage can also pull hot carriers into the gate oxide and trap them there before they even
reach the drain region.

Trapped carriers or charges in the gate oxide can shift the threshold voltage and Trans conductance
of the device. The excess electron-hole pairs created by impact ionization can also increase
substrate current, which in gross cases can upset the balance of carrier flow and facilitate latch-up.

Junction Burn-out

Junction burn-out refers to the destruction of a p-n junction as a result of excessive power dissipation
from an (EOS) or electrostatic discharge (ESD) event. It is usually in the form of a silicon meltdown at
the junction itself, causing the junction to become open or shorted.
.

Metal Burn-out

Metal burn-out refers to the gross destruction of a metal line from excessive current or power
dissipation. This is the most obvious attribute of gross electrical overstress (EOS) damage, although
not all EOS-damaged devices will exhibit a metal burn-out.

Metal burn-outs are often accompanied by carbonized plastic, metal reflow, and
discoloration of the metal around it. Metal lines that become open after a metal burn-out
are said to have 'fused.' The photo attached to the article on EOS shows metal burn-
outs. On the right is another photo of a failure site with metal burn-outs.

Mobile Ionic Contamination

Mobile ionic contamination refers to the presence of mobile ions such as Na+, Cl-, and K+ in the
device structures of an integrated circuit. These mobile ions can come from the environment, humans,
wafer processing materials, and packaging materials.

Mobile ionic contamination is commonly observed in the gate oxide of a MOS transistor. These ions
can accumulate and cause charge build-ups that can shift the gate threshold of the MOS
transistor. Inversion channels may also form in MOS transistors. In bipolar devices, mobile ions can
affect carrier concentrations, changing the beta of the transistor.

Mobile ions respond to temperature and voltage, so failures due to mobile ionic contamination can be
accelerated by burn-in. Mobile ionic contamination failures can also be made to recover by subjecting
the device to unbiased bake, since this will redistribute the ions by promoting their random
movement. Thus, a device is most likely a mobile ionic contamination failure if it fails after burn-in but
recovers after unbiased bake.

Slow Charge Trapping

Slow charge trapping refers to the long-term retention of electrons in the gate oxide of a MOS device
due to the presence of imperfections in the gate oxide interface. These imperfections or 'traps'
include structural damage, defects, and impurities in the oxide. Thus, improved oxide growth to
minimize trap density will minimize the occurrence of slow trapping.
Slow trapping is prevalent in memory devices that require carrier movement in the oxide for proper
operation. Trapped charges in the oxide can shift the threshold voltage of the device.

Silicon Nodules are silicon aggregates that come out of silicon-doped aluminium metal lines,
causing the device to fail in several ways. Here are some key points about silicon nodules:

1) The aluminium metal lines used in die circuits are doped with silicon atoms in a very controlled
manner to enhance their properties. A typical process involves sintering or alloying at 400-450 deg
C, wherein the aluminium lines are doped with about 1-2% silicon.

2) During this alloying process, not all of the silicon dopants are dissolved in the aluminium metal
lines. Instead of going into the solution, some Si atoms remain as silicon precipitates. Only about
0.4% silicon dissolves in the aluminium solution.

3) As the metal is cooled down after the alloying process, more silicon atoms separate from and
come out of the aluminium solution.

4) The elemental silicon precipitates existing in the metal (as discussed in # 2) act as nucleation
sites for silicon atoms that emerge from the solution during the cool-down phase. The silicon atoms
that nucleate eventually form larger aggregates of silicon that are known as silicon nodules.

5) Silicon nodules grow bigger with long exposure to elevated temperatures. Studies have shown
that silicon nodules can attain diameters greater than 1 micron.

6) The growth of silicon nodules to large diameters exert stress on the metal lines. In fact, narrow
metal lines, i.e., those whose widths are less than 3 microns, can fracture and become open in the
presence of silicon nodules with diameters greater than 1 micron. This phenomenon is often
referred to as 'aluminium stress cracking.'

7) Aluminium stress cracking is aggravated by factors other than silicon nodules. During sputter-
deposition of the aluminium, for instance, nitrogen may be trapped within the layer, producing
additional strain on the aluminium. Differences among the coefficients of thermal expansion of
silicon, silicon dioxide, and aluminium also result in stresses within the die circuit that can aggravate
aluminium cracking.

8) Aside from aluminium stress cracking, the formation of silicon nodules on bond pads also
impedes wire bonding. As a result, excessive silicon nodule formation on bond pads has been
confirmed to cause ball bond lifting issues as well.

Electro migration refers to the gradual displacement of the metal atoms of a conductor as a result
of the current flowing through that conductor. The process of electro migration is analogous to the
movement of small pebbles in a stream from one point to another as a result of the water gushing
through the pebbles.

Because of the mass transport of metal atoms from one point to another during electro migration,
this mechanism leads to the formation of voids at some points in the metal line and hillocks or
extrusions at other points. It can therefore result in either: 1) an open circuit if the void(s) formed in
the metal line become big enough to sever it; or 2) a short circuit if the extrusions become long
enough to serve as a bridge between the affected metal and another one adjacent to it.

Electro migration is actually not a function of current, but a function of current density. It is also
accelerated by elevated temperature. Thus, electro migration is easily observed in Al metal lines that
are subjected to high current densities at high temperature over time.

Electro migration is widely believed to be the effect of momentum transfer from the electrons of the
metal, which move according to the applied electric field, to the ions that constitute the lattice of the
metal.
There are two major driving factors that make electro migration happen: 1) the direct action of the
electric field on the charged atoms or ions of the metal; and the 2) frictional force or momentum
exchange between the flowing electrons and these ions. The total driving force is the sum of the
effects of these two factors.

All metal films have imperfections or microstructural variations that cause the atomic flow rates
through them to be non-uniformly distributed. This non-uniform atomic flow rates (or flux divergence)
through different sections of the conductor result in mass depletion (which causes voids) and mass
accumulation (which causes hillocks) as the mass transport mechanism occurs during electro
migration.

In Al films, the dominant mechanism of atomic migration is along grain boundaries and
surfaces. Lattice mismatches (such as those between adjacent large and small grains or when three
grain boundaries meet) can create grain boundary interconnections that provide shorter paths for the
atoms, enabling the latter to move faster through the film.

Another important thing to note regarding how grain structures affect electro migration failure rates is
the conclusion from various studies that below a critical value for the metal line width, electro
migration is impeded. Electro migration failure rates predictably decrease with decreasing line
widths, but up to a certain point only.

At the critical limit, the width of the metal line becomes smaller than the grain size itself; such that all
grain boundaries are now perpendicular to the current flow. Such a structure is also known as a
'bamboo structure.' This results in a longer path for mass transport, thereby reducing the atomic flux
and electro migration failure rate.

There is also a critical lower limit for the length of the metal line that will allow electro migration to
occur. Known as the Blech length, any metal line that has a length below this limit will not fail by
electro migration. Thus, the Blech length must be considered when designing test structures for
electro migration. Otherwise, no failures may be observed, leading to an incorrect conclusion.

Electrical Overstress, or EOS, is a failure mechanism wherein the device is subjected to excessive
voltage, current, or power. Electrostatic Discharge, or ESD, is a special type of EOS mechanism in
the form of a single-event, rapid transfer of electrostatic charge between two objects. Many people
distinguish ESD from other EOS-related but non-ESD mechanisms, so this discussion will do the
same and refer to ESD as a separate mechanism from conventional EOS.

EOS and ESD can destroy a semiconductor device in many ways, resulting in observable signs of
damage or failure attributes. There are, however, three (3) frequently-encountered and basic
mechanisms by which a device is damaged by EOS or ESD. These mechanisms are: 1) dielectric or
oxide punch through; 2) fusing of a conductor or resistor; and 3) junction damage or burn-out.

Dielectric or Oxide Punch through

Dielectric or oxide punch through refers to the EOS/ESD mechanism involving a voltage pulse that is
large enough to rupture an oxide or dielectric layer. This problem is prevalent in MOS circuits
because the thin oxide isolating the gate and the channel of the MOS transistor can easily be
'punched through' by large voltage spikes. Trends in new fab processes that lean towards thinner
oxide layers also aggravate the occurrence of this mechanism.

A typical dielectric punch through event may occur in the following stages: 1) a high voltage spike
occurs between two pins connected to opposite sides of a dielectric layer, in effect applying a large
potential difference across the dielectric layer; 2) the breakdown voltage of the dielectric layer is
exceeded by the large potential difference across it; 3) the dielectric breaks down and starts
conducting current; 4) adiabatic or localized heating of the dielectric at the point of current conduction
occurs; and 5) the conduction site melts down forming a filament that shorts the metal layer above
the dielectric (connected to one of the pins) and the metal layer below the dielectric layer (connected
to the other pin).
Figure 1: Photo of an oxide punch through after the top metal layer has been removed

Dielectric punch through is minimized by using adequate ESD protection circuits and prevention of
EOS occurrences, such as the inadvertent or random generation of voltage spikes in the circuit.

Die scratching is a failure mechanism wherein the surface of the die is mechanically damaged by a
rigid object that is accidentally dragged across or moved over it. Die scratching usually results in
gross abrasion, scraping, or laceration damage on the die's active circuit (see Figure 1). The
damage itself is referred to as a 'die scratch', while the damaged die is referred to as a 'scratched
die.'

Die scratches are caused by mechanical means, usually by mishandling. 'Mishandling' in this context
also includes the improper or careless use of tools and accessories used by an operator while
working. It is common to see die scratches that resulted from a pointed object such as a probe
needle or tweezers accidentally touching the die and sweeping across its surface.

Scratches that reach the active circuit beneath the glassivation will immediately lead to electrical
failure due to shorted and open metal lines. Metal shorts are commonly seen in narrowly-spaced
metal lines, wherein the displaced metal materials bridge the lines together. Open circuits are often
induced in narrow, isolated lines.

Shallow scratches on the die that do not reach the active circuit will not cause immediate electrical
failure, but may pose reliability risks if the top passivation has been breached. For instance, the
seepage of moisture and contaminants through a damaged portion of the glassivation can result in
die corrosion.

Figure 1. Optical photo (left) and SEM photo (right)

of die scratches
Die scratching can occur anywhere from wafer fab to assembly prior to encapsulation. Picking up a
die carelessly with a tweezer for eutectic die attach can result in the tweezer slipping out of position
while scratching the die surface. Improper equipment set-up can cause probe needles, die overcoat
dispense tools, and the like to land on and scratch the surface of the die.

Foreign materials and dirt embedded at the pick-up tool tips of pick-and-place machines during die
attach can also cause die scratches. Similarly, the use of defective, worn-out, or damaged pick-up
tools can scratch the die surface. Manual capping of ceramic packages prior to sealing may also
cause a die scratch, if the cap or lid inadvertently gets into contact with the surface of the die.

Die scratches are quite easy to confirm by optical microscopy, since they truly resemble scratches
seen every day in common objects.
Corrosion is the degradation of metals as a result of electrochemical activity. The process of
corrosion requires 4 components for it to occur: 1) an anode; 2) a cathode; 3) an electrolyte; and 4)
electrical connection between the anode and the cathode. Thus, the key to corrosion prevention is
the elimination of at least one of these components. The presence of an anode and a cathode
implies that there is a potential difference between them, i.e., the anode has a greater tendency to
lose electrons while a cathode has a greater tendency to gain them. The presence of this potential
difference is the primary driver of corrosion.

The anode is the metal or site with a higher potential to oxidize (lose electrons). Thus, a metal
x+
undergoing corrosion is said to be 'anodic' if it is where the oxidation reaction takes place: M M
-
+ xe . The anode is often one of the following:
1) The more active metal;
2) A stressed region such as a crack, a scratch, a grain boundary, or a deformed structure;
3) An area that is starved of oxygen; and
4) An area with variations in its composition.

The cathode is the metal or site with a higher potential for reduction (gaining of electrons), or lower
tendency to oxidize. It is often one of the following:
1) A noble metal;
2) An unstressed region;
3) An area with high oxygen concentration; and
4) A non-metallic component.

The electrolyte is the medium through which ions may move, the most common of which is water.

Die Corrosion

Die corrosion refers to the corrosion of the metal areas on the surface of the die. Aluminium (Al)
metal areas are the most prevalent on a typical die circuit, so Al corrosion is quite
commonly encountered. Other thin-film layers on the die such as sichrome resistors
can also corrode. Gross cases of chemical corrosion can lead to either electrically open
or electrically shorted metal lines, with the latter being due to corrosion by-products that
can bridge two metal lines together. Corroded metal lines appear dark under an optical
microscope (as shown in the picture on the right).

Chemical corrosion of Al is triggered by the presence of moisture and contaminants on the die
surface. Corrosion of Al can occur whether it is acting as an anode or as a cathode. Al bond pads,
being un-glassivated, are more vulnerable to corrosion. However, corrosion can also occur in
subsurface Al lines that are accessible to moisture by imperfections in its protective glassivation or
inter-metal dielectric layers.

Corrosion is often a result of many wafer fab or packaging contamination problems. Improper rinsing
or excessive use of corrosive contaminants such as P, S, and Cl during wafer fab can make the die
highly susceptible to die corrosion. Packaging and passivation defects that allow excessive ingress
of moisture and contaminants into the die can also lead to die corrosion. The use of plastic moulding
compounds with corrosive ingredients and the use of die attach material that exhibits resin bleeding
of corrosive contaminants may likewise trigger die corrosion.

Fig 1. SEM photo of Fig 2. Photo of a corroded bond

corroded aluminium pad that exhibited ball lifting; this
metal lines corrosion was caused by Cl
contamination