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  • (1992) (Ieee) - Design and Implementation of A Robot Control System Using A Unified Hardware-Software Rapir-Prototyping Framework

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    Design And Implementation Of A Robot Control System Using A Unified Hardware-Software Rapir-Prototyping Framework

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    (1992)(Ieee) - Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapir-Prototyping Framework

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    Design And Implementation Of A Robot Control System Using A Unified Hardware-Software Rapir-Prototyping Framework

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    © All Rights Reserved
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    Download as pdf
    7 views4 pages

    (1992) (Ieee) - Design and Implementation of A Robot Control System Using A Unified Hardware-Software Rapir-Prototyping Framework

    Uploaded by

    Erico Antonio Teixeira
    Design And Implementation Of A Robot Control System Using A Unified Hardware-Software Rapir-Prototyping Framework

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
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    Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapid-Prototyping Framework Mani B. Srivastava, Trevor I. Blumenau, and Robert W. Brodersen EECS Department, University of California at Berkeley Abstract The increasing complexity of applications and the relative ‘maturity of CAD tool for ASIC design have made design aids forthe higher-level aspects of system design essential We have developed a unified framework forthe rapid. protetyping of hardware and sofware for applicaion-specif systems. Tis framework is flly described in [1]. The application ofthe {framework to the development ofa real-time multisensory robet control system is described in this paper 1.0 Introduction ‘The negraion of erogenous haar oftware and elector anal comments fom a complet sym rams a chalenging sign robin Compute ied deg cigs ae rive a ‘he sys el when compre thee aval a he chip evel. Pr ‘is searchin CAD has purty concn nthe design of nd appa spec Cs (ASIC) ands avid aking ates ot forthe dexgn of ott chips, bt boars and software as wel Denas abut the CAD framework cn be faa elsewhere] Tn tis paper we rere the sign of el ine mi sory ob onl sys using our sem rapt romping fanework. The Ky fears of tie compu aided system design mebodologyoeed by ‘ot famework a exemplifod trough ths system. The sytem com ‘nls, ineal-ime, asx degree of freedom aco obra sing aston fre an proiny sing In aon tthe novel system design metadclogy, smother key ‘spectofterbot contol sens ti eumsve ws of cil He evict hardware, mace ese by our syste evel rapid ny ing framework. This provides much improved prfomance ver corr ‘mercial and ther eeach robot core sytney tad ‘ward geen pupoes compe, 2.0 Framework for rapid-prototyping of hardware and software ‘We ive implemented a sign tamewer [I] for dose bs Jove sams wich ses a nied view for he hardwae and oftware ‘component hat make up a system, As shown in igure I, an labo. ‘eine folowing sibeecons, a high evel peicaton of ys 1068-640452 83.006 1952 1588 a tenis imple asst of cum red cet bare wing ami of software programmable and non programmable hardware and ASIC, going tough saps of schitetre mapping, breve hard ‘ware module arse sofware module paso. 2.1 System specification ‘The rp sym is viewed by te wer a parameter, tc, ierarchical eter of sequential processes hat operat concent, ad ime sing well deed communication mec. Systems of est tous, sahas arabs comer r spect ogra ses ‘lage ganar prin, and arena expensed a et ‘of processes communicating va mesage ques This lo event ‘fom de fact tha he system twee frac seme poking, ice custom distbated eal sine OS. Cammunication is one ng FIFO camels at comet inp and out prs cn he press. 2.2. Architecture mapping In acho mapping each proces in he cig deseiption it agpd sero afar proces ramingon a roganmabl oc Sor module, oro a Aandwar proces ting on a dedicated easton, haere module. pla mapping bed apprach sted in which the proces network is partond i arama echiectr et- pla The template prunes and the peroning re mally pect fx alhough he Wb parning ecu present in[2] maybe _lajabl wanna pr of his ce “The wehiteaze epi, shown in Figure 2 has ayer iad- ae hie wih aerial bus natin fr increased band with The are fuer in be rece, The bot vo jer of {heir ae sumed yeast bar Each em bord has ne cot mere proparunablepocesor mode ming ares OS ke ‘nl, and cooing umber of ppicaon speci ave maxes wi stndard hardware ae software interfaces, These live modes fo dhe lowes ayer ofthe ira al cn be eer dedi cs ‘om hardware modules or ected software proganmuble modus. ‘Tecasom boars ese on aback plane usa we slves ante roczsormaduerumingarealtie OS which fms th scene aye terry The prosesing modern caso bor com nea and scone wih th maser yer 2 poceing ode wing | sundae intefae and software proecol. The apt yer ‘ofthe hierarchy i fomed by & UNIX werksaton tit communis with he layer 2 processor over a network utng standard prac, ‘Compassion power, the communicaon bandwith andthe ait © ‘ent reli cms inease a one gps down hs layered ci secur ienpe 2.3 Board-level hardware modules ‘The ames provides sv bor ee mae gmeaon as vw eser. We we the same danse end dexgn manage ols as ese fo ASICs, soa he vaio peeing ASIC geen els sme nary avaiable as special cae tour-evel module persons ‘Thine asikom asembier (LAGER [3.x compar (C0 ‘Slicon faa behavioral eyes ryt (HYPER (SD. ‘A key component of cr toad eve hardware module gneaon seagy ia very exis bear of ressbe pretrial subystem modules. This includes a variety of complete processor ‘modules, mamarysubysiems, data sepsion teyns, Du ie face modes, Sher op commniaton mode, ating mats e Fer example, TMSS20C30 proceso moduein he Bry proves ‘complete iccomputr based rnd a power DSP wns config ain items of memory pmizatn, YO dvs, end ht ices permed, ‘Tis rary enables sub-system evel eb, nds ese ‘poring the achtecue trate sracgy deat eter The sy ‘em architace template is essentially a parametriod network of Iirmy modes. ‘To nce the design of bord level moles, stun desrp- ‘ion language wih isp based pramesrizaon fits, ols 10 30 ‘oar evel aomasicneraciveisr speieding bed paconert ‘crating anda bolo map abhor deeripton oa nels o> _gammable devies, such a FPGAS, are alto provided. An inecace Sybex system ALOHA (6 hs bon grado provide by ‘Dynes eras been Var modes chs ep merry iui ora VMEbus. 24 System software modules Many processes in the eiginal process network desrpion othe sytem a implamera softwar process, Sever f hse te cess cn mipioa poceser mate ‘Tealw anion mapping of tse sofware roost evr. ‘System Spectction wae Simuae rama “mio” J | gee SEE, ober a ada al osu Sone oman ewan tweed te T tanto = t T cob Event Cote FIGURE (Overview oft CAD Frmener for Sy Level Design FIGURE 2: Layered Artitcare Template. ous programmable processor male in he Wray, weave sand ‘and na set felicia e mliking ke fre pce modules, All software locks inthe system descrpon ae mapped [reese on on ofthese elms keels whch alo provide tar implemening he chal based communication prea. Eah ba ware process lo has a wraper software proces ruting oh he Fr gammabl proceso to which itis tached. This resin nior intact each proces, wheter it boars star a fal aes cay mga of nos btn tarda and stare ‘Spi software ress erro he varios proces males 10 vida consent ra-me envont for eres fe VO, progam dng eT s vl by proctor ie of ma mekemes, Atprecr freer spor ross mode based cand ‘TMS320C30, MC36002, DSPSEC, MCSH020 and SPARC, ogeber ih comespnngkemel Fo example, wee SPOX elie keel forte TMS320€30 module, sn VDI (simple ome rown a rel forthe DSPIOC module. 3.0 Application to robot control system In sharp conras wo architects based round general pupose Imogene shred memory MIMD ml rocesor wth of ae U boards ta pica of most sae ofthat ob conte ems (8]9).ow eanom seer approach oles mach improved pero. ‘mance in amore compact pacage The sina obo conan not only have high ease compton requirements, Btls eed exensve seized 1O capil, This etic he core based snare geal purpose machines wi ied UO capabilites spe ‘ongolmettaniss, rw narrealne again et benches st. Roberic coro lori have become far mere compil an te snp PD on cobs be past Sa of te at yes ica oredr and postion console emneines bah rain tthe ‘ame tine (10). Poston con is generally wed wen he ob does ‘ot touch anyting However, for asin which the robot aces an bjt, force cena is alnst neces (1], For eumpl, ecto lus of raping pit om a sare canna be ely pefomned sing & aston cone -any err inthe sysem canbe catasngtic. Thebi- ‘yt specify a a contol np the desired force against the srface sees obi, ‘We use «fom of fore conte called impedance cnt (12) in hich he force api bythe robot n-taris roproal one ispacemer from is gol psn. This syste is salar to a 57g, ‘wher F= K+AX. This ype of enter is wel sta to tusks such reintolimerions using amemoe car of compliance as ropes 1 [13] Fipze3 shows an exremelysinplifed proces netwak vow ol tesysem. Lineariaon of th rbot congo algorid is bast on he aula ‘om of compte ini, Cails, and gpavistonal es el hse ‘em hve tbe upd a a esnably high ue. There el ‘umes fre formations nd writ conversions ha mst pet xmas th conta oop Ata higher ve «joy can r- 23 continuously monitors the proximiy sensor, and update he ‘moi ips, Crain be hardware arciete mut be deged 3.1 Architecture of the system ‘The esking wehtecure ofthe robot contol sytem shown in Figure 4 Its an instantiation ofthe layered archer template decribed in secton 22, and consis two esto obec boards The ‘Satis contol boar which n tum communicates with extom ‘rip toar sing a her ope ink. Tsp board nafaces ‘wh be jt mots and carer ssa in herb am The conor ‘oad alo communicates wi foe, pion snd ober senses. 3.1.1 Robot controller board ‘This isa casiom baad wo which heroes elated wth conta law, poston, velo, fores and caret sensing and moo ve are aged. pas layers 3 ae 4 the eiicue emp cise secon 2.2. There two processor maxes toa! snd he 33 MF ‘TMS320C2, power floating pie signa proce The wo TMS ooeing modes ae dsingished by he Kd of sve modes tat ‘hey have: These seve modules rele he specie queens fe rbot crema ks. ‘TMS procesor mle #1 has hee ses. Fin sa poe pro- ‘ganmble proceser module based wound 450 MHz DSPA2C which ‘Ss deca othe tajacory calulation proces. The second slave Ser optic bsed communication link connect the ober peripheral ward at tor nd al serves a an ere othe robot maa is twat apy specie volags rapes he may ese fe ma cures, dw agpty tak tothe robe The ASIC ape the tooo proces employs en asynchronous design mehology, nd famaorsom FIGURE 4: ingienenntencf be Robo Conta yer. as synthesized using the interface synthesis ol. The tid seve ‘Muched io TMS processor module # spoon veloc sensing ‘module. The ASICS es male were totaly generated fom | perametznd sucarl Gesripion ‘The cond proces mode, TMS proces male #2, ha te steve. The ft siveis a DSPIOC bed proce mode Kenta ‘be one atachad io TMS procesor mode #, This however ded ‘ated tothe proces cacalang the Forward Kinematics endl he aco ‘anf tie robot arm. The cond save i the fre sensor mode at ‘nara ita sain gauge be force are senng west The id modules th pon velocity sensing module, wich isin fa share ih be TMS proceso mote. ‘The board was fabricated as 9U VME slave board and is fly funeonal Pinay a ares of be mode grease, at ‘be subsystem vel Hay, is complex 50+ component 12" 14" ‘own hada design cyl of es han wo moni, Purber,oce fo Jows he hoc tpi, sytem twee vas confged it inveylietine 3.1.2 Robot peripheral board ‘Thistomisrealy prof eobcxin ai prove nce whe ‘bot ot mots and ks. Bs kis recie volage rien va ‘es fom the contol bard ane apy them the rb mote, FIGURE 3: Serie View of te Robt Contl Sym sexs the motor cent ano spy the takes incase of sls cr When cremated ‘Tne oases AD DVA, dopa commiaicaton modes fom the apy module tray. The rooea prcesor ae synbeszad sing the ALOHA tol, wil he digi pulse-width modulators implemeried with be FPGA module generar Only sl! nog ‘ariono heb (opamp based fies ha be cn designed fot ‘his bow he est was eiderasomatly gener cristata ‘fom the reusable parametrized subeysem liar. AS eros of his Joel of atomssion teenie development ce fom np ceciption "ie working board was pan san to ont, 3.2 Organization of software processes Due the inbeent large gne pails preset in te robot enol syste, it i easy decomposed ito a network of processes. Sameof tne proceses a hardware proces in ha hey Rn on own dette hardware. Oder however te infeed os she Process and ee mappedo ene of he seve swe ograt Nae rczson svalaen he pte hers of echt whee ey ner de coro of kee ‘The SUN workstation ine tp lye runs ase inte process ‘at proves an nerve caver bad on tp of Cree A rary of rbot pce snes proves nner tthe ower Jevetsof he conta sen and alow the wri swich between ped ‘2ce canto an postion cent mode, cia ther ad eo ha, ute the gal sate ofthe obo (esto, fed pp pi motion jc. ‘The MO6820 tus procera be soon layer sessile for

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