Professional Documents
Culture Documents
1527
1527
Prof. Guang-Zhong Yang
!
gHegDeep N-well
~
H'?2
103
103e-learning2
IC2
dH
/ http://www.cic.org.tw/cic_v13/login/login.jsp
CIC Y
(CIC)
(NDL)(ITRC)
(uSAT)
6 27
(MEMS)
UL
155
H'? 2
Prof. Guang-Zhong Yang
Professor Yang
H'? 3
!
103
103
CMOS
(
)
H'? 4
gHegDeep N-well
(noise)VDDGNDDeep N-
wellwellwellDeep
N-wellFig.1CICwellDeep N-
well
Fig. 1
H'? 5
Deep N-well
Case 1Fig. 2(a)
Deep N-wellPMOSN-well
(PMOS1PMOS2)NMOSP-wellFig. 2(b)NMOS
noisePMOSbody
Fig. 2(c)(a)NMOSDeep N-
wellNMOSDeep N-well
H'? 6
Case 2 IC 2 VDD Fig. 3(a)
VDD Deep N-well VDD1VDD2well
VDD1VDD2VDD1VDD2
H'? 7
Case 3Fig.4(a)PMOSbodysource
Deep N-well bodysource
wellVDDVDD
Fig.4(b)(a)NMOS Deep N-well
NMOSDeep N-well
3 Deep N-well
H'? 8
2014H'?(CIC)
(CIC)
20148588
CICCICMorSensor
CMOS MEMS
2014
!
CIC:
http://www.cic.org.tw/CIC_Workshop_2014
201485() 15:30~20:30
1F
03-5773693 ext.155
E-mailworkshop@cic.narl.org.tw
2014 CIC
14:00~15:30 LB
15:30~15:35 /Lr
15:35~16:00 - H / Lr
16:00~16:20 CIC.. / L : Lr 1F
CIC Special
+
Session FPGA Duob[9MorSensorE. (260)
16:20~16:40
L : L CICb[
l
16:40~17:10 Q&A 303 (1F)
Reception Dinner'
17:30~19:00 CIC LB
T:TCICb[l
H'? 9
:
: CIC
852014
CIC Reception Dinner
(17:30-19:00)
:
/
Apple mini 16GB Wifi+3G 1
1
SONY SmartWatch 2 SW2 1
Asus ZenFone 5 1
Apple mini 16GB Wifi+3G 1
GPS 1
SONY 1
Asus Memo pad7 16GB 2
Asus ZenFone 5 2
//
Acer 10 1
2
CIC 5
: CIC
8/6-8/7 VLSI/CAD
CIC(4)
( : 8/6 PM15:30 ; 8/7 AM10:30 )
H'? 10
103CIC$!
~ke'T!!
1033660
1.
(HSA Foundation)
AMDQualcommARMMediaTekImaganation
TIOracle HSAHSA Platform System Archi-
tecture Specification HSAIL - The HSA Programmers Reference Manual HSA Runtime
2.
CIC MEMS measurement tool introduction CICMEMS
White Light Inteferometer()In-plane Vibration Analyzer (
)Laser Doppler Vibrometer ()Desktop Scanning Electron
Microscope ()Nanoindenter ()
3. (3D ICs)
1.CIC
2.CIC
[]
C10307D07C10309D15CF(C9:00~17:00)
2
CICABa268
CIC[a492473
'H'?607
[W5511
1036D11C()10:00F
9
2
7 d'?&O(Yg
&(
g(q)
103($g)
H'? 11
g(q)
103$)d
%]yN(
s
5)
Bw 9
d'?0SK0
d'?)
T9 03-5773693 141
E-Mail: cic-isd@cic.narl.org.tw
9! 03-577-3693144 E-Mail:
1.
2.
3.
4.
5.
q
103
(NTD)
C001 Circuit Simulation and Analysis with HSPICE 1400 3600 150
C002 Analog IC Design using ADP and Laker 2100 5400 450
C003 Physical Verification with Calibre 1400 3600 270
/
C004 Full-Custom IC Design Concepts / 2800 7200 500
Mixed-Signal IC Implementation and Verifica-
C005 tion 2100 5400 200
C010 IC 0 150
C101 Cell-based IC Implementation and Verification 1400 3600 250
/
C102 Verilog 2100 300
C104 Logic Synthesis with Design Compiler 2100 2 250
C105 HDL Debugging with Verdi / 1400 3600 150
Cell-Based IC Physical Design and Verifica-
C106 tion with SOC Encounter 2100 2 200
H'? 12
Post-Layout Simulation Verification with
C109 1400 3600 180
Nanosim
Cell-Based IC Physical Design and Verifica-
C111 tion with IC Compiler 2100 2 250
C115 PrimeTime Signoff 700 1800 150
C201 RF Measurement 700 1800 180
C203 Design of RF CMOS IC 1400 3600 250
C204 Spectre RF 700 1800 150
C205 ADS Circuit 1400 3600 180
C207 ADS Momentum 1400 3600 180
/
C209 CMOS/IPD 700 1800 150
High-Frequency Communication System
C210 Measurement 700 1800 150
C211 PCBPADS Logic 700 150
C212 PCBPADS Layout 1400 150
C213 3DEMPro 700 200
C303 FPGA Design Fundamentals(for Xilinx) 1400 2 450
C304 FPGA Design Fundamentals(for Altera ) 1400 3600 450
Design for Testability with DFT Compiler and
C401 TetraMAX 1400 3600 200
C404 Analog Measurement 700 1800 180
C509 Hardware/Software
Co-Design in ESL / 0 150
Environment
C512 System Verilog 1400 3600 200
C514 700 1800 350
C601 CMOS MEMS Design and Simulation 1400 3600 300
C606 Sensor Readout Circuit Technology 700 1800 180
/
C609 CIC MEMS measurement tool introduction 700 1800 150
C701 T25HV 350 900 150
/
C801 (3D ICs) 700 1800 150
1.
2.
103
H'? 13
H'?
103e-Learning2
103
: CIC(http://www.cic.org.tw//
)
: 1038410:00103824
: http://www.cic.org.tw//e-Learning
:
:
: 03-577-3693144 E-Mail:
9 11
8/4~8/24 10/6~10/26
9/1~9/14 11/03~11/16
103E001-C HSPICE
103E002-C Full-Custom IC Design Concept
103E003-C RF CMOS IC Design
103E004-C Verdi fundamental and Siloti full-chip-simulation training
103E005-C LakerADP+LakerL3 SDL flow training
H'? 14
103E006-C Advanced Design System - Fundamentals
103E007-C CMOS BioMEMS Sensing Technology
103E008-C Sensor Readout Circuit Technology
103E009-C RF
103E010-C Advanced Design System - Momentum
103E011-C Digital IC Testing Step-by-Step with Verigy 93000
103E012-C Step Into Electronic System Level Design
103E013-C FPGA Design Fundamentals for Altera
103E014-C Logic Synthesis (Synopsys)
103E015-C Cell-Based IC Physical Design and Verification with IC Compiler
103E016-C Brief Introduction of Cell-based Design
103E017-C T18
103E018-C TSMC 0.35UM
HSPICE
.gHSPICEP
9
1.HSPICEd
2.
3.3
4.S
5./q
HSPICEg@R
Inside Spice: Overcoming the Obstacles of Circuit Simulation
The Designer's Guide to SPICE and Spectre
SPICE - A Brief Tutorial
http://www.seas.upenn.edu/~jan/spice/spice.overview.html
d 9gHSPICESPICE3
q
(
H'? 15
Full-Custom IC Design Concept
wE5.IC
M{
1.IC
2.m
3.9
4.CAD/EDA Flow
gw539(
q
VLSI(UNIXdP<
RF CMOS IC Design
dd9Lq
B
ddVZ
(6(y
U(Yd
MM9
dY
q (3
H'? 16
Verdi fundamental and Siloti full-chip-
]
simulation training
To help you understand complex designs more easily. To help you trace back
to the root cause quickly when finding bugs. To do debugging and verification
in one unified and friendly environment.
Technology Background
Set Up the Environment
Understand FSDB Dumping Tasks and Utilities
Import Design
Debug in Source Code View
Debug in Waveform View
Debug in Schematic View
Debug in FSM view
Debug in Temporal Flow View
Power Aware Debug
Running Full Chip Simulation with Siloti
Basic HDL/HVL coding skills: Verilog, VHDL, SystemVerilog Familiarity
q with standard simulators Architecture engineer Development engineer Verifi-
cation engineer
To finish your analog design by using Laker ADP and Laker L3 (SDL flow)
H'? 17
LakerADP:
1.Basic drawing
2.Using Symbol Editor
3.Parameter & Property
4.Design debugging
5.Simulation Console
6.Back Annotation & TCL call back fuction
LakerL3 :
1.Laker L3 Overview
2.Laker L3 GUI
3.Design In
4.Laker L3 Functions
5.Net Router
6.ECO and Discrepancy
7.Use Legacy Design in L3
8.L3TCL
Basic Analog Design & Layout, Laker Basic ,LakerL2,Analog Device , Linux
q
env Analog Design engineer Analog Layout engineer CAD engineer
dMAgilent ADS
d. Agilent ADS3(dB'
ADSg((simulator).Vo
SHarmonic BalanceCircuit Envelope(B
q 3(
H'? 18
CMOS BioMEMS Sensing Technology /
d.CIC(CMOS BioMEMS!3
(u-TAS, micro-total analysis system)
1. CMOS &MEMS .
2. Transducer.
3. CIC CMOS BioMEMS b[.
4. db[Y(fSoC.
5. Microfluidics and micro-bio-system
6.
q CMOS MEMSf(
.h.~
M9`
(
Introduction to MEMS
Readout Circuit Introduction
Noise reduction techniques
q
H'? 19
RF /
dMADSM>
}B9YM
?BM9Yg&}9
"
vMADSRF.(9
RF SiP3ML}1 GHz
2 UWBL/}Y
}EDA"1 Agilent/ADS
2 Virtuoso-XLM93
/qU/qH+(
('ML}
q (
.h.~
M9`
(d.Agilent 2.5Db
Momentumf
d. Agilent M o m e n-
tum(dB'(Microstrip lineRFIC laun-
chpatch antennaCoplanar Waveguide)EMB.EM
ADS}
q 3(
H'? 20
Digital IC Testing Step-by-Step with Verigy
93000
0V
1..
2.loadboardgB
3.
4.3
d(."(
g'gCgC++/SystenC
gVerilog
d. BMARMFast Model9Car-
bonSoC Designer
q (
H'? 21
FPGA Design Fundamentals for Altera
d.FPGAd9MorFPGAb[gQuartus II9
Modelsim
1.FPGA
2.FPGA9Quartus II
3."Modeslim
4.MorFPGA platform.9
q dFPGA 1.Verilog 2.
dm
gd
dm
g 1.Verilog 2.
q
3.
H'? 22
Cell-Based IC Physical Design and Verification
with IC Compiler
1.d(Cell-Based Back-
end()}Mixed-signal Flow(3
2.dgate-level netlistGDS&
ICH(Y
#design! ]d>Digital IC()
(B`Yhard-Macro
.Cell-based~(3
Cell-based
Cell-based 3
q cell-basedd9
H'? 23
T18
hCIC.(
f)ffz
&^
/ Introduction .
/ Applications T18/q.
/ Material download B
\/ Process Design Kit (PDK) PDK(Model.
1/ Reference
TSMC 0.35UM
1. TSMC 0.35UM.
2. gTSMC 0.35UM
3. gTSMC 0.35UM9
4. egTSMC 0.35UMCIC
q d 9gTSMC 0.35UM(
H'? 24
H'?
ICICC2
102IC/
IC IC IC
IC
1039DICC
IC IC
IChttp://
103/07/25 103/07/25 www.cic.org.tw/ICDESIGN
1.
103/08/11~ 103/08/11~ 2.
103/08/30 103/08/30
1.
103/09/15~ 103/09/15~ 2.
103/09/26 103/09/26 /
3.
1.
2.
103/09/27() 103/09/28() (:
)
103/10/31 103/10/31
~ ~
103/11/17 103/11/17
103/11/28 103/11/28
http://www.cic.org.tw/ICDESIGN
03-5773693*225 03-5774064
icdesign@cic.narl.org.tw
300267
IC
H'? 25
T18-103BH
H
i ('A)
g(U(
T18-103B-A0002 O 1.409*0.747
T18-103B-A0004 O U(YgK-band( 0.753*0.664
0.18umg
T18-103B-A0006 O 0.793*0.753
200M-1.6GHz
gWLAN 20 MHz Ellipti-
T18-103B-A0011 OO 0.548*0.878
caloH
T18-103B-A0012a O YKd( 0.623*0.607
eU(zG
T18-103B-A0030 O 1.354*1.365
+X
T18-103B-A0031 O 1.766*1.693
T18-103B-A0032 O gE-UTRA 0.605*0.740
gWiMAX 15 MHzoLad-
T18-103B-A0033 OO 0.790*0.663
derH
g5=(24GHz
T18-103B-A0034 O 0.890*0.590
Y(
T18-103B-A0035 O 1.500*1.300
H'? 26
gx(K
T18-103B-A0036 O 0.841*0.465
5U
gx(K
T18-103B-A0037 O 0.756*0.435
5U
T18-103B-A0038 O 5 GHz / 60 GHz 2.419*1.474
w5(5-GHz CMOSU
T18-103B-A0047 O 1.311*1.016
g5GHzLM960GHz
T18-103B-A0048 O 2.236*1.362
CMOS
gLTE 15MHzoLad-
T18-103B-A0049 OO 1.041*1.170
derH
T18-103B-A0052 O (U 2.044*1.000
g0Y!
T18-103B-A0055 O 0.962*0.932
gWiMAX 3.5 GHz
T18-103B-A0057am O CMOSg 2.903*2.238
g\3(B(10-bit 30MS/s U
T18-103B-A0058 O 0.821*0.724
G
IEEE 802.15.6-2012 (9 0.901*0.889
T18-103B-A0059a jO
T18-103B-A0060 O S( 1.140*1.660
g(ETCITS)H(
T18-103B-A0065 O 2.142*0.715
T18-103B-A0067 OO S(S 1.416*1.392
gCMOS-MEMS Y(Y:
T18-103B-A0068m O 0.795*1.339
H'? 27
T18-103B-A0069 O | 1.300*1.300
gCMOS(/qY
T18-103B-A0070 O 1.343*0.968
T18-103B-A0071 Ov g24 GHz( 1.012*0.672
T18-103B-A0080 OB Y( 1.115*1.110
T18-103B-A0083a O H 1.489*1.481
T18-103B-A0084a O YG 1.489*1.481
T18-103B-A0085a IO ? 1.489*1.481
T18-103B-A0086a O ?H 1.489*1.481
g412/20uG
T18-103B-N0003 OO 1.165*1.148
T18-103B-P0001 O g('CMOS 1.509*1.374
e10/,
T18-103B-P0005 OA 1.582*1.388
G
T18-103B-P0006 O gf(G 0.868*0.827
20.9 27.6GHzgo+
T18-103B-P0008 IO 0.657*0.657
H'? 28
e(10/,
T18-103B-P0010 O 2.048*1.138
G
T18-103B-P0011 O (CMOST 2.392*2.000
g(au-
T18-103B-P0025 O 0.734*0.434
dio)G(6Y
T18-103B-P0028 O g(Audio)G^( 0.538*0.615
(1.8G~2.8GHz
T18-103B-I0001 O 1.300*0.693
(
T18-103B-I0002 O- ( 1.103*0.893
0.9-VeU/G 0.997*1.033
T18-103B-I0005 OO
g(3G
T18-103B-I0006 OAO 1.458*1.378
T18-103B-I0011 O gf( 0.700*0.500
H'? 29
T18-103B-E0001 O 1MHz}8/SAR ADC 1.093*0.993
g(GFO!}/
T18-103B-E0012 O 0.888*0.888
H
9DAC(G
T18-103B-E0013 O 1.149*1.148
FOLDPC(8,4)H
T18-103B-E0014 On ( 0.599*0.600
T18-103B-E0016 O x 0.535*0.550
T18-103B-E0017 O ( 0.658*0.604
9(
T18-103B-E0021 IO 0.639*0.588
48-bit 20 MS/
T18-103B-E0022 O 0.777*0.723
sU(G
T18-103B-E0023 IO g8-10GHz 0.450*0.621
(ATMEther-
T18-103B-E0026a OIO 1.034*1.025
netVH
T18-103B-E0027 O 16-20GHz 0.630*0.465
/,/G
T18-103B-E0029 O 1.000*1.000
H'? 30
T18-103B-E0030 O- g(U\ 0.510*0.514
T18-103B-E0032 O g 1.003*0.668
T18-103B-E0043 Ob 0.628*0.628
T18-103B-E0047 O 0.978*0.959
gY((4
T18-103B-E0050 ZOA 0.841*0.724
10-bit 20 MS/s G
gB(CMOS
T18-103B-E0051 O 0.298*0.300
T18-103B-E0052 O f 1.200*1.200
T18-103B-E0053 O 0.940*0.940
T18-103B-E0055 O 0.640*0.829
T18-103B-E0060 O Q 0.953*0.952
H'? 31
T18-103B-E0061 O g(1VM- 0.725*0.906
T18-103B-E0065 O C 0.816*0.821
T18-103B-E0073 BO \ 0.796*1.017
1/R-
T18-103B-E0074 O 0.816*0.847
2R>G
T18-103B-E0075 OO U 1.000*1.000
T18-103B-E0078 O 0.628*0.628
}4L
T18-103B-E0079 O 1.016*0.949
T18-103B-E0080 OO 0.888*0.758
T18-103B-E0082 O J( 1.190*1.195
T18-103B-E0083 O U 1.000*0.900
T18-103B-E0084 O U( 0.930*1.000
T18-103B-E0088 O \( 1.009*1.022
H'? 32
T18-103B-E0090 O ( 0.724*0.943
T18-103B-E0091 O C 1.126*1.109
T18-103B-E0093 O 1.132*1.022
gLbalun(24GHzg0.18um
T18-103B-E0094 O 0.750*0.505
CMOS
T18-103B-E0095 O (w 0.780*0.680
GFO(G!
T18-103B-E0102 O 0.888*0.888
H
10/24 GHzgyg(}U
T18-103B-E0103 O 0.957*0.918
T18-103B-E0104 O 24GHzCMOSL 0.450*0.450
fM9g(
T18-103B-E0106 O 1.200*0.904
(g
T18-103B-E0107 O 2.4GHz 0.396*0.425
g(5.6
T18-103B-E0111 O 0.763*0.770
GHzgWiMAX (
T18-103B-E0112 O \S 1.133*1.180
T18-103B-E0116 O 0.742*0.794
T18-103B-E0118 O U 1.195*1.199
H'? 33
Wafer Mapping (IC)
H'? 34
D35-103BH
H
IC ('A)/('A)
gt(tH
D35-103B-A0006 1.096*1.005
fHJc(
D35-103B-A0010m 1.905*1.927
D35-103B-A0011 (CMOS-MEMSx 1.181*1.075
D35-103B-A0014 2.500*2.500
CMOSz??
D35-103B-A0015 5.200*1.520
gb[
D35-103B-A0016 gCMOS 1.928*1.920
D35-103B-A0017 1.926*1.810
D35-103B-A0019 2.470*1.953
5(M9(:
D35-103B-P0001 1.505*1.646
8
D35-103B-P0002 YS8DC-DC 1.513*1.513
g9
D35-103B-P0004 1.539*2.174
(
(wCMOS j
D35-103B-I0001 0.979*1.999
H
g(
D35-103B-I0002 0.876*0.908
/8
(wCMOS 5
D35-103B-I0003 I 0.979*1.999
H
T(U
D35-103B-I0004 2.447*2.490
D35-103B-I0005 ,A eo` 2.349*2.349
D35-103B-I0007a ( 0.865*0.904
H'? 35
D35-103B-E0002 , VLSI(null) 1.056*1.056
,,
D35-103B-E0027 (null) 1.489*1.489
/
(INDEPENDENT STUDIES IN ELEC-
D35-103B-E0028 , TROMAGNETIC COMPATIBILITY) 1.000*1.000
H'? 36
,,
D35-103B-E0029 (Special Project) 1.430*1.402
D35-103B-E0030 (null) 1.444*1.500
H'? 37