These are the buzzwords for this semester.

See the Glossary of Buzzwords from Fall 2005 to Present

for explanations of each buzzword.

List of Buzzwords:
ISA
algorithm
ascii
Byte addressable
circuits
clock cycle
data type
electrons
Endianness
layers of transformation
microarchitecture
tradeoffs
Moore's Law
Hardware
Programmer
Pragma
Compiler
Multicores
Energy Efficiency
Microarchtecture
Bandwidth
Soft Errors
Partitioning
Role of the Architect
Critical Path Design
Bread and Butter Design
Balanced Design
Large/Fast cache trade-off
Global/Microarchitecture/physical view
Profiling
Quick sort
Data dependent operations in hardware
Peformance
Energy
Instruction supply
Datapath
Data supply
Dark Silicon
Accelerators
3D chips
Prediction of technology - alpha 21164 example
speculation
unaligned access
addressing mode
condition codes
programmer vs. architect
data type
instruction cycle
sign-extend
hardware interlocks
physical memory
load/store architecture
fixed length and uniform decode
out of order execution
0,1,2,3 address machines
stack
compatibility vs. a new ISA
RISC
VAX
overflow
pseudo-op
COND bits
J bits
control signal
IRD register
ready bit
control store
decoder
microinstruction
microsequencer
Parasitic Capacitor (in transistor)
SRAM
DASD
Refresh (in DRAM)
DRAM
Sequential Access Storage
Page mode
Volatile/Non-Volatile
Bitline
Wordline
CAM
Row Buffer
Sense Amplifier
Rank
Byte-on-Bus bits
chip enable
Address Space
Bank
Interleaving
Byte Rotate
error correction
parity
hamming code
error detection
Error Correcting Code
pipeline / assembly line
Branch prediction
out of order
Compile time prediction
setup time / hold time
clock skew
profiling
Pentium / RISC frequency
predicated execution
hammock
program phases
last time taken predictor
2-bit saturating counter
infinity
Branch History Register (BHR)
two-level adaptive predictor
Pattern History Table (PHT)
GAg (and variations)
Flynn's bottleneck
Global/set/per 2-level predictor
significance of misprediction rate
Hashing = key transformation
Associative memory
context switch
CAM
HEP (Burton Smith)
Hashing functions
issue width
g-share predictor (Scott McFarling)
Multi-threading
thread = instruction stream
Virtual memory
self-modifying code
pages
Frames
Thrashing
Page fault
Resident page
PTE (Page table entry)
Page table
Modify bit
Protection bit
Levels of privilege
Virtual Address Translation
ACV/ TNV checks
Disk arm / track / Rotation / Seek
Reference bits
System space
Variable page size
Intel variable page sizes
2-level mapping in virtual address translation
Segmentation
VAX P0 (program) / P1 (control) space
Working Set
Balance Set
Page Table Base registers
System Base Register
Walking the page table
TLB (Translation lookaside buffer)
TLB Hit rate
PBR / SBR
VMS / WNT
Real Address
linear address space
Segmented Model
cache
context switching
Segment Registers
Tag store
Logical Address
Intel Page directory, Page table
Task State Segment (TSS)
Instruction prefixes of x86