E x p e r i me n t No - 7

D e s i g n a n d I mp l e me n t a t i o n o f 4 - b i t r i p p l e c o u n t e r a n d Mo d - 1 0
counters using flip flop and gates

Object
a. To design of 4- bit Ripple Counter using J-K Flip flop (IC7476).
b. Verify the timing diagram and truth Table.
c. To design of Mod-10 Counter using J-K Flip flop (IC7476) and AND gate.
d. Verify the timing diagram and truth Table of Mod-10 counter.
Apparatus Required

1. Components Development System

2. Discrete Components - IC7476 Dual JK Flip-flop 2Nos
3. AND Gate (IC7408) 1No.
4. Patch Cord- 7Nos
5. wires As required

Theory :-Asynchronous Counter is sequential circuit that is used to count the number of clock
input signal. The output of one flip flop is given as a clock input to another flip-flop, so it is
called as Serial Counter. A ripple counter is an asynchronous counter where only the first flip-
flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the
preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way
the clock pulse ripples it way through the flip-flops. The MOD of the ripple counter or
asynchronous counter is 2n if n flip-flops are used. A four-bit asynchronous counter is shown on
the below figure. The external clock is connected to the clock input of the first flip -flop (FFA)
only. So, FFA changes state at the falling edge of each clock pulse, but FFB changes only when
triggered by the falling edge of the QA output of FFA similarly FFC changes only when
triggered by the falling edge of the QB output of FFB. Because of the inherent propagation delay
through a flip-flop, the transition of the input clock pulse and a transition of the QA output of
FFA can never occur at exactly the same time. Therefore, the flip-flops cannot be triggered
simultaneously, producing an asynchronous operation. Usually, all the CLEAR inputs are
connected together, so that a single pulse can clear all the flip-flops before counting starts. The
clock pulse fed into FFA is rippled through the other counters after propagation delays, like a
ripple on water, hence the name Ripple Counter

CLR = PRE = 5V(VCC)

Pin 13 = GND

Pin 5 = 5Volts(Vcc)
Circuit Diagram

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE (Mod-10)

CLK QA QB QC QD

9
10
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.