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DFT Compiler RTL Test Design Rule Checking User Guide
DFT Compiler RTL Test Design Rule Checking User Guide
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DFT Compiler RTL Test Design Rule Checking User Guide, W-2004.12
ii
Contents
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
iii
Violations That Prevent Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Used As Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Black Box Feeds Into Clock or Asynchronous Control . . . . . . . . . . . . . . . 17
Source Register Launch Before Destination
Register Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Latches as the Source and Destination Register . . . . . . . . . . . . . . . 17
Registered Clock-Gating Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Three-State Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Feeding Multiple Register Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Violations That Reduce Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Combinational Feedback Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clocks That Interact With Register Input . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiple Clocks That Feed Into Latches and Flip-Flops . . . . . . . . . . . . . . 22
Latch Requires Multiple Clocks to Capture Data . . . . . . . . . . . . . . . 22
Latches Are Not Transparent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Index
iv
About This Manual
The DFT Compiler RTL Test Design Rule Checking User Guide describes
design rule checking at the RTL level when using DFT Compiler.
Audience
This manual is intended for ASIC deisgn engineers who have some exposure
to testability concepts and strategies. It is also useful for test and
design-for-test engineers who want to understand how basic test automation
concepts and practices relate to DFT Compiler.
Related Publications
For additional information about DFT Compiler, see:
Documentation on the Web, which provides HTML and PDF documents and
is available through SolvNet at:
http://solvnet.synopsys.com
The documentation installed with the DFT Compiler software and available
through the DFT Compiler Help menu
Synopsys Online Documentation (SOLD), which is included with the
software for CD users or is available to download through the Synopsys
Electronic Software Transfer (EST) system
v
About This Manual
Conventions
You might also want to refer to the documentation for the following related
Synopsys products:
Design Compiler
BSD Compiler
TetraMAX
Conventions
The following conventions are used in Synopsys documentation.
Convention Description
Regular bold User input that is not Synopsys syntax, such as a user
name or password you enter in a GUI.
vi
About This Manual
Customer Support
Convention Description
Edit > Copy Indicates a path to a menu command, such as opening the
Edit menu and choosing Copy.
Customer Support
Customer support is available through SolvNet online customer support and
through contacting the Synopsys Technical Support Center.
Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and
answers to frequently asked questions about Synopsys tools. SolvNet also
gives you access to a wide range of Synopsys online services including
software downloads, documentation on the Web, and Enter a Call to the
Support Center.
To access SolvNet,
vii
About This Manual
Customer Support
viii
1
Preparing your RTL Design for Design Rule Checking1
or
dc_shell-t> set hdlin_enable_rtldrc_info true
dc_shell-t> analyze -format verilog my_design.v
dc_shell-t> elaborate my_design
Important:
You must set the hdlin_enable_rtldrc_info variable to true before
you read in your HDL source. Then TestDRC can report file names and line
numbers associated with any testability violations, which makes it easier to
edit the source code and fix the violations.
1
Preparing your RTL Design for Design Rule Checking
Setting the Scan Style
To save execution time in subsequent dc_shell sessions, you can save the
design in .db format using the following command:
dc_shell-t> write -format db -hierarchy -output my_design.db
For more information about these commands, see the Design Compiler
documentation.
2
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
3
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
STIL 1.0 {
Design P2000.9;
}
Header {
Title "DFT Compiler 2000.11 STIL output";
Date "Wed Jan 3 17:36:04 2001";
History {
}
}
Signals {
"ALARM" In; "BSD_TDI" In; "BSD_TEST_CLK" In; "BSD_TMS" In;
"BSD_TRST" In; "CLK" In; "HRS" In; "MINS" In; "RESETN" In;
"SET_TIME" In; "TEST_MODE" In; "TEST_SE" In; "TEST_SI" In;
"TOGGLE_SWITCH" In;
"AM_PM_OUT" Out; "BSD_TDO" Out; "HR_DISPLAY[0]" Out;
"HR_DISPLAY[1]" Out; "HR_DISPLAY[2]" Out; "HR_DISPLAY[3]" Out;
"HR_DISPLAY[4]" Out; "HR_DISPLAY[5]" Out; "HR_DISPLAY[6]" Out;
"HR_DISPLAY[7]" Out; "HR_DISPLAY[8]" Out; "HR_DISPLAY[9]" Out;
"HR_DISPLAY[10]" Out; "HR_DISPLAY[11]" Out; "HR_DISPLAY[12]"
Out;
"HR_DISPLAY[13]" Out; "MIN_DISPLAY[0]" Out; "MIN_DISPLAY[1]"
Out;
"MIN_DISPLAY[2]" Out; "MIN_DISPLAY[3]" Out; "MIN_DISPLAY[4]"
Out;
"MIN_DISPLAY[5]" Out; "MIN_DISPLAY[6]" Out; "MIN_DISPLAY[7]"
Out;
"MIN_DISPLAY[8]" Out; "MIN_DISPLAY[9]" Out; "MIN_DISPLAY[10]"
Out;
"MIN_DISPLAY[11]" Out; "MIN_DISPLAY[12]" Out; "MIN_DISPLAY[13]"
Out;
"SPEAKER_OUT" Out;
}
SignalGroups {
"all_inputs" "ALARM" + "BSD_TDI" + "BSD_TEST_CLK" + "BSD_TMS" +
"BSD_TRST" + "CLK" + "HRS" + "MINS" + "RESETN" + "SET_TIME" +
"TEST_MODE" + "TEST_SE" + "TEST_SI" + "TOGGLE_SWITCH"; //
#signals=14
"all_outputs" "AM_PM_OUT" + "BSD_TDO" + "HR_DISPLAY[0]" +
4
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
ScanStructures {
ScanChain "c0" {
ScanLength 40;
ScanIn "TEST_SI";
ScanOut "SPEAKER_OUT";
}
}
Timing {
WaveformTable "_default_WFT_" {
Period 100ns;
Waveforms {
"all_inputs" { 0 { 5ns D; } }
"all_inputs" { 1 { 5ns U; } }
"all_inputs" { Z { 5ns Z; } }
"all_outputs" { X { 0ns X; } }
"all_outputs" { H { 0ns X; 95ns H; } }
"all_outputs" { T { 0ns X; 95ns T; } }
"all_outputs" { L { 0ns X; 95ns L; } }
"CLK" { P { 0ns D; 45ns U; 55ns D; } }
"BSD_TEST_CLK" { P { 0ns D; 45ns U; 55ns D; } }
"RESETN" { P { 0ns U; 45ns D; 55ns U; } }
}
}
}
PatternBurst "__burst__" {
"__pattern__" {
}
}
PatternExec {
Timing "";
PatternBurst "__burst__";
}
5
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
Procedures {
"load_unload" {
W "_default_WFT_";
V { "BSD_TEST_CLK"=0; "BSD_TRST"=0; "CLK"=0; "RESETN"=1;
"TEST_MODE"=1; "TEST_SE"=1; "_so"=#; }
Shift {
W "_default_WFT_";
V { "BSD_TEST_CLK"=P; "BSD_TRST"=0; "CLK"=P; "RESETN"=1;
"TEST_MODE"=1; "TEST_SE"=1; "_so"=#; "_si"=#; }
}
}
"capture" {
W "_default_WFT_";
F { "BSD_TRST"=0; "TEST_MODE"=1; }
V { "_pi"=\r14 #; "_po"=\r31 #; }
}
"capture_CLK" {
W "_default_WFT_";
F { "BSD_TRST"=0; "TEST_MODE"=1; }
"forcePI": V { "_pi"=\r14 #; }
"measurePO": V { "_po"=\r31 #; }
"pulse": V { "CLK"=P; }
}
"capture_BSD_TEST_CLK" {
W "_default_WFT_";
F { "BSD_TRST"=0; "TEST_MODE"=1; }
"forcePI": V { "_pi"=\r14 #; }
"measurePO": V { "_po"=\r31 #; }
"pulse": V { "BSD_TEST_CLK"=P; }
}
"capture_RESETN" {
W "_default_WFT_";
F { "BSD_TRST"=0; "TEST_MODE"=1; }
"forcePI": V { "_pi"=\r14 #; }
"measurePO": V { "_po"=\r31 #; }
"pulse": V { "RESETN"=P; }
}
}
MacroDefs {
"test_setup" {
W "_default_WFT_";
V { "BSD_TEST_CLK"=0; "CLK"=0; }
V { "BSD_TEST_CLK"=0; "BSD_TRST"=0; "CLK"=0; "RESETN"=1;
"TEST_MODE"=1; }
}
}
6
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
Note:
The read_init_protocol command only imports the test_setup
section of the protocol file and ignores the remaining sections.
Design Examples
This section contains two simple design examples that illustrate how to
generate test protocols. The first example shows how to use the
set_signal_type command to control the clock signal, the scan-enable
signal, and the asynchronous reset. The second example decribes a two-pass
process for defining an initialization sequence in a test protocol.
out1
in2 out2
U2
in3
in1
clk U1
cdn
7
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
endmodule
In this design, you must define the clock signal, clk. You must also specify that
in3 be held at 1 during scan-in to enable the clock signal for U2. Finally you
must hold the cdn signal at 1 during scan-in so that the reset signal is not
applied to the registers. Example 2 shows a command sequence that specifies
a test protocol for the design using the set_signal_type command.
Example 2 Command Sequence that Defines a Test Protocol
8
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
in1 out1
ff_c
in2 out2
ff_d
ff_a_reg/Q ff_b_reg/Q
cdn
ff_a ff_b
clk resetn
9
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
end
end
endmodule
In this design, you must define the clock signal, clk. You must also make sure
that cdn and the Q output of ff_b_reg remain at 1 during the test cycle, so
that the resetn signal remains at 1.
If you do not initialize the design, test DRC assumes that the resetn signal is
not controllable and marks the two flip-flops ff_c and ff_d as having design
rule violations.
To initialize the design, you must hold cdn at 1, and pulse the clk signal twice
so that the resetn signal is at 1.
For this example, the protocol is generated in a two-pass process. In the first
pass, the generated protocol contains an initialization sequence based on the
test attributes placed on clk and cdn ports. The script is shown in Example 3.
Example 3 Command Sequence that Defines Preliminary Protocol
MacroDefs {
"test_setup" {
W "_default_WFT_";
V { "clk"=0; }
V { "cdn"=1; "clk"=0; }
}
}
If you run test design rule checking without modifying these initialization steps,
it reports the following violation:
Warning: Reset input of DFF ff_d_reg was not controlled. (D3-1)
10
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
For the second pass of the protocol generation process, modify the initialization
sequence as shown:
1. Add the three lines shown in bold to the test_setup section of the
MacroDefs block:
MacroDefs {
"test_setup" {
W "_default_WFT_";
V { "clk"=0; }
V { "cdn"=1; "clk"=0; }
V { "cdn"=1; "clk"=P; }
V { "cdn"=1; "clk"=P; }
V { "cdn"=1; "clk"=0; } }
}
The added steps pulse the clock signal twice while holding the cdn port to
1. The final step holds clk to 0 because the test design rule checker
expects all clocks to be at an inactive state at the end of the initialization
sequence.
2. Save the protocol into a new file (in this case, the file is called second.spf).
write_test_protocol -format stil -output second.spf
b. Read just the initialization portion of the protocol and use the
create_test_protocol command to fill in the remaining sections of
the protocol:
remove_test_protocol
read_init_protocol second.spf
create_test_protocol
4. After you have read in the initialization protocol, perform test DRC again.
The following violation is reported:
Warning: Cell ff_b_reg has constant 1 value. (TEST-505)
This is to be expected because the outputs of ff_a and ff_b did not reach
0. Constant flip-flops are not included in the scan chain.
11
Preparing your RTL Design for Design Rule Checking
Defining the Test Protocol
12
2
Checking for Violations in RTL Designs2
Overview
Test design rule checking checks your design to determine if you have any test
design rule violations. Before you can fix your design, you must understand
what types of violations are checked and why these checks are necessary.
This chapter explains the test design rule checks that are performed on your
design. This chapter also describes messages you see when you encounter
test design rule violations and methods to efficiently fix the violations.
This chapter includes the following sections:
Violations That Prevent Scan Insertion
Violations That Prevent Data Capture
Violations That Reduce Fault Coverage
13
Checking for Violations in RTL Designs
Violations That Prevent Scan Insertion
Uncontrollable Clocks
This violation can be caused by undefined or unconditioned clocks. DFT
Compiler considers a clock to be controlled only if both of these conditions are
true:
It is forced to a known state at time = 0 in the clock period (which is the same
as the clock off state in TetraMAX).
It changes state as a result of the test clock toggling.
Going to an unknown state (X) is considered to be a change of state.
However, if the clock stays in a single known state no matter what state the
test clock is in, the clock will generate a violation for not being reached by
any test clock.
You must use the create_test_clock command to define test clocks in your
design. Use the set_signal_type and set_test_hold commands to
condition gated clocks to reach their destinations.
The violation message provides the name of the signal that drives the clock
inputs and the registers that ATPG cannot control.
If a design has an uncontrollable register clock pin, it generates one of the
following messages:
14
Checking for Violations in RTL Designs
Violations That Prevent Data Capture
15
Checking for Violations in RTL Designs
Violations That Prevent Data Capture
Note that ATPG does not consider timing when generating vectors for a scan
design. If you do not fix the violations in this section, ATPG might generate
vectors that fail functional simulation or fail on the tester (although in TetraMAX,
in particular, you would also have to override the TetraMAX default settings).
The violations are described in the following sections:
Clock Used As Data
Black Box Feeds Into Clock or Asynchronous Control
Source Register Launch Before Destination Register Capture
Registered Clock-Gating Circuitry
Three-State Contention
Clock Feeding Multiple Register Inputs
U3 U1
D1 D Q
my_clock
CP
If the clock and data input to a register are interdependent, you might get the
following message:
16
Checking for Violations in RTL Designs
Violations That Prevent Data Capture
U2
D Q OP1
my_black_box
D1 D Q CP
G
CLK
For more information about black boxes, see Black Boxes on page 23.
17
Checking for Violations in RTL Designs
Violations That Prevent Data Capture
my_latch U2
D1 D Q D Q OP1
my_clock G G
If multiple latches are enabled so that the latches feed through capture data,
you get the following message:
U2
D_1 D Q OP
my_inv_clk
U3 U1 CP
D_2 D Q
my_clock CP
The U1 output invalidly clocks register U2. The OR gate, U1, has two inputs
where one is the output of register U3 and the other input is the signal used to
clock U3.
18
Checking for Violations in RTL Designs
Violations That Prevent Data Capture
Notice that Power Compiler clock gating does not lead to this violation, because
Power Compiler uses opposite-edge-triggered flip-flops or latches to create the
clock-gating signals.
This circuit configuration results in timing hazards, including clock glitches and
clock skew. Modify the clock-gating logic to eliminate this type of logic.
If you implement this type of clock-gating circuitry, you get the following
message:
Three-State Contention
DFT Compiler can check to see if your RTL code contains three-state
contention conditions. If floating or contention is found, one of the following
three error messages is issued:
D20 Bus gate N failed contention ability check for drivers G1 and G2.
D22 Wire gate N failed contention ability check for drivers G1 and G2.
19
Checking for Violations in RTL Designs
Violations That Reduce Fault Coverage
Figure 7 Clock Signal Feeds Register Clock Pin and Asynchronous Reset
U2
D Q OP1
my_clock CP
RST
If you implement this type of design circuitry, you get the following message:
20
Checking for Violations in RTL Designs
Violations That Reduce Fault Coverage
If you are using the loop as a latch, convert the combinational elements that
make up this feedback loop into a latch from your ASIC vendor library. Figure 8
shows this type of loop.
Figure 8 Highlighted Combinational Feedback Loop
in1
in2 U2 Q
U1
If your design contains a sensitizable feedback loop, you get the following
message:
U2
clk1 D Q OP1
clk2 CP
RST
21
Checking for Violations in RTL Designs
Violations That Reduce Fault Coverage
If a clock affects the data of a register, you get one of these messages:
22
Checking for Violations in RTL Designs
Violations That Reduce Fault Coverage
If you generate logic that violates these clock rules, you get the following
message:
D8 Clock clk1 cannot capture data with other clocks off. (D8-1)
Black Boxes
Logic that drives or is driven by black boxes cannot be tested because it is
unobservable or uncontrollable. This violation can drastically reduce fault
coverage, because the logic that surrounds the black box is unobservable or
uncontrollable. Figure 11 shows an example.
23
Checking for Violations in RTL Designs
Violations That Reduce Fault Coverage
my_bb1 my_bb2
IN1 IN OUT IN OUT OP1
If there are any black boxes in your design, dft_drc issues the following
warning:
Warning: Cell U0 (black_box) is unknown (black box) because
functionality for output pin Z is bad or incomplete. (TEST-451)
24
Index
A D
asynchronous control pins violations 15 data feedthrough 17
asynchronous signals 3
attributes F
recognized by RTL TestDRC 3
test_asynch 3, 15 feedback violations 20
test_asynch_inverted 3, 15 feedthrough 17
format
STIL 4
B
black box
violations 17, 23 H
HDL source files 1
C
clocks I
feeding multiple register inputs 19 identifying test clocks 3
gating violations 18 initialization protocol
identifying test clocks 3 and RTL TestDRC 3
interaction violations 21 STIL format 4
multiple 22 initialization requirements, defining 3
uncontrollable 14
used as data violation 16
L
combinational feedback, violations 20
latches
commands
as source and destination violation 17
create_test_clock 3, 14
requiring multiple clocks violations 22
read_init_protocol 3
launch before capture violations 17
set_signal_type 3, 8, 14
set_test_hold 3, 14
constant logic values, defining for test mode 3 M
control signals 3 multiple clocks
create_test_clock command 3, 14 required by latch 22
violations 22
25
P test_scan_enable attribute 3
protocol file test_scan_enable_inverted attribute 3
design examples 7
U
R uncontrollable clocks 14
read_init_protocol command 3 uncontrollable registers 15
reading HDL source files 1 unreliable capture 17
registered clock gating circuitry violations 18
RTL TestDRC V
recognized attributes 3
violations
asynchronous control pins 15
S black box 17
saving, db format files 2 black boxes 23
scan enable signals 3 clock feeding multiple register inputs 19
sensitizable feedback loops 20 clock used as data 16
set_signal_type command 3, 8, 14 clocks interacting with register input 21
combinatial feedback loops 20
set_test_hold command 3, 14
latch requiring multiple clocks 22
signals
latches as source and destination 17
control 3
scan enable 3 launch before capture 17
STIL format multiple clocks 22
initialization protocol 4 preventing data capture 15
preventing scan insertion 14
reducing fault coverage 20
T registered clock gating circuitry 18
test clocks 3
uncontrollable clocks 14
test_asynch attribute 3, 15
test_asynch_inverted attribute 3, 15
26