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Cd54hc4046a PDF
Cd54hc4046a PDF
Cd54hc4046a PDF
CD54HCT4046A, CD74HCT4046A
Data sheet acquired from Harris Semiconductor
SCHS204J
High-Speed CMOS Logic
February 1998 - Revised December 2003 Phase-Locked Loop with VCO
Features Description
Operating Frequency Range The HC4046A and HCT4046A are high-speed silicon-gate
- Up to 18MHz (Typ) at VCC = 5V CMOS devices that are pin compatible with the CD4046B of
[ /Title the 4000B series. They are specified in compliance with
- Minimum Center Frequency of 12MHz at VCC = 4.5V
(CD74 JEDEC standard number 7.
HC404 Choice of Three Phase Comparators
The HC4046A and HCT4046A are phase-locked-loop
- EXCLUSIVE-OR circuits that contain a linear voltage-controlled oscillator
6A,
- Edge-Triggered JK Flip-Flop (VCO) and three different phase comparators (PC1, PC2 and
CD74 PC3). A signal input and a comparator input are common to
- Edge-Triggered RS Flip-Flop
HCT40 each comparator.
46A) Excellent VCO Frequency Linearity
The signal input can be directly coupled to large voltage
/Sub- VCO-Inhibit Control for ON/OFF Keying and for Low signals, or indirectly coupled (with a series capacitor) to small
ject Standby Power Consumption voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
(High- Minimal Frequency Drift
passive low-pass filter, the 4046A forms a second-order loop
Speed Operating Power Supply Voltage Range PLL. The excellent VCO linearity is achieved by the use of
CMOS - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V linear op-amp techniques.
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Ordering Information
Fanout (Over Temperature Range)
TEMP. RANGE
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
PART NUMBER (oC) PACKAGE
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD54HC4046AF3A -55 to 125 16 Ld CERDIP
Wide Operating Temperature Range . . . -55oC to 125oC CD54HCT4046AF3A -55 to 125 16 Ld CERDIP
Balanced Propagation Delay and Transition Times CD74HC4046AE -55 to 125 16 Ld PDIP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright 2003, Texas Instruments Incorporated
1
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Pinout
CD54HC4046A, CD54HCT4046A (CERDIP)
CD74HC4046A (PDIP, SOIC, SOP, TSSOP)
CD74HCT4046A (PDIP, SOIC)
TOP VIEW
PCPOUT 1 16 VCC
PC1OUT 2 15 PC3OUT
COMPIN 3 14 SIGIN
VCOOUT 4 13 PC2OUT
INH 5 12 R2
C1A 6 11 R1
C1B 7 10 DEMOUT
GND 8 9 VCOIN
Functional Diagram
2
3 PC1OUT
COMPIN 15
PC3OUT
13
14 PC2OUT
SIGIN
1
PCPOUT
6
C1A
7
C1B 4
11 VCOOUT
R1
12 VCO
R2 10
9 DEMOUT
VCOIN
5
INH
Pin Descriptions
PIN NUMBER SYMBOL NAME AND FUNCTION
1 PCPOUT Phase Comparator Pulse Output
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input
4 VCOOUT VCO Output
5 INH Inhibit Input
6 C1A Capacitor C1 Connection A
7 C1B Capacitor C1 Connection B
8 GND Ground (0V)
9 VCOIN VCO Input
10 DEMOUT Demodulator Output
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection
13 PC2OUT Phase Comparator 2 Output
14 SIGIN Signal Input
15 PC3OUT Phase Comparator 3 Output
16 VCC Positive Supply Voltage
2
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
C1
6 7 4 3 14
COMPIN SIGIN
VCOOUT
C1A C1B
PC1OUT 2
VREF +
12 R2 SD PC3OUT
15
Q
- VCO
R2
Q
RD
11 R1
R1
- + VCC
VCC
UP
D Q
p
10
CP Q R3
DEMOUT 13
- RD PC2OUT
R5 +
C2
VCC Q
D GND
CP DOWN
Q 1
RD
5 9
General Description
VCO Phase Comparators
The VCO requires one external capacitor C1 (between C1A The signal input (SIGIN) can be directly coupled to the self-
and C1B) and one external resistor R1 (between R1 and biasing amplifier at pin 14, provided that the signal swing is
GND) or two external resistors R1 and R2 (between R1 and between the standard HC family input logic levels.
GND, and R2 and GND). Resistor R1 and capacitor C1 Capacitive coupling is required for signals with smaller
determine the frequency range of the VCO. Resistor R2 swings.
enables the VCO to have a frequency offset if required. See
Phase Comparator 1 (PC1)
logic diagram, Figure 1.
This is an Exclusive-OR network. The signal and comparator
The high input impedance of the VCO simplifies the design input frequencies (fi) must have a 50% duty factor to obtain
of low-pass filters by giving the designer a wide choice of the maximum locking range. The transfer characteristic of
resistor/capacitor ranges. In order not to load the low-pass PC1, assuming ripple (fr = 2fi) is suppressed, is:
filter, a demodulator output of the VCO input voltage is
provided at pin 10 (DEMOUT). In contrast to conventional VDEMOUT = (VCC/) (SIGIN - COMPIN) where VDEMOUT
techniques where the DEMOUT voltage is one threshold is the demodulator output at pin 10; VDEMOUT = VPC1OUT
voltage lower than the VCO input voltage, here the DEMOUT (via low-pass filter).
voltage equals that of the VCO input. If DEMOUT is used, a The average output voltage from PC1, fed to the VCO input
load resistor (RS) should be connected from DEMOUT to via the low-pass filter and seen at the demodulator output at
GND; if unused, DEMOUT should be left open. The VCO pin 10 (VDEMOUT), is the resultant of the phase differences
output (VCOOUT) can be connected directly to the of signals (SIGIN) and the comparator input (COMPIN) as
comparator input (COMPIN), or connected via a frequency- shown in Figure 2. The average of VDEM is equal to 1/2
divider. The VCO output signal has a specified duty factor of VCC when there is no signal or noise at SIGIN, and with this
50%. A LOW level at the inhibit input (INH) enables the VCO input the VCO oscillates at the center frequency (fo).
and demodulator, while a HIGH level turns both off to Typical waveforms for the PC1 loop locked at fo are shown
minimize standby power consumption. in Figure 3.
3
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
The frequency capture range (2fC) is defined as the VDEMOUT = (VCC/4) (SIGIN - COMPIN) where
frequency range of input signals on which the PLL will lock if VDEMOUT is the demodulator output at pin 10;
it was initially out-of-lock. The frequency lock range (2fL) is VDEMOUT = VPC2OUT (via low-pass filter).
defined as the frequency range of input signals on which the
The average output voltage from PC2, fed to the VCO via the
loop will stay locked if it was initially in lock. The capture
low-pass filter and seen at the demodulator output at pin 10
range is smaller or equal to the lock range.
(VDEMOUT), is the resultant of the phase differences of
With PC1, the capture range depends on the low-pass filter SIGIN and COMPIN as shown in Figure 4. Typical waveforms
characteristics and can be made as large as the lock range. for the PC2 loop locked at fo are shown in Figure 5.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that VCC
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
VDEMOUT (AV)
VCC
1/2 VCC
VDEMOUT (AV)
1/2 VCC
0
-360o 0o DEMOUT 360o
COMPIN
VCOOUT
VCC
PC2OUT
SIGIN GND
PCPOUT
PC1OUT
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
VCC
COMPARATOR 2, LOOP LOCKED AT fo
VCOIN
GND
When the frequencies of SIGIN and COMPIN are equal but
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE the phase of SIGIN leads that of COMPIN, the p-type output
COMPARATOR 1, LOOP LOCKED AT fo driver at PC2OUT is held ON for a time corresponding to
the phase difference (DEMOUT). When the phase of SIGIN
Phase Comparator 2 (PC2) lags that of COMPIN, the n-type driver is held ON.
This is a positive edge-triggered phase and frequency When the frequency of SIGIN is higher than that of
detector. When the PLL is using this comparator, the loop COMPIN, the p-type output driver is held ON for most of
is controlled by positive signal transitions and the duty the input signal cycle time, and for the remainder of the
factors of SIGIN and COMPIN are not important. PC2 cycle both n- and p-type drivers are OFF (three-state). If
comprises two D-type flip-flops, control-gating and a three- the SIGIN frequency is lower than the COMPIN frequency,
state output stage. The circuit functions as an up-down then it is the n-type driver that is held ON for most of the
counter (Figure 1) where SIGIN causes an up-count and cycle. Subsequently, the voltage at the capacitor (C2) of
COMPIN a down-count. The transfer function of PC2, the low-pass filter connected to PC2OUT varies until the
assuming ripple (fr = fi) is suppressed, is: signal and comparator inputs are equal in both phase and
4
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
5
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
VCO SECTION
INH High Level Input VIH - - 3 2.1 - - 2.1 - 2.1 - V
Voltage 4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
INH Low Level Input VIL - - 3 - - 0.9 - 0.9 - 0.9 V
Voltage 4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VCOOUT High Level VOH VIH or VIL -0.02 3 2.9 - - 2.9 - 2.9 - V
Output Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
VCOOUT High Level - - - - - - - - - V
Output Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
VCOOUT Low Level VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Output Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
VCOOUT Low Level - - - - - - - - - V
Output Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
C1A, C1B Low Level VOL VIL or VIH 4 4.5 - - 0.40 - 0.47 - 0.54 V
Output Voltage
5.2 6 - - 0.40 - 0.47 - 0.54 V
(Test Purposes Only)
6
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
TEST
CONDITIONS VCC 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
INH VCOIN Input II VCC or - 6 - - 0.1 - 1 - 1 A
Leakage Current GND
R1 Range (Note 2) - - - 4.5 3 - 300 - - - - k
R2 Range (Note 2) - - - 4.5 3 - 300 - - - - k
C1 Capacitance - - - 3 - - No - - - - pF
Range Limit
4.5 - - - - - - pF
6 - - - - - - pF
VCOIN Operating - Over the range 3 1.1 - 1.9 - - - - V
Voltage Range specified for R1 for 4.5 1.1 - 3.2 - - - - V
Linearity See Figure
10, and 34 - 37 6 1.1 - 4.6 - - - - V
(Note 3)
PHASE COMPARATOR SECTION
SIGIN, COMPIN VIH - - 2 1.5 - - 1.5 - 1.5 - V
DC Coupled 4.5 3.15 - - 3.15 - 3.15 - V
High-Level Input
Voltage 6 4.2 - - 4.2 - 4.2 - V
PCPOUT, PCn OUT VOH VIL or VIH -0.02 2 1.9 - - 1.9 - 1.9 - V
High-Level Output 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads 6 5.9 - - 5.9 - 5.9 - V
PCPOUT, PCn OUT VOH VIL or VIH -4 4.5 3.98 - - 3.84 - 3.7 - V
High-Level Output -5.2 6 5.48 - - 5.34 - 5.2 - V
Voltage
TTL Loads
PCPOUT, PCn OUT VOL VIL or VIH 0.02 2 - - 0.1 - 0.1 - 0.1 V
Low-Level Output 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads 6 - - 0.1 - 0.1 - 0.1 V
PCPOUT, PCn OUT VOL VIL or VIH 4 4.5 - - 0.26 - 0.33 - 0.4 V
Low-Level Output 5.2 6 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
SIGIN, COMPIN Input II VCC or - 2 - - 3 - 4 - 5 A
Leakage Current GND 3 - - 7 - 9 - 11 A
4.5 - - 18 - 23 - 29 A
6 - - 30 - 38 - 45 A
PC2OUT Three-State IOZ VIL or VIH - 6 - - 0.5 - 5 - 10 A
Off-State Current
SIGIN, COMPIN Input RI VI at Self-Bias 3 - 800 - - - - - k
Resistance Operation Point: 4.5 - 250 - - - - - k
VI = 0.5V,
See Figure 10 6 - 150 - - - - - k
DEMODULATOR SECTION
Resistor Range RS at RS > 300k 3 50 - 300 - - - - k
Leakage Current 4.5 50 - 300 - - - - k
Can Influence
VDEMOUT 6 50 - 300 - - - - k
7
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
TEST
CONDITIONS VCC 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Offset Voltage VCOIN VOFF VI = VVCO IN = 3 - 30 - - - - - mV
to VDEM VCC
4.5 - 20 - - - - - mV
2
Values Taken Over 6 - 10 - - - - - mV
RS Range
See Figure 23
Dynamic Output RD VDEMOUT = 3 - 25 - - - - -
Resistance at VCC
4.5 - 25 - - - - -
DEMOUT 2
6 - 25 - - - - -
Quiescent Device ICC Pins 3, 5 and 14 6 - - 8 - 80 - 160 A
Current at VCC Pin 9 at
GND, I1 at Pins 3
and 14 to be
excluded
HCT TYPES
VCO SECTION
INH High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
INH Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
VCOOUT High Level VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Output Voltage
CMOS Loads
VCOOUT High Level -4 4.5 3.98 - - 3.84 - 3.7 - V
Output Voltage
TTL Loads
VCOOUT Low Level VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Output Voltage
CMOS Loads
VCOOUT Low Level 4 4.5 - - 0.26 - 0.33 - 0.4 V
Output Voltage
TTL Loads
C1A, C1B Low Level VOL VIH or VIL 4 4.5 - - 0.40 - 0.47 - 0.54 V
Output Voltage
(Test Purposes Only)
INH VCOIN Input II Any Voltage 5.5 - 0.1 - 1 - 1 A
Leakage Current Between VCC and
GND
R1 Range (Note 2) - - - 4.5 3 - 300 - - - - k
R2 Range (Note 2) - - - 4.5 3 - 300 - - - - k
C1 Capacitance - - - 4.5 0 - No - - - - pF
Range Limit
VCOIN Operating - Over the range 4.5 1.1 - 3.2 - - - - V
Voltage Range specified for R1 for
Linearity See Figure
10, and 34 - 37
(Note 3)
PHASE COMPARATOR SECTION
SIGIN, COMPIN VIH - - 4.5 to 2 - - 2 - 2 - V
DC Coupled 5.5
High-Level Input
Voltage
8
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
TEST
CONDITIONS VCC 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
SIGIN, COMPIN VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
DC Coupled 5.5
Low-Level Input
Voltage
PCPOUT, PCn OUT VOH VIL or VIH - 4.5 4.4 - - 4.4 - 4.4 - V
High-Level Output
Voltage
CMOS Loads
PCPOUT, PCn OUT VOH VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V
High-Level Output
Voltage
TTL Loads
PCPOUT, PCn OUT VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V
Low-Level Output
Voltage
CMOS Loads
PCPOUT, PCn OUT VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V
Low-Level Output
Voltage
TTL Loads
SIGIN, COMPIN Input II Any - 5.5 - - 30 38 45 A
Leakage Current Voltage
Between
VCC and
GND
PC2OUT Three-State IOZ VIL or VIH - 5.5 - - 0.5 5 - - 10 A
Off-State Current
SIGIN, COMPIN Input RI VI at Self-Bias 4.5 - 250 - - - - - k
Resistance Operation Point:
VI = 0.5V,
See Figure 10
DEMODULATOR SECTION
Resistor Range RS at RS > 300k 4.5 5 - 300 - - - - k
Leakage Current
Can Influence
VDEM OUT
Offset Voltage VCOIN VOFF VI = VVCO IN = 4.5 - 20 - - - - - mV
to VDEM VCC
2
Values taken over
RS Range
See Figure 23
Dynamic Output RD VDEM OUT = 4.5 - 25 - - - - -
Resistance at VCC
DEMOUT 2
Quiescent Device ICC VCC or - 5.5 - - 8 - 80 - 160 A
Current GND
Additional Quiescent ICC VCC - 4.5 to - 100 360 - 450 - 490 A
Device Current Per (Note 4) -2.1 5.5
Input Pin: 1 Unit Load Excluding
Pin 5
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7k.
3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
9
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
INH 1
-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPLH, tPHL
SIGIN, COMPIN to PCIOUT 2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
6 - - 34 - 43 - 51 ns
SIGIN, COMPIN to PCPOUT 2 - - 300 - 375 - 450 ns
4.5 - - 60 - 75 - 90 ns
6 - - 51 - 64 - 77 ns
SIGIN, COMPIN to PC3OUT 2 - - 245 - 305 - 307 ns
4.5 - - 49 - 61 - 74 ns
6 - - 42 - 52 - 63 ns
Output Transition Time tTHL, tTLH 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Output Enable Time, SIGIN, tPZH, tPZL 2 - - 265 - 330 - 400 ns
COMPIN to PC2OUT
4.5 - - 53 - 66 - 80 ns
6 - - 45 - 56 - 68 ns
Output Disable Time, SIGIN, tPHZ, tPLZ 2 - - 315 - 395 - 475 ns
COMPIN to PC2OUT
4.5 - - 63 - 79 - 95 ns
6 - - 54 - 67 - 81 ns
AC Coupled Input Sensitivity VI(P-P) 3 - 11 - - - - - mV
(P-P) at SIGIN or COMPIN
4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
VCO SECTION
Frequency Stability with f R1 = 100k, 3 - 0.11 - - - - - %/oC
Temperature Change T R2 =
4.5 - 0.11 - - - - - %/oC
6 - 0.11 - - - - - %/oC
Maximum Frequency fMAX C1 = 50pF 3 - 24 - - - - - MHz
R1 = 3.5k
R2 =
4.5 - 24 - - - - - MHz
6 - 24 - - - - - MHz
C1 = 0pF 3 - 38 - - - - - MHz
R1 = 9.1k
R2 =
4.5 - 38 - - - - - MHz
6 - 38 - - - - - MHz
10
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Center Frequency C1 = 40pF 3 7 10 - - - - - MHz
R1 = 3k
R2 =
4.5 12 17 - - - - - MHz
VCOIN = 6 14 21 - - - - - MHz
VCC/2
Frequency Linearity fVCO R1 = 100k 3 - 0.4 - - - - - %
R2 =
4.5 - 0.4 - - - - - %
C1 = 100pF
6 - 0.4 - - - - - %
Offset Frequency R2 = 220k 3 - 400 - - - - - kHz
C1 = 1nF
4.5 - 400 - - - - - kHz
6 - 400 - - - - - kHz
DEMODULATOR SECTION
VOUT VS fIN R1 = 100k 3 - - - - - - - mV/kHz
R2 =
4.5 - 330 - - - - - mV/kHz
C1 = 100pF
RS = 10k 6 - - - - - - - mV/kHz
R3 = 100k
C2 = 100pF
HCT TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPHL, tPLH
SIGIN, COMPIN to PCIOUT CL = 50pF 4.5 - - 45 - 56 - 68 ns
SIGIN, COMPIN to PCPOUT tPHL, tPLH CL = 50pF 4.5 - - 68 - 85 - 102 ns
SIGIN, COMPIN to PC3OUT tPHL, tPLH CL = 50pF 4.5 - - 58 - 73 - 87 ns
Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns
Output Enable Time, SIGIN, tPZH, tPZL CL = 50pF 4.5 - - 60 - 75 - 90 pF
COMPIN to PC2OUT
Output Disable Time, SIGIN, tPHZ, tPLZ CL = 50pF 4.5 - - 68 - 85 - 102 pF
COMPIN to PCZOUT
AC Coupled Input Sensitivity VI(P-P) 4.5 - 15 - - - - - mV
(P-P) at SIGIN or COMPI
VCO SECTION
Frequency Stability with f R1 = 100k, 4.5 - 0.11 - - - - - %/oC
Temperature Change T R2 =
Maximum Frequency fMAX C1 = 50pF 4.5 - 24 - - - - - MHz
R1 = 3.5k
R2 =
C1 = 0pF 4.5 - 38 - - - - - MHz
R1 = 9.1k
R2 =
Center Frequency C1 = 40pF 4.5 12 17 - - - - - MHz
R1 = 3k
R2 =
VCOIN =
VCC/2
Frequency Linearity fVCO R1 = 100k 4.5 - 0.4 - - - - - %
R2 =
C1 = 100pF
11
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Offset Frequency R2 = 220k 4.5 - 400 - - - - - kHz
C1 = 1nF
DEMODULATOR SECTION
VOUT VS fIN R1 = 100k 4.5 - 330 - - - - - mV/kHz
R2 =
C1 = 100pF
RS = 10k
R3 = 100k
C2 = 100pF
SIGIN
INPUTS VS
SIGIN COMPIN
INPUTS VS
FIGURE 8. INPUT TO OUTPUT PROPAGATION DELAYS AND FIGURE 9. THREE STATE ENABLE AND DISABLE TIMES FOR
OUTPUT TRANSITION TIMES PC2OUT
II
VI
VI
12
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
108 108
R1 = 2.2K R1 =3K
107 R1 = 22K 107 R1 = 30K
R1 = 220K R1 =330K
CENTER FREQUENCY (Hz)
104 104
103 103
102 102
FIGURE 11. HC4046A TYPICAL CENTER FREQUENCY vs R1, FIGURE 12. HC4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (VCC = 4.5V) C1 (VCC = 6V)
108 108
R1 = 1.5K R1 = 2.2K
R1 = 15K 107 R1 = 22K
107 R1 = 150K R1 = 220K
CENTER FREQUENCY (Hz)
CENTER FREQUENCY (Hz)
105 105
104 104
103 103
FIGURE 13. HC4046A TYPICAL CENTER FREQUENCY vs R1, FIGURE 14. HCT4046A TYPICAL CENTER FREQUENCY vs R1,
C1 (VCC = 3V, R2 = OPEN) C1 (VCC = 4.5V)
108 140
R1 = 3K C1 = 50pF
R1 = 30K VCC = 6V
107 R1 = 1.5M
R1 = 300K 120
CENTER FREQUENCY (Hz)
R1 = 3M
106 R1 = 15M
100
105 VCC = 4.5V
104 80
103 60 VCC = 3V
102
40
VCOIN = 0.5 VCC
10
VCC = 5.5V
1 20
1 10 102 103 104 105 106 0 1 2 3 4 5 6
FIGURE 15. HCT4046A TYPICAL CENTER FREQUENCY vs R1, FIGURE 16. HC4046A TYPICAL VCO FREQUENCY vs VCOIN
C1 (VCC = 5.5V) (R1 = 1.5M, C1 = 50pF)
13
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
90 800
C1 = 0.1F VCC = 6V C1 = 0.1F VCC = 6V
80 R1 = 1.5M R1 = 150K
700
70
600
VCC = 4.5V VCC = 4.5V
60
500
50
VCC = 3V 400
40 VCC = 3V
30 300
20 200
10 100
0 1 2 3 4 5 6 0 1 2 3 4 5 6
FIGURE 17. HC4046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 18. HC4046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 1.5M, C1 = 0.1F) (R1 = 150k, C1 = 0.1F)
18 1400
C1 = 0.1F VCC = 6V C1 = 50pF VCC = 6V
16 R1 = 5.6k 1200 R1 = 150K
VCC = 4.5V
VCO FREQUENCY (kHz)
14
VCC = 3V 1000 VCC = 4.5V
12
10 800
VCC = 3V
8
600
6
4 400
2 200
0 1 2 3 4 5 6 0 1 2 3 4 5 6
FIGURE 19. HC4046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 20. HC4046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 5.6k, C1 = 0.1F) (R1 = 150k, C1 = 50pF)
24 24
C1 = 50pF VCC = 6V VCOIN = 0.5 VCC
VCO FREQUENCY CHANGE, f (%)
20 R1 = 1.5M
C1 = 50pF, VCC = 3V
R1 = 5.6K
20 16 R2 = OPEN
VCO FREQUENCY (MHz)
12
VCC = 4.5V R1 = 150K
16 8
4
12 VCC = 3V 0 R1 = 3K
-4
8 -8
R1 = 1.5K
-12
4 -16
0 1 2 3 4 5 6 -75 -50 -25 0 25 50 75 100 125 150
VCOIN (V) AMBIENT TEMPERATURE, TA (oC)
FIGURE 21. HC4046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 22. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
(R1 = 5.6k, C1 = 50pF) vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (VCC = 3V)
14
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
FIGURE 23. HC4046A TYPICAL CHANGE IN VCO FREQUENCY FIGURE 24. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (VCC = 4.5V) R1 (VCC = 6V)
20
VCOIN = 0.5 VCC 20 VCOIN = 0.5 VCC
VCO FREQUENCY CHANGE, f (%) R1 = 2.2M
C1 = 50pF, VCC = 4.5V
VCO FREQUENCY CHANGE, f (%)
0 0
R1 = 3K
-4 -4 R1 = 2.2K
-8 -8
-12 -12
-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE, TA (oC) AMBIENT TEMPERATURE, TA (oC)
FIGURE 25. HCT4046A TYPICAL CHANGE IN VCO FIGURE 26. HC4046A TYPICAL CHANGE IN VCO FREQUENCY
FREQUENCY vs AMBIENT TEMPERATURE AS A vs AMBIENT TEMPERATURE AS A FUNCTION OF
FUNCTION OF R1 R1 (VCC = 4.5V)
15
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
108 108
107 107
OFFSET FREQUENCY (Hz)
R2 = 220K R2 = 150K
103 103
R2 = 2.2M R2 = 1.5M
102 102
FIGURE 27. HC4046A OFFSET FREQUENCY vs R2, C1 FIGURE 28. HC4046A OFFSET FREQUENCY vs R2, C1
(VCC = 4.5V) (VCC = 3V)
108 108
107 107
OFFSET FREQUENCY (Hz)
106 106
R2 = 2.2K
R2 = 3K
105 105
R2 = 22K R2 = 30K
104 104
R2 = 220K R2 = 300K
103 103
R2 = 2.2M R2 = 3M
102 102
VCOIN = 0.5 VCC
10 VCOIN = 0.5 VCC 10 HC VCC = 6V
VCC = 4.5V R2 = 11M HCT VCC = 5.5V R2 = 15M
1 1
1 10 102 103 104 105 106 1 10 102 103 104 105 106
CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF)
FIGURE 29. HCT4046A OFFSET FREQUENCY vs R2, C1 FIGURE 30. HC4046A AND HCT4046A OFFSET FREQUENCY
(VCC = 4.5V) vs R2, C1 (VCC = 6V, VCC = 5.5V)
PIN 9 = 0.95 VCC FOR fMAX PIN 9 = 0.95 VCC FOR fMAX
102 PIN 9 = 0V FOR fMIN 102 PIN 9 = 0V FOR fMIN
VCC = 3V, 4.5V, 6V VCC = 4.5V TO 5.5V
fMAX /fMIN
fMAX /fMIN
10 10
0 0
10-2 10-1 1 10 102 10-2 10-1 1 10 102
R2/R1 R2/R1
FIGURE 31. HC4046A fMIN/fMAX vs R2/R1 (VCC = 3V, 4.5V, 6V) FIGURE 32. HCT4046A fMAX/fMIN vs R2/R1 (VCC = 4.5V TO 5.5V)
16
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
8
C1 = 50pF
6 VCC = 4.5V
R2 = OPEN
f 4
VCOIN = 2.25V 1V
LINEARITY (%)
f2 2
f0
V = 0.5V OVER THE VCC RANGE: 0 VCOIN = 2.25V 0.45V
f0 FOR VCO LINEARITY
fo = f1 + f2 -2
f1 2 fo - fo
LINEARITY = f x 100% -4
o
V V -6
-8
MIN 1/2VCC MAX 1K 10K 100K 1M 10M
VVCOIN R1 (OHMS)
FIGURE 33. DEFINITION OF VCO FREQUENCY LINEARITY FIGURE 34. HC4046A VCO LINEARITY vs R1 (VCC = 4.5V)
8 8
C1 = 50pF C1 = 50pF
6 VCC = 3V 6 VCC = 6V
R2 = OPEN R2 = OPEN
4 4
VCOIN = 3V 1.5V
LINEARITY (%)
LINEARITY (%)
0 0
VCOIN = 1.50V 0.3V
-2 -2
-4 -4
VCOIN = 3V 0.6V
-6 -6
-8 -8
1K 10K 100K 1M 10M 1K 10K 100K 1M 10M
R1 (OHMS) R1 (OHMS)
FIGURE 35. HC4046A VCO LINEARITY vs R1 (VCC = 3V) FIGURE 36. HC4046A VCO LINEARITY vs R1 (VCC = 6V)
DEMODULATOR POWER DISSIPATION, PD (W)
8
VCC = 5.5V, 104
VCOIN = 2.75V 1.3V VCOIN = 0.5 VCC
6
VCC = 4.5V,
VCOIN = 2.25V 1.0V
4 103
VCC = 6V
LINEARITY (%)
0 102
VCC = 3V VCC = 4.5V
-2 VCC = 5.5V,
VCOIN = 2.75V 0.55V
-4 VCC = 4.5V, 10
VCOIN = 2.25V 0.45V
C1 = 50pF
-6
R2 = OPEN
-8 1
1K 10K 100K 1M 10M 1K 10K 100K 1M
R1 (OHMS) RS (OHMS)
FIGURE 37. HCT4046A VCO LINEARITY vs R1 (VCC = 4.5V, FIGURE 38. HC4046A DEMODULATOR POWER DISSIPATION
VCC = 5.5V) vs RS (TYP) (VCC = 3V, 4.5V, 6V)
17
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
106
DEMODULATOR POWER DISSIPATION, PD (W)
FIGURE 39. HCT4046A DEMODULATOR POWER DISSIPATION FIGURE 40. HC4046A VCO POWER DISSIPATION vs R1
vs RS (TYP) (VCC = 3V, 4.5V, 6V) (C1 = 50pF, 1F)
106 106
VCOIN = 0V (AT fMIN) VCOIN = 0.5V
VCC = 6V
VCO POWER DISSIPATION, PD (W)
VCO POWER DISSIPATION, PD (W)
R1 = RS = OPEN R2 = RS = OPEN
C1 = 50pF CL = 50pF VCC = 5.5V
C1 = 50pF
105 105
102 102
1K 10K 100K 1M 1K 10K 100K 1M
R2 (OHMS) R1 (OHMS)
FIGURE 41. HCT4046A VCO POWER DISSIPATION vs R2 FIGURE 42. HCT4046A VCO POWER DISSIPATION vs R1
(C1 = 50pF, 1F) (C1 = 50pF, 1F)
106
VCOIN = 0V (AT fMIN)
VCC = 6V
VCO POWER DISSIPATION, PD (W)
R1 = RS = OPEN
C1 = 50pF CL = 50pF
105 VCC = 4.5V
C1 = 50pF
VCC = 6V
104 C1 = 1F
VCC = 3V
C1 = 1F
VCC = 3V
103 C1 = 50pF
VCC = 4.5V
C1 = 1F
102
1K 10K 100K 1M
R2 (OHMS)
18
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
PHASE
SUBJECT COMPARATOR DESIGN CONSIDERATIONS
VCO Frequency PC1, PC2 or PC3 VCO Frequency Characteristic
Without Extra Offset With R2 = and R1 within the range 3k < R1 < 300k, the characteristics of the VCO
operation will be as shown in Figures 11 - 15. (Due to R1, C1 time constant a small offset
remains when R2 = .)
fMAX
fVCO
fo 2fL
fMIN
MIN 1/2 VCC VVCOIN MAX
fMIN
19
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
PHASE
SUBJECT COMPARATOR DESIGN CONSIDERATIONS
PLL Conditions with PC1 VCO adjusts to fo with DEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2)
No Signal at the PC2 VCO adjusts to fMIN with DEMOUT = -360o and VVCOIN = 0V (see Figure 4)
SIGIN Input
PC3 VCO adjusts to fMAX with DEMOUT = 360o and VVCOIN = VCC (see Figure 6)
PLL Frequency PC1, PC2 or PC3 Loop Filter Component Selection
Capture Range
|F(j)|
R3
-1/
INPUT C2 OUTPUT
(A) = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
A small capture range (2fc) is obtained if > 2fc 1/ (2fL/.)1/2
FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
R3
|F(j)| R4
m=
R4 R3 + R4
INPUT OUTPUT -1/2 -1/3
C2 m
1/3 1/2
(A) 1 = R3 x C2; (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
2 = R4 x C2;
3 = (R3 + R4) x C2
20
PACKAGE OPTION ADDENDUM
www.ti.com 25-Oct-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
5962-8875701EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8875701EA
CD54HCT4046AF3
A
5962-8960901EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960901EA
CD54HC4046AF3A
CD54HC4046AF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4046AF
CD54HC4046AF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8960901EA
CD54HC4046AF3A
CD54HCT4046AF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8875701EA
CD54HCT4046AF3
A
CD74HC4046AE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4046AE
(RoHS)
CD74HC4046AEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4046AE
(RoHS)
CD74HC4046AM ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AM96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AMT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046ANSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
CD74HC4046ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4046AM
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 25-Oct-2016
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD74HC4046APWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4046A
& no Sb/Br)
CD74HC4046APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4046A
& no Sb/Br)
CD74HC4046APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4046A
& no Sb/Br)
CD74HC4046APWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4046A
& no Sb/Br)
CD74HCT4046AE ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4046AE
(RoHS)
CD74HCT4046AEE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4046AE
(RoHS)
CD74HCT4046AM ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AM96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AMG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
CD74HCT4046AMT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4046AM
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 25-Oct-2016
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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