Integration of Spin-RAM technology in FPGA circuits
W. Zhao*1, E. Belhaire1, Q. Mistral1, E. Nicolle2, T. Devolder1, C. Chappert1
1. Institut dElectronique Fondamentale, University of Paris 11/ CNRS, France
2. STMicroelectronics, 850, Rue Jean Monnet, F38926 Crolles, France
*Email: zhao@ief.u-psud.fr
Abstract
In this paper, we propose a new non-volatile FPGA
circuit based on Spin-RAM technology (Spin Transfer
Torque Magnetisation Switching RAM), new generation
of MRAM (Magnetic RAM). This Spin-RAM based
FPGA circuit could process securely the information in
low power dissipation and high speed; meanwhile all the
data processed are stored permanently in the distributed
Spin-RAM memory. In this non-volatile FPGA design,
MTJs (Magnetic Tunnel Junction) are used as storage
elements. Contrary to conventional MRAM circuits we
dont use a complex sense amplifier, but a simple SRAM
based sense amplifier couples two MTJs per bit. The
non-volatility of Spin-RAM allows the dynamical
configuration of FPGA circuits and the start-up time of
circuit can be decreased up to some hundred pico
seconds. As conventional MRAM, the MTJs of
Spin-RAM will be on the semiconductor surface;
therefore the circuit die area will not be enlarged
comparing with the conventional FPGA.
1. Introduction
In the last 10 years, FPGA [1] circuits have developed
rapidly, because of their configurability, their easy use
and the low cost to design a function on them. However,
the internal memories used in FPGA circuits could limit
their future development. Most FPGA circuits use
SRAM based configuration [2] and Flip-Flop [3] as
internal memory; but as the SRAM is volatile both their
configuration and the information stored in their internal
registers are lost when the power is turned down. The
configuration is then stored in an external PROM and
downloaded in the FPGA at startup. Internal Flash
technology is now sometime used to replace the external
memory [4], however its slow reprogramming and its
limited number of writing cycles (up to 106) prevent its
application to replace the SRAM based internal registers,
which work at very high frequency [3].
High writing and reading speed makes Spin-RAM (Spin
Transfer Torque Magnetization RAM) technology [5] as
one of the best solutions to bring a complete
non-volatility to FPGA circuits while keeping low power
dissipation. A MTJ (Magnetic Junction Tunnel), as
Spin-RAM storage element, can be re-programmed more
than 1012 times and has a large retention time of up to 10
years. A lot of progress of this memory in the technology
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has been done, especially by Sony [6], Hitachi [7] and
Samsung [8] in the last years.
Conventional FIMS (Field induced Magnetic Switching)
writing approach based MRAM [9-11] technology has
been proposed to implement the non-volatile
configuration [12] and non-volatile register [13] in
FPGA; however the die area of this FPGA circuit is
much larger than the classical FPGA circuit, because the
conventional MRAM technology need large current to
write the information in the MTJs and then requires
some large transistors. Spin-RAM is based on Spin
Transfer Torque Magnetization writing approach, which
figures low writing current [7]. As the MTJs are
processed over the chip surface [9], shown in Fig. 1.1,
and they are in very small size (e.g. 100nm80nm),
Spin-RAM based FPGA circuit does not take more die
area than the classical FPGA and the actual layout of
semiconductor circuit is barely affected, by the
non-volatile property addition.
Figure 1.1 the position of MTJs
In this paper, we introduce firstly the Spin-RAM in the
second section; the three Spin-RAM based logic
components are shown in the third section and the
performance comparison between the Spin-RAM based
FPGA, MRAM based FPGA and SRAM based FPGA is
presented in the fourth third section.
2. Spin-RAM Introduction
Magnetic Tunnel Junction (MTJ) is used as the storage
element of Spin-RAM. It is mainly composed by three
layers (Fig. 2.1), 2 ferromagnetic layers and one oxide
barrier. A MTJ behaves as a resistor with two resistance
characteristics (high and low) depending on the
magnetization direction in the two ferromagnetic layers.
A MTJ presents a low (respectively high) resistance
when the spin transport is in the same (resp. opposite)
direction in two ferromagnetic layers. This resistance among the logic components. There are two types of
variation behavior was observed firstly by Julliere [14] memory points, the configuration memory (Look up
in 1975. The ratio between the two resistances at zero table and Interconnection switch) and the registers
bias is named TMR (Tunneling Magnetoresistance Ratio) (Latch or Flip-Flop), see Fig. 3.1.
and is defined in Equ. (E.1). The TMR is currently up to
70% in an AlxO barrier MTJ and 230% in an MgO
barrier MTJ [15].
R RP (E.1)
TMR = AP
R Ap

Figure 3.1 the two types of memory in FPGA circuit

(a) (b)
Figure 2.1(a) Low resistance MTJ (b) High resistance
MTJ
This improvement of TMR allows a simple CMOS
sensing circuit to read the information in MTJs more
easily when the low and high resistance represent
different bit of information. There are currently three
MTJ writing approaches, FIMS [9-11], TAS (Thermally
assisted switching) [16] and Spin transfer torque. The
high switching current (>mA) requirement of the first
writing approache limits its applications with Standard
CMOS chip. Slonczewski [17] showed that there is a
threshold current density for switching MTJ in 1996,
named critical current density. If the current density in
the MTJ is bigger than the critical current density, the
MTJ state will change (Fig. 2.2), the positive and
negative directions of current determines the MTJ state
changing from parallel (P) to anti-parallel (AP) or AP to
P. This critical current density has been found as low as
8*105 A/cm2 [7]; as the dimension of MTJ is very small,
the critical current is about 100uA and can now be easily
generated by some small transistors.
Figure 2.2 The MTJ state changes from Parallel (P) to
Anti-parallel (AP) if the positive direction current
density I>Ic, on the contrast, its state will return if the
negative direction current density I > Ic.
This distributed character of the memory imposes to the
sensing structure to be much simpler than in a standard
MRAM memory. In our Spin-RAM based FPGA design,
two complementary MTJs are used per bit and a simple
SRAM based sensing structure is applied for reading the
information in the two MTJs as represented in Fig. 3.2
[18]. This sensing structure works at very high speed
[13]. The cell sense the magnetic information by briefly
turning on the MN2 switch and then promptly turning it
off (NR is the reading control signal). Thanks to our
simulation the output stabilise after about 200 ps, which
allows the FPGA circuits to realize a real instant-on.
Figure 3.2 Sensing structure of Spin-RAM based FPGA
We have mentioned above that Spin transfer torque
writing approach needs a bi-directional current to write
the information in the MTJ, so that a bi-directional
current generator is used , as represented in Fig. 3.3, in
this one bit distributed Spin-RAM; NW is the writing
control signal as comparable to enable in the classical
logic components. These transistors are in small size
because of the low writing current required in this
writing approach.

3. Spin-RAM based logic components

3.1 One bit distributed Spin-RAM in FPGA circuit
The memory points used in FPGA are not like in Figure 3.3 Writing circuit of one bit distributed
ordinary memory chip because they are distributed Spin-RAM

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The complete one bit distributed Spin-RAM is shown in
Fig. 3.4a where NW and NR control the writing and
reading of the couple of MTJs. The CMOS part of the
one bit distributed Spin-RAM has been evaluated at the
layout level with Cadence virtuoso and its size is about
5.5*7.1um2 in a 90nm technology. The 8 bits distributed
Spin-RAM can be implemented with an additional
selecting coder (Fig. 3.5). This structure can be used in
the interconnection and the LUT (Look up table) of a
FPGA to implement the dynamical configuration
function with up to eight different configuration.
(a)
(b)
Figure 3.4 (a) one bit distributed Spin-RAM (schematic)
(b) one bit distributed Spin-RAM (layout 5.5*7.1um2 )
Figure 3.5 Eight bits distributed Spin-RAM
3.2 Spin-RAM based Interconnection switch and LUT
The interconnection switch memorizes the connection
routes between the logic elements. In a conventional
FPGA circuit, the structure of interconnection,
represented in Fig. 3.6a, includes 6 transistors and 6
SRAM which must be programmed at the circuit
start-up.
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Figure 3.6 (a) the structure of interconnection based on
SRAM (b) the structure of interconnection based on
Spin-RAM
In Spin-RAM based FPGA circuit, the SRAM is
replaced by a one bit distributed Spin-RAM (Fig 3.4 and
3.6b). Thanks to the non-volatility of Spin-RAM, this
FPGA circuit does not require the external Flash ROM
memory and therefore there is no initialization phase at
chip restart. By using multi bits distributed Spin-RAM
(e.g. 8 bits as in Fig. 3.5); Multi-context configuration
can be easily implemented and the FPGA circuit is
dynamically configurable.
The LUT behaves as a function generator, composed by
a coder and some bits distributed RAM as represented in
Fig. 3.6. It is similar to the structure shown in Fig. 3.5. In
this latter one a 3-input Spin-RAM based non-volatile
LUT replaces the Flash ROM and the SRAM. LUT with
more inputs LUT can be designed the same way. As we
already mentioned in the first section, MTJs are on top
of the chip surface and the area increase to implement
this multi-context configuration FPGA is estimated as
negligible.
Figure 3.6 SRAM based LUT (Look up table)
3.3 Spin-RAM based Flip-Flop
In a FPGA circuit, the Flip-Flops are used as registers to
temporarily store the results proceeded and synchronize
them with the global clock. It is one of the most
important components in FPGA circuit as it partially
determines the data processing speed and it is at the
origin of a significant part of the total power
consumption. SRAM [3] based master-slave Flip-Flop is
widely used in current FPGA circuit implementations.
The Master and Slave parts are both clock-controlled
latches (see Fig. 3.7). The master part is used to write the
information in the Flip-Flop and the slave part is used to
output this information, the global clock and its
anti-phase clock control the overall process.
In our Spin-RAM based Flip-Flop design, a one-bit
distributed Spin-RAM is used to replace the master latch
in the master slave Flip-Flop and the clock then control
the writing and reading phases of the MTJs (Fig. 3.8).
Figure 3.8 Spin-RAM based Flip-Flop
In Spin-RAM integrated circuit, high speed switching
within 2 ns pulse has been demonstrated by Sony [6] and
for the SRAM based sensing structure, the reading time
is as low as 200ps [13]. The overall propagation delay is
then around 2.2ns and this Spin-RAM based Flip-Flop
can process information at an estimated frequency as
high as 480MHz.
4. Comparison with other memory technology
The circuit performance in terms of surface, power
dissipation, processing speed and non-volatility are
compared with SRAM, Flash and conventional MRAM
technology in Table 4.1 and 4.2.
Table 4.1: Comparison of different memory technologies
for the configuration of FPGA circuits
Table 4.2: Comparison of different memory technologies
for the register or Flip-Flop in FPGA circuits
Spin-RAM provides all the advantages of non-volatility,
high speed, low power dissipation and high density, and
this demonstrates that Spin-RAM technology is a very
promising solution for the future FPGA.
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5. Conclusion
This Spin-RAM based FPGA features simultaneously
non-volatility, high processing speed and low power
dissipation. Multi-context configuration or dynamical
re-configuration FPGA can be implemented easily and
with small physical surface overhead, therefore it could
be a technological choice in multi functions processing
circuit, such as MP3 player or Mobile phones. The
Spin-RAM based Flip-Flop can also be used to replace
all the registers in SOC (System-on-chip) to make these
chips non-volatile and secure. Therefore it could be
advantageously used in the field of aviation and space
where the security of information is one of the most
important considerations.
Acknowledgment
The work and results reported were obtained with
research funding from the European Community under
the sixth Framework, Contract Number 510993:
MAGLOG. The views expressed are solely those of the
authors, and the other Contractors and/or the European
Community cannot be held liable for any use that may be
made of the information contained herein.
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