SIMULATION PROGRAMS USING XILINX ISE

1. DESIGN AND SIMULATION OF 8BIT ADDER

MAIN MODULE
module Adder_8_Sim(cout,sum,a,b,cin);
output cout;
output[7:0]sum;
input[7:0]a,b;
input cin;
wire[6:0]c;
fullAdder FA1(c[0],sum[0],a[0],b[0],cin);
fullAdder FA2(c[1],sum[1],a[1],b[1],c[0]);
fullAdder FA3(c[2],sum[2],a[2],b[2],c[1]);
fullAdder FA4(c[3],sum[3],a[3],b[3],c[2]);
fullAdder FA5(c[4],sum[4],a[4],b[4],c[3]);
fullAdder FA6(c[5],sum[5],a[5],b[5],c[4]);
fullAdder FA7(c[6],sum[6],a[6],b[6],c[5]);
fullAdder FA8(cout,sum[7],a[7],b[7],c[6]);
endmodule

FULL ADDER MODULE

module fullAdder(cout,sum,a,b,cin);
output cout,sum;
input a,b,cin;
wire c1,c2,c3,s1;
xor g1(s1,a,b);
xor g2(sum,s1,cin);
and g3(c1,a,b);
and g4(c2,a,cin);
and g5(c3,b,cin);
or g6(cout,c1,c2,c3);
endmodule

2. DESIGN AND SIMULATION OF 4BIT MULTIPLIER

MAIN MODULE
input [3:0] a;
input [3:0] b;
output [7:0] p;
wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14;
wire s0,s1,s2,s3,s4,s5;
wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
and(p[0],a[0],b[0]); // 0th bit of result 'p'
and(w0,a[1],b[0]); // 1st bit of result 'p'
and(w1,a[0],b[1]);
halfadder HA1(p[1],c0,w0,w1);
and(w2,a[0],b[2]); // 2nd bit of result 'p'
and(w3,a[1],b[1]);
and(w4,a[2],b[0]);
halfadder HA2(s0,c1,w2,w3);
fulladder FA1(p[2],c2,c0,s0,w4);
 and(w5,a[0],b[3]); // 3rd bit of result 'p'
and(w6,a[1],b[2]);
and(w7,a[2],b[1]);
and(w8,a[3],b[0]);
halfadder HA3(s1,c3,w5,w6);
fulladder FA2(s2,c4,w7,s1,c1);
fulladder FA3(p[3],c5,w8,s2,c2);
and(w9,a[1],b[3]); // 4th bit of result 'p'
and(w10,a[2],b[2]);
and(w11,a[3],b[1]);
fulladder FA4(s3,c6,w9,w10,c3);
fulladder FA5(s4,c7,w11,s3,c4);
halfadder HA4(p[4],c8,s4,c5);
and(w12,a[2],b[3]); // 5th bit of result 'p'
and(w13,a[3],b[2]);
fulladder FA6(s5,c9,w12,w13,c6);
fulladder FA7(p[5],c10,c7,s5,c8);
and(w14,a[3],b[3]); // 6th and 7th bit of result 'p'
fulladder FA8(p[6],p[7],c9,w14,c10);
endmodule

HALF ADDER MODULE

module halfadder(sum, carry, a, b);
input a;
input b;
output sum;
output carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

FULL ADDER MODULE

input a,b,c;
output sum,carry;
wire w1,w2,w3;
xor(sum,a,b,c);
and(w1,a,b);
and(w2,c,b);
and(w3,a,c);
or(carry,w1,w2,w3);
endmodule

3. DESIGN AND SIMULATION OF ADDRESS DECODER.

module Address_Decoder_Sim(in1, sel, out2);
input [1:0] in1;
input [2:0] sel;
output [15:0] out2;
reg [7:0] select;
/* address decoder */
always @(sel)
begin
case (sel)
3'b000 : select = 8'b00000001;
3'b001 : select = 8'b00000010;
3'b010 : select = 8'b00000100;
3'b011 : select = 8'b00001000;
3'b100 : select = 8'b00010000;
3'b101 : select = 8'b00100000;
3'b110 : select = 8'b01000000;
3'b111 : select = 8'b10000000;
endcase
end
assign out2[0] = in1[0] & select[0];
assign out2[1] = in1[1] & select[0];
assign out2[2] = in1[0] & select[1];
assign out2[3] = in1[1] & select[1];
assign out2[4] = in1[0] & select[2];
assign out2[5] = in1[1] & select[2];
assign out2[6] = in1[0] & select[3];
assign out2[7] = in1[1] & select[3];
assign out2[8] = in1[0] & select[4];
assign out2[9] = in1[1] & select[4];
assign out2[10] = in1[0] & select[5];
assign out2[11] = in1[1] & select[5];
assign out2[12] = in1[0] & select[6];
assign out2[13] = in1[1] & select[6];
assign out2[14] = in1[0] & select[7];
assign out2[15] = in1[1] & select[7];
endmodule

4. DESIGN AND SIMULATION OF 8-TO-1 LINE MULTIPLEXER

module Multiplexer_8x1_Sim(en, a, y, sel);
input en;
input [7:0] a;
input[2:0] sel;
output y;
reg y;
always@(en or a)
begin
if(!en)
y=1'b0;
else
case(sel)
3'b000 : y = a[7];
3'b001 : y = a[6];
3'b010 : y = a[5];
3'b011 : y = a[4];
3'b100 : y = a[3];
3'b101 : y = a[2];
3'b110 : y = a[1];
3'b111 : y = a[0];
endcase
end
endmodule

5. DESIGN AND SIMULATION OF 4-BIT COUNTER

MAIN MODULE
module counter_4_Sim (CLK, CLR, up_down, Q);
input CLK, CLR, up_down;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge CLK or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
if (up_down)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule

TEST STIMULUS MODULE

module testCounter_v;
// Inputs
reg CLK;
reg CLR;
reg up_down;
// Outputs
wire [3:0] Q;
// Instantiate the Unit Under Test (UUT)
Counter_4_Sim uut (
.CLK(CLK),
.CLR(CLR),
.up_down(up_down),
.Q(Q)
);
initial begin
forever begin
CLK <= 0;
#5
CLK <= 1;
#5
CLK <= 0;
end
end
initial begin
forever begin
CLR = 1;
#20
CLR = 0;
#150
CLR = 1;
#10
CLR = 0;
end
end
initial begin
forever begin
up_down = 1;
#180
up_down = 0;
#180
up_down = 1;
end
end
endmodule

6. DESIGN AND SIMULATION OF PRBS GENERATOR

MAIN MODULE
module Prbs_Generator_Sim(rand, clk, reset);
input clk, reset;
output rand;
wire rand;
reg [3:0] temp;
always @ (posedge reset)
begin
temp <= 4'hf;
end
always @ (posedge clk)
begin
if (~reset)
begin
temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]};
end
end
assign rand = temp[0];
endmodule

TEST STIMULUS MODULE

module prbsGen_v;
// Inputs
reg clk;
reg reset;
// Outputs
wire rand;
// Instantiate the Unit Under Test (UUT)
Prbs_Generator_Sim uut (
.rand(rand),
.clk(clk),
.reset(reset)
);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
endmodule

7. DESIGN AND SIMULATION OF 4BITACCUMULATOR

MAIN MODULE
module Accumulator_Sim(CLK, CLR, D, Q);
input CLK, CLR;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge CLK or posedge CLR)
begin
if (CLR)
tmp <= 4'b0000;
else
tmp <= tmp + D;
end
assign Q = tmp;
endmodule

TEST STIMULUS MODULE

module accumulator_v;
// Inputs
reg CLK;
reg CLR;
reg [3:0] D;
// Outputs
wire [3:0] Q;
// Instantiate the Unit Under Test (UUT)
Accumulator uut (
.CLK(CLK),
.CLR(CLR),
.D(D),
.Q(Q)
);
initial begin
forever begin
CLK <= 0;
#5
CLK <= 1;
#5
CLK <= 0;
end
end
initial begin
forever begin
CLR = 1;
#25
CLR = 0;
#150
CLR = 1;
#25
CLR = 0;
end
end
initial begin
D = 4'b0001;
end
endmodule

FPGA IMPLEMENTATION
1. FPGA IMPLEMENTATION OF 8-BIT ADDER USING SPARTAN 3 XC3S400
VERILOG CODE
module Adder_8_FPGA(clk,addr,load,clear,data_in,calc,result);
input clk,clear,calc,load;
input [2:0]addr;
input [7:0]data_in;
output reg [7:0]result;
reg [7:0]ram[7:0];
wire [7:0]temp;
always@(posedge clk)
begin
if(~clear)
begin
ram[0]=8'b0;
ram[1]=8'b0;
ram[2]=8'b0;
ram[3]=8'b0;
ram[4]=8'b0;
ram[5]=8'b0;
ram[6]=8'b0;
ram[7]=8'b0;
end
else if(~load)
ram[addr]=data_in;
end
assign temp=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7];
always@(posedge clk)
begin
if(~load)
result=data_in;
else if(~calc)
result=temp;
else
result=ram[addr];
end
endmodule

2. FPGA IMPLEMENTATION OF 4-BIT MULTIPLIER USING SPARTAN 3

XC3S400

module Multiplier_4_FPGA(clk,addr,load,clear,data_in,calc,result);
input clk,clear,calc,load;
input addr;
input [3:0]data_in;
output reg [7:0]result;
reg [3:0]ram[1:0];
wire [7:0]temp;
always@(posedge clk)
begin
if(~clear)
begin
ram[0]=4'b0;
ram[1]=4'b0;
end
else if(~load)
ram[addr]=data_in;
end
always@(posedge clk)
begin
if(~load)
result={4'b0,data_in};
else if(~calc)
result= multiply_4x4_2sC (ram[0],ram[1]);
else
result={4'b0,ram[addr]};
end

function[7:0] multiply_4x4_2sC;
input[3:0] a,b;
reg[3:0] a_mag,b_mag;
reg[6:0] y_mag;
reg[6:0] y_neg;
begin
case (a[3])
0: a_mag = a[2:0];
1: a_mag = 8 - a[2:0];
endcase
case (b[3])
0: b_mag = b[2:0];
1: b_mag = 8 - b[2:0];
endcase
y_mag = a_mag * b_mag
if ((a[3] ^ b[3]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
begin
y_neg = 128 - y_mag[5:0];
multiply_4x4_2sC = {1'b1,y_neg};
end
else
multiply_4x4_2sC = y_mag;
end
endfunction
endmodule

3. FPGA IMPLEMENTATION OF ADDRESS DECODER USING SPARTAN 3

XC3S400
Same as simulation program

4. FPGA IMPLEMENTATION OF 8-TO-1 LINE MULTIPEXER USING SPARTAN

3 XC3S400
Same as simulation program
 5. FPGA IMPLEMENTATION OF 4-BIT COUNTER USING SPARTAN 3
XC3S400
module Counter_4_FPGA(clk, reset, count);
input clk;
input reset;
output [3:0] count;
reg[3:0] count;
integer timer_count1 = 0,timer_count2 = 0;
reg clk_msec,clk_sec;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end
always@(posedge clk_sec)
begin
if(~reset)
count = 4'b0000;
else
count = count+1;
end

TANNER EXPERIMENTS
1. INVERTER- SCHEMATIC
2. DIFFERENTIAL AMPLIFIER
FOR COMMON MODE CHANGE THE PHASE OF THE AC VOLTAGE SOURE
ARE AT 0 DEGREE

FOR DIFFERENTIAL MODE MODE CHANGE THE PHASE OF ANY ONE

OFTHE AC VOLTAGE SOURCE TO 180 DEGREE AND OTHER AT 0 DEGREE

3. NUMBER CONTROLLED OSCILLATOR

 MICROWIND EXPERIMENT
INVERTER LAYOUT DIAGRAM