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COMSATS Institute of Information Technology: LAB #05: Multiplier (Gate Level and Data Flow Models)
COMSATS Institute of Information Technology: LAB #05: Multiplier (Gate Level and Data Flow Models)
Class: BEE-VI
Procedure:
First of all, open Xilinx ISE and make new project.
Select device XC6SLX16 and add Verilog module file.
Write code to implement two bit multiplier and run it.
Make RTL file and save it.
Create Verilog fixture file and add all the input schemes with 100ns delay.
Observe wave diagram and verify your theoretical results and save it.
Open user constraints and assign I/Os to have result for two bit multiplier and save
it.
Re-run the code and generate bit file.
Connect the hardware and open configure target device.
First auto-connect the cable in the window of iMPACT software and then add your
Xilinx device.
Program it and test your results practically and match it with wave diagrams
results.
Repeat this experiment for two bit multiplier using data flow modeling.
Conclusion:
In this experiment we learnt about the syntax of multiplier and observed the behavior
of comparator practically on Spartan 6 FPGA kit.
Task1: Two Bit Multiplier (Gate Level) RTL Image:
Code:
module Two_Multiplier_Module(
input[1:0] a,b,
output [3:0] mul);
wire y;
assign mul[0]= a[0] & b[0];
assign
{y,mul[1]}=((a[0]&b[1])+(a[1]&b[0]));
assign {mul[3],mul[2]}=(y+(a[1]&b[1]));
endmodule
Wave Diagram:
Task2: Two Bit Multiplier (Data Flow) RTL Image:
Code:
module TWO_MUL_Module(input
[1:0] a,b, output [3:0] mul);
assign mul=a*b;
endmodule