F eature S tory

A New Approach to Identifying

Large, Yield-Impacting Defects
on Polished Si Wafers
Kerem Kapkin, KeunSu Kim, Jason Saito, Hyosik Suh KLA-Tencor Corporation
Chung Geun Koh, Dae Jong Kim, Byeong Sam Moon, Seung Ho Pyi Hynix Semiconductor Corporation

For 45nm-generation wafers, innovations in bare wafer inspection technology provide enhanced capture and
classification of large, shallow defects. New classification technology, combined with multi-channel processing, enables
wafer manufacturers and IC device makers to find and separate these defects into categories based on whether they are
cleanable, or require scrapping the wafer. Identifying these defects early in the manufacturing process enables improved
product quality and higher yield.

As devices continue to shrink, wafer surface condition, defect
size, shape and type are becoming increasingly important
factors in device yield, performance and reliability. ITRS (Inter
national Technology Roadmap for Semiconductors) guidelines
stipulate a sensitivity to critical defects on a bare wafer surface
of a size equal to one-half the design rule.
At the same time, IC manufacturers have been reducing the
specification for the total number of defects allowed for accep-
tance of incoming wafers and are now specifying limits on the
number of large light point defects (LLPDs). These LLPDs are
large but very shallow: they may be several microns wide but
have a height of only a few nanometers. LLPDs are generated
both during single-crystal silicon ingot growth and during
the subsequent wafer-making and surface-preparation pro-
cesses. These LLPDs manifest themselves on incoming bare
silicon wafers in the form of faceted pits or bumps, air pockets
and polishing scratches, and have a very high likelihood of
becoming yield killer defects. Thus, IC manufacturers must
identify and sort out wafers with LLPDs before beginning
device processing.
Wafer manufacturers need to detect, accurately identify and
separate these defects from the background population of large
particles, which may be cleaned or reworked, while avoiding
unneeded wafer rejection. Also, since LLPDs are a result of
various wafer manufacturing process issues, wafer manufactur-
ers must quickly identify the LLPD root cause and implement
fixes to prevent unnecessary wafer scrap.
In this article, we demonstrate a method for classifying these
critical LLPDs by utilizing a new unpatterned wafer inspection
system, the Surfscan SP2XP. The systems latest technologies
of GC (global composite) and RBB (rules-based binning) have
proven effective for both the wafer manufacturers final inspec-
tion step and IC device manufacturing IQC (Incoming Quality
Control) applications.

Particle COP Residue Scratch

0.1m 0.1m 0.1m 0.1m

Figure 1: Conventional defects or LPDs (Light Point Defects) which require increased sensitivity for detection and classification.

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F eature S tory
Wafer Defect Types and Their Sources
Conventional small (sub-micron) defects that impact device
yield include particles, COPs (crystal originated pits or
particles), residues and scratches, and are well characterized.
Examples of these defect types are pictured in Figure 1. Large
particle defects on the wafer may originate from handling
contamination, process equipment, or from the cleanrooms
ambient environment. Many of these can be removed with
various cleaning processes.
LLPDs are more challenging to identify and characterize. A
typical simplified Si wafer production scheme is shown in
Figure 2. The source of faceted LLPD defects can be divided
into two primary groups: the crystal-growing process and the
wafering process.
The Surfscan SP2XP inspection
system can identify large light point
defects by type, size and number.
Previously, the full spectrum of LLPD defects could not be
separated by type or source and could only be categorized as
one group based on their darkfield scattering signatures.
However, their identification and classification by individual
type is very important. Wafer manufacturers can use this infor-
mation to isolate various process-related problems and crystal
growth issues, then implement corrective measures. IC device
manufacturers can use classification information to create their
incoming wafer quality acceptance specifications based on
specific LLPD type, defect size and number.
Conventional technology and methods in use by IC manufac-
turers for testing incoming wafer quality are as follows:
1st Step - Unpatterned inspection tool 1st sampling
2nd Step - Manual visual inspection for confirmation
3rd Step - SEM verification
Until now, wafer manufacturers have been unable to identify
and classify LLPDs effectively, especially the separation of an
Crystal Wire Saw Lapping
LLPD (Crystal)
Figure 2: Simplified Si wafer manufacturing process and faceted LLPD.
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Large defects (~16m)
Figure 3: Emerging (faceted) LLPD defects (polishing related defects,
air pockets and etch-related defects, respectively).
important defect type on bare Si wafers faceted LLPDs
(Figure 3). The most critical faceted LLPD is the air pocket
defect, which forms during the crystal-pulling process and is
distributed across the wafer within the silicon substrate. The
size of the air pocket exposed to the surface is a function of
its location and how much has been revealed during cutting
and polishing of the wafer. While exposed air pockets can be
measured in various sizes as pits, the buried ones in the bulk
remain as voids.
Other types of faceted defects are created by either mechanical or
chemical damage during etching or polishing steps. Although
they are limited to the wafer surface and do not exist within
the substrate, they can affect implant profile, device topogra-
phy and electrical properties, which can destroy a die. Some
faceted LLPDs can be reworked with further polishing and
etching if caught during inline process monitoring.
Methods to Detect and Classify LLPD to Prevent
Yield Impact
Wafer manufacturers require a production-worthy inspection
technology that allows inspection of all outgoing wafers for all
defects of interest (DOIs), with high throughput and economi-
cal operating cost. It is necessary to capture the full range of
DOI types and to automatically classify them with the highest
accuracy and purity. This will prevent out-of-spec wafers from
reaching the IC device manufacturer and eliminate unneces-
sary wafer rejection and scrap due to false positives.
Etching Polishing Inspection
LLPD (Wafering process)
4
F eature S tory

capture a phase difference, which reveals height or slope in-

Wide
formation, as shown in Figure 5. This DIC technology allows
Narrow Normal and BF detection of defects that are large, flat or shallow and may not
Illumination be detected by darkfield channels.
After complete optical information of the wafer surface has
been captured, it is analyzed using a new algorithm known as
Bright rules-based binning (RBB). RBB allows the user to compare
Field mathematical or logical conditions between the five defect
Collector
DIC channels (BF DIC, DF Normal Wide, DF Normal Narrow, DF
Oblique Wide, DF Oblique Narrow), as shown in Figure 6.

Rotating The results of these logical comparisons can be used to classify

Wafer Scan the defects of interest. All darkfield channels can be combined
Oblique as the darkfield composite and all five channels, including
Illumination
brightfield, can be combined as the grand composite. The
Figure 4: Surfscan SP2XP illumination and optics technology. grand composite and brightfield channels serve to identify

The most important goal of the first inspection step is to Oblique Normal BF DIC
capture complete surface optical information with the highest
possible sensitivity at a production-worthy throughput. As
Wide
shown in Figure 4, the new system illuminates the bare
Si wafer with both normal and oblique incidence 355nm
UV laser beams to provide darkfield (DF) detection of DOIs.
The light scattered from the various defect types is collected
by both wide and narrow detectors, enabling further analysis
and classification. This architecture results in four distinct
Narrow

light collection channels (oblique narrow, oblique wide, nor-

mal narrow and normal wide).
In addition to the multi-channel darkfield collection, the sys-
tem also employs a new brightfield (BF) illumination channel Figure 6: Surfscan SP2XP creates five (5) channels of information for
to capture other defect types or surface characteristics. This BF each defect.
technology utilizes differential interference contrast (DIC) to

Signal Convex Step Concave

A B C D E
0

Time

A B C D E
Beam motion Arbitrary surface

Figure 5: Brightfield (BF) illumination and differential interference contrast (DIC) technology.

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F eature S tory

Case Study 2: Twenty-three 200mm wafers

Grand Classification with Defect
composite rules-based binning classification In this case study, twenty-three 200mm wafers obtained from
various wafer manufacturers were similarly scanned and the
Brightfield RBB LPD results combined for comparison of the conventional method
versus the new RBB approach. SEM review confirmed a total
of 28 LLPD defects on these 23 wafers.
LLPD The conventional method reported a total of 65 LLPDs
crystal
Grand Grand composite -- 20 LLPDs were classified correctly
composite with RBB -- 45 particles were misclassified as LLPDs
LLPD
wafering
-- 8 LLPDs were not detected at all
The results of this case study are shown in Figure 10.
Darkfield LLPD
The conventional method would have caused a 69% increase
composite wafering
in false wafer rejection due to misclassification of particles as
LLPD defects, and a 29% miss rate on LLPD defects which
Figure 7: Rules-based binning classification results. could have caused an unexpected device yield impact at the
IC device manufacturer.
LLPD defects, and RBB is used to further separate LLPD de- The new approach detected all of the 28 LLPDs successfully, as
fects into particles, air pockets, polishing pits and etch defects. verified by the SEM review.
Schematic analysis is shown in Figure 7.
The data used in Figure 8 were obtained from seven 300mm Electrical Analysis of LLPD Defect Types: Large Particles
wafer inspections. The DF channel information (oblique (LPDs) versus Large Pits (LLPDs)
narrow and wide, normal narrow and wide) was merged into
In order to analyze the yield impact of various types of LLPD
one DF composite plus BF. When the DF composite and BF
defects, an incoming prime wafer was inspected for LLPD defects.
defects were overlaid, the common defects were revealed as
Two LLPD defects were captured on this wafer. SEM analysis
LLPD defects. SEM analysis verified 100% purity of this
automatic classification.
Darkfield Brightfield Grand composite
Once the LLPD defects were identified, it was possible to composite LLPD : DF & BF
further identify and separate the large particles, air pockets, oblique + normal common defects

polishing pits and etch defects precisely using BF (DIC) infor-

mation combined with DF channel data through RBB. LLPD
Cluster

A comparison of LLPD results using conventional 8950 DFC Defects 56 BF Defects 17 LLPD Defects
methods versus new technology with RBB
An overlay of inspection LLPD
data from seven LLPD LPD Purity
300mm wafers
Case Study 1: Twenty 300mm wafers LLPD 17 0 100%
LPD 0 8950 100%

Twenty 300mm wafers obtained from various wafer manufac- Accuracy 100% 100%

turers were inspected, and the scan results were combined to

compare the conventional method versus the new approach. Figure 8: Grand composite of DF and BF(DIC) for LLPD classification.
SEM review showed a total of 29 LLPD defects.
The conventional method identified a total of 28 LLPD True LLPD

-- 16 LLPDs were correctly identified Missed LLPD

Particles classified as LLPD
-- 12 particles were incorrectly classified as LLPDs
1ea.
-- 13 LLPD defects were missed LLPD
12ea.
The results of this case study are shown in Figure 9. 29ea. 29ea.
16ea.
The conventional method would have caused a 43% increase
in false wafer rejection at the wafer manufacturers final inspec- 13ea.
Missed
tion step due to particles being reported as LLPD defects. LLPD
Conventional New Identified LLPD
Additionally, 45% of the total LLPD population was missed, method approach by review
passing the risk to the IC manufacturers customers.
The new RBB-based approach was able to detect all 29 LLPDs; Figure 9: Current challenges with faceted LLPD in 300mm
only one particle was misclassified as an LLPD. wafer manufacturing.

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F eature S tory

Further analysis of the failure mechanism caused by the

polished pit revealed that after the CMP process, the SiO2 STI
True LLPD
(Shallow Trench Isolation) film was not completely polished
Missed LLPD
Particles classified as LLPD
and removed over the Si3N4 etch stop. Therefore the subse-
45ea. quent wet chemical Si3N4 removal process was unsuccessful
LLPD
in and around the pit, preventing formation of the working
transistor structure necessary for the memory cell.
20ea. 28ea. 28ea.

8ea. Conclusions
Missed
LLPD Conventional New Identified LLPD Although shrinking device design rules are driving sensitivity
method approach by review requirements to capture smaller critical size defects, large,
yield-impacting defects have been growing in importance.
Figure 10: Current challenges with faceted LLPD in 200mm Wafer manufacturers require a better method to capture and
wafer manufacturing. accurately classify LLPDs to prevent unnecessary false wafer
rejection or shipping of defective wafers to IC device makers
that do not meet IQC specifications. Capturing and correctly
identified them as a large particle and a polishing pit. This classifying these defects early in the wafering process has the
prime wafer was allowed to proceed through complete process- additional benefit of rapid root-cause identification that allows
ing for 80nm DRAM memory devices. Electrical test results of wafer manufacturers to quickly implement corrective measures
the die built on the LLPD defect locations revealed that both at the right process steps to ensure consistent product quality.
had yield-related issues, although at differing levels of severity.
While the large particle generated a few bad memory cells, The new wafer inspection technology has demonstrated the
the polishing pit completely destroyed the memory device, as ability to address the challenges faced by both wafer manufac-
shown in Figure 11. turers and IC device manufacturers and has provided a solution
for improving product quality, cost and productivity. The new
rules-based binning technology, combined with multi-channel
LLPD Wafering Large Particles processing, gives wafer manufacturers and IC device makers
dramatically increased effectiveness in defect capture and
accurate classification for both conventional defect types and
yield-killer LLPDs. This achieves the goal of improving wafer
quality, an important factor in overall yield, ultimately
improving the fabs financial bottom line.
8M1A
90 1A

2104K1C
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Acknowledgments
The authors would like to thank the engineering and applica-
s
tions staff at Hynix Semiconductor Wafer Engineering Group,
1A

93 1A

300mm prime wafer inspection

77

87 77

before device processing

and KLA-Tencors Surfscan division for their valuable contri-
butions to this original work and team effort.
Killer Device Yielding Die
This work also would not have been successful without the
Figure 11: DRAM device memory cell bitmap; yield impact of faceted
direction, information and strong support from wafer manufac-
LLPD vs. large particle on 80nm DRAM in IC manufacturing. turers across the globe.

References
Before CMP Device failure area
1. International Technology Roadmap for Semiconductors 2005 Edition,
After CMP Yield Enchancement, pp. 710.
2. C.G. Koh, D.J. Kim, Hynix Technical Report, A06041883, Evaluation
Result of SP2 SSIS - 200mm Wafers, UNPUBLISHED.
3. C.G. Koh, B.S. Moon, D.J. Kim, Hynix Technical Report, A06095565,
STI
Evaluation Result of SP2 SSIS - 300mm Wafers, UNPUBLISHED.
Si

Figure 12: Device failure caused by remaining oxide and the unstripped
nitride film due to patterning and CMP issues of the faceted LLPD.

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