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GPIO (Interrupt Mode) : Lea Dominique Fariola
GPIO (Interrupt Mode) : Lea Dominique Fariola
Abstract The paper details the activities done in using different priorities. These priorities can be changed by the user
STML053R8T6. It aims to create a successful simulation using from the program.
software and uploading it to the microprocessor. An external
trigger which is a pushbutton has a pin setting of GPIO_EXTI13.
II. USER LED AND USER PUSHBUTTON
The NVIC of the system was enabled to has a more precise
output. Callback function calls the external trigger pin. There is Unlike the previous paper, some of the settings of pins for
also an addition situation wherein two waveforms must be the Interrupt Mode is different wherein the settings of the pins
displayed. First waveform displays if there is no external trigger
applied and the second waveform displays if an external trigger is are GPIO_Output. PA5 is set as GPIO_Output and PC13 is set
applied. The paper came up with a conclusion that Interrupt as GPIO_EXTI13. The Clock Configuration is the same as the
Mode is very useful especially when lagging effect happens to the previous experiment as long as the resulting frequency is
system. Therefore, the interrupt mode codes must only brief but
also exact so that the time it would take to perform the 32MHz. In the Configuration tab, the settings for GPIO under
interruption would not lag. the System group was configured the same as the previous
experiment wherein the GPIO mode is Output Push Pull, the
Index Terms STML053R8T6, STM32CubeMX, interrupt
mode, nvic, GPIO Pull-up/Pull-down is No pull-up and no pull-down with
a Fast maximum output speed. For PC13, its GPIO mode is
External Interrupt Mode with Rising edge trigger detection
I. INTRODUCTION while its GPIO pull-up/pull-down is the same with PA5. PA5 is
General Purpose Input/ Output (GPIO) contains several the LED while the PC13 is the external trigger.
classifications. This paper is about GPIO in its Interrupt Mode. For the NVIC of the System Configuration, EXTI line 4 to
Interrupts are some kinds of developing signals that may 15 interrupts was enabled wherein PC13 is under it. The source
pop up to a CPU and requests that you should pause the main code was then generated and the IAR Embedded Workbench
program to execute some critical code at some other location IDE was shown.
which is the Interrupt Handler or Interrupt Service Routine, and
jumps back resuming the main program you are on previously.
This can be used in situations wherein it does not require much
execution time. The code on the interrupt handler must be as
brief as possible and must not use delay. Also, their shared
variables must be carefully managed.
The Nested Vectored Interrupt Controller (NVIC) is closely
coupled to the processor core interface. This enables low
latency interrupt processing and efficient processing of late
arriving interrupts. All of the interrupts and the core exceptions
are managed by NVIC. Each interrupt present on an STM
corresponds with a physical address which is used to indicate
the position of the interrupt handler so that it can jump Figure 1. Code Segment for Pushbutton initial state
precisely. The NVIC has the ability to handle interrupts with
The main.c file was configured to add a code segment. Fig.
1 shows the code. uint16_PushButton. This code must be
encoded under the USER CODE BEGIN PFP.
The PushButton must have an initial value of zero because Figure 4. Waveform 1
the nature of a pushbutton is an open connection and as it is
toggled it is then that a current can flow through it. It is an Fig. 4 displays the first waveform. Another set of codes is
unsigned integer where it allows to declare variables of the needed in order for the codes to be simulated.
same size as a pointer.
B. Waveform 2
Figure 5. Waveform 2
V.ACKNOWLEDGMENT
The student would like to thank the Almighty Father for the
guidance, wisdom, and knowledge He granted all throughout
the duration of the creation of this paper.
VII. REFERENCES
Figure 8. Segment code for waveform 2 [1] L. T. Phuc, "letanphuc," letanphuc.net, 20 March 2015.
[Online]. Available: http://letanphuc.net/2015/03/stm32f0-
Fig. 8 shows the segment code for the second waveform. tutorial-3-external-interrupts/ .
Based from the waveform 2 in Fig. 5, pin 1 goes in its HIGH [2] A. Community, "ARM Community," community.arm.com,
state at the first clock pulse and pin 2 on the second clock pulse 1995-2017. [Online]. Available:
https://www.community.arm.com/processors/b/documents/pos
and so on. Observe that the segment code for the waveform 1
ts/a-beginner-s-guide-on-interrupt-latency---and-interrupt-
has just opposite arrangements as the segment code for the latency-of-the-arm-cortex--m-processors.
waveform 2. [3] STMicroelectronics, "ST," www.st.com, 2016. [Online].
Available: 00105960.pdf/jcr:content/translations/en.DM00105960.pdf.
http://www.st.com/content/ccc/resource/technical/document/d
atasheet/8a/f4/9d/d7/61/1b/46/b4/DM00105960.pdf/files/DM