Course: M.Tech (Electronics & Communication Engineering)
Subject: VLSI DESIGN Paper Code: MEC-020 Semester: VI
Questions from Unit I
Q.1. Derive drain current equation(current - voltage equation) for NMOS with a neat diagram. Q.2. Explain n-well CMOS Process with necessary sketches. Q.3. Explain following terms in short. (i) Body effect. (ii) Moores law (iii) Threshold voltage. (iv) Noise Margin (v) Channel length modulation Q.4. Explain MOS system under external bias with necessary diagram. Q.5. Define VLSI design methodology (Y Chart)and MOS Scaling. Q.6. Explain the CMOS inverter switching characteristic and explain the definitions of delay and transition times. Questions from Unit II Q.1. Derive equation of TPLH and TPHL for CMOS inverter Q.2. Determine pull-up to pull-down ratio for an nMOS inverter driven by another nMOS inverter. Q.3. Draw and explain working of CMOS inverter and derive the expression for VIL, VIH, VOH,VOL for CMOS inverter. Q.4. A CMOS inverter has VTO,n = 0.8 V, VTO,p = - 0.8 V , and kn=kp. Obtain VIL,VIH, VOH,VOL , NMH and NML for VDD = 5v . Q.5. Consider a CMOS inverter, with the following device parameters, VDD= 5V, VTon =0.6V, VTop= -0.7V, nCox=60A/V2, pCox=20 A/V2, =0. Determine the(w/L) ratios of the nMOS and the pMOS transistors such that the switching threshold is Vth =2.5 V. Q.6. Measured voltage and current data for a MOSFET are given below:
Determine the type of the device and calculate the parameters Kn,VT0 and . Assume F=-0.3V.
Questions from Unit III
Q.1. Discuss and describe the basic design rules for miniaturizing VLSI circuits in brief.. Q.2. Draw the color coded stick diagrams of two input nMOS, CMOS NAND and NOR gates. Q.3. Design the circuit described the function Y=[A(B+C)(D+E)] using CMOS logic. Also find the equivalent CMOS inverter circuit if (W/L)p = 5 and (W/L)n = 2 Q.4. Implement the following function using CMOS transmission gate (i) F=AB+ A B (ii)F=AB + AC + ABC Q.5. Explain symbol, different corours and lines used for drawing stick diagram. Draw a stick diagram of CMOS inverter. Q.6. Explain the scaling down of Mos-Transistor using constant Field Scaling and its limitation. Questions from Unit IV Q.1. Briefly explain the issues involved in Built-in-Self Test(BIST) techniques. Q.2. Define the terms controllability and observability. Discuss in brief Ad-hoc testable design techniques. Q.3. What are stuck-at-zero and stuck-at-one faults? Explain briefly test and testability of vlsi circuits. Q.4. Write short note on VLSI testing. Q.5. Define stuck-at-0, stuck-at-one and bridging faults with example. Q.6. Enlist the classification of dynamic CMOS logic circuit and discuss the advantage of dynamic logic circuit over static CMOS logic circuit.
Questions from Unit V
Q.1. Draw and explain architecture of CPLD. Q.2.Write short note on FPGA. Q.3. Write the dataflow modeling for a 4:1 MUX using Verilog HDL. Q.4. Explain the different timing controls available in Verilog HDL. Q.5. Explain the different kinds of physical defect (faults) that can occur on a CMOS circuits. Q.6. Discuss the various design techniques involved in low power CMOS VLSI circuits.