This document describes a behavioral VHDL code for a full adder circuit. It defines the entity SUMACOMPLEMAYOR with inputs a, b, Cin and outputs salida, Cout. The architecture Behavioral defines components for a full adder XOR gate, AND gate, and OR gate. It maps the inputs and outputs to these components to implement the full adder logic and calculate the sum and carry out signals.
Original Description:
Programa en lenguaje VHDL, el cual representa la función de un sumador binario completo.
This document describes a behavioral VHDL code for a full adder circuit. It defines the entity SUMACOMPLEMAYOR with inputs a, b, Cin and outputs salida, Cout. The architecture Behavioral defines components for a full adder XOR gate, AND gate, and OR gate. It maps the inputs and outputs to these components to implement the full adder logic and calculate the sum and carry out signals.
This document describes a behavioral VHDL code for a full adder circuit. It defines the entity SUMACOMPLEMAYOR with inputs a, b, Cin and outputs salida, Cout. The architecture Behavioral defines components for a full adder XOR gate, AND gate, and OR gate. It maps the inputs and outputs to these components to implement the full adder logic and calculate the sum and carry out signals.
1 ---------------------------------------------------------------------------------- 2 -- Company: INSTITUTO TECNOLOGICO DE LAZARO CARDENAS 3 -- Engineer: MARIO ALBERTO ALVAREZ VAZQUEZ 4 -- Create Date: 21:03:04 10/19/2016 5 -- Design Name: SUMADOR COMPLETO 6 -- Module Name: SUMACOMPLEMAYOR - Behavioral 7 ---------------------------------------------------------------------------------- 8 library IEEE; 9 use IEEE.STD_LOGIC_1164.ALL; 10 11 -- Uncomment the following library declaration if using 12 -- arithmetic functions with Signed or Unsigned values 13 --use IEEE.NUMERIC_STD.ALL; 14 -- Uncomment the following library declaration if instantiating 15 -- any Xilinx primitives in this code. 16 --library UNISIM; 17 --use UNISIM.VComponents.all; 18 19 entity SUMACOMPLEMAYOR is 20 Port ( a : in STD_LOGIC; 21 b : in STD_LOGIC; 22 salida : out STD_LOGIC; 23 Cin : in STD_LOGIC; 24 Cout : out STD_LOGIC); 25 end SUMACOMPLEMAYOR; 26 --------------------------------------------------------------------- 27 architecture Behavioral of SUMACOMPLEMAYOR is 28 29 component SUMACOMPLEXOR 30 Port ( a : in STD_LOGIC; 31 b : in STD_LOGIC; 32 sal : out STD_LOGIC); 33 end component; 34 --------------------------------------------------------------------- 35 component SUMACOMPLEAND 36 Port ( a : in STD_LOGIC; 37 b : in STD_LOGIC; 38 sal : out STD_LOGIC); 39 end component; 40 --------------------------------------------------------------------- 41 component SUMACOMPLEOR 42 Port ( a : in STD_LOGIC; 43 b : in STD_LOGIC; 44 sal : out STD_LOGIC); 45 end component; 46 --------------------------------------------------------------------- 47 signal Q0,Q1,Q2,Q3,Q4:std_logic; 48 begin 49 50 U0:SUMACOMPLEXOR port map ( a => a, b => b, sal => Q0); 51 U1:SUMACOMPLEXOR port map ( a => Q0, b => Cin, sal => Q1); 52 U2:SUMACOMPLEAND port map ( a => Q0, b => Cin, sal => Q2); 53 U3:SUMACOMPLEAND port map ( a => a, b => b, sal => Q3); 54 U4:SUMACOMPLEOR port map ( a => Q2, b => Q3, sal => Q4); 55 salida <= Q1; 56 Cout <= Q4; 57 end Behavioral;