Dar es Salaam Institute of Technology

Computer Studies Department

Assignment
Class: B. Eng 15Co

Module: MICROPROCESSOR
Name of the Student: KEVIN ZILIMU
Admission Number: 150242432309
ASSIGNMENT 1
 1. Differences in terms of speed, data size and other qualities of improving speed of microprocessor
from 4004 to Pentium D

Processor type(Intel) Speed Data size Other qualities of improving speed

740 kHz Clock rate 4-bits 0.07 MIPS(Millions of
4004 Instruction Per Second)
Number of transistors 2,300 at
10 m
Addressable Memory 640 bytes
Program Memory 4 KB

Clock rate 2 MHz 8-bits 0.29 MIPS

8008 Bus width 8 bits data, 16 bits
address
Number of transistors 4,500,
6 m
Addressable memory 64 KB
Clock rate 2 MHz 8-bits 0.29 MIPS
8080 (very rare 8080B: Bus width 8 bits data, 16 bits
3 MHz) address
Number of transistors 4,500,
6 m
Addressable memory 64 KB

Clock rate 3 MHz 8-bits 0.37MIPS

8085 Bus width 8 bits data, 16 bits
address
Number of transistors 6,500 at
3 m

16-bits
0.33 MIPAS
8086 5 MHz 16-bits
0.66 MIPS
16-bits
0.75 MIPS
8 MHz Bus width 16 bits data, 20
bits address
10 MHz Number of transistors 29,000
at 3 m

Addressable memory
1 megabyte

Clock rates: 16-bits Internal architecture 16 bits

8088 External bus Width 8 bits
4.77 MHz with 0.33 data, 20 bits address
MIPS Number of transistors
29,000 at 3 m
 Addressable memory
8 MHz with 0.66 1 megabyte
MIPS

Clock rates 6 MHz 16-bits

80186 1 MIPS
Number of transistors
55000

Clock rates: 16-bits Bus width: 16 bits data, 24 bits

80286 address.
6 MHz with 0.9 Number of transistors
MIPS 134,000 at 1.5 m
Addressable memory 16 MB
8 MHz, 10 MHz
with 1.5 MIPS

12.5 MHz with 2.66

MIPS

16 MHz, 20 MHz
and 25 MHz
available.

iAPX 432 Clock rates: 32-bits One terabyte virtual address

space
5 MHz 43205 Memory Control Unit
(MCU)
7 MHz Architecture and execution
unit internal data base paths
8 MHz 32 bit
Two-chip General Data
Processor (GDP), consists of
43201 and 43202
80386DX Clock rates: 32-bits Bus width 32 bits data, 32 bits
address
16 MHz Number of transistors 275,000
with 5 MIPS at 1 m
Addressable memory 4 GB
20 MHz Virtual memory 64 TB
First x86 chip to handle 32-bit
with 6 to 7
data sets
 MIPS

25 MHz
with 7.5
MIPS

33 MHz with
9.9 MIPS

Clock rates: 32-bits Internal architecture 32 bits

80386SX External data bus width 16
16 MHz bits
with 2.5 External address bus width
MIPS 24 bits
Number of transistors
20 MHz 275,000 at 1 m
with 3.1 Addressable memory 16 MB
MIPS Virtual memory 32 GB

25 MHz
with 3.9
MIPS

33 MHz
with 5.1
MIPS

Clock rates: 32-bits Internal architecture 32 bits

80386SL External bus width 16 bits
20 MHz Number of transistors
with 4.21 855,000 at 1 m
MIPS Addressable memory 4 GB
Virtual memory 1 TB
25 MHz
with 5.3
MIPS,

Clock rates: 32-bits Bus width 32 bits

80486DX Number of transistors 1.2
25 MHz million at 1 m; the 50 MHz
 was at 0.8 m
with 20 Addressable memory 4 GB
MIPS Virtual memory 1 TB
Level 1 cache of 8 KB on chip
33 MHz Math coprocessor on chip
with 27
MIPS

50 MHz
with 41
MIPS

80486SX
Clock rates: 32-bits Bus width 32 bits
Number of transistors 1.185
16 MHz million at 1 m and 900,000
with 13 at 0.8 m
MIPS Addressable memory 4 GB
Virtual memory 1 TB
20 MHz
with 16.5
MIPS

25 MHz
with 20
MIPS

33 MHz
with 27
MIPS

80486DX2 Clock rates: 32-bits

40 MHz

50 MHz

66 MHz
80486SL Clock rates: 32-bits Bus width 32 bits
Number of transistors 1.4
20 MHz million at 0.8 m
with 15.4 Addressable memory 4 GB
MIPS Virtual memory 1 TB

25 MHz
with 19
MIPS

33 MHz
with 25
MIPS

Clock rates: 32-bits Number of transistors 1.6

80486DX4 million at 0.6 m
75 MHz Bus width 32 bits
with 53 Addressable memory 4 GB
MIPS Virtual memory 64 TB

100 MHz
with 70.7
MIPS

Clock rates 32-bits Number of transistors 3.1

Original 166-300 MHz million to 4.5 million
Pentium System bus clock rate 60 or
66 MHz
Address bus 32 bits
Addressable Memory 4 GB
Virtual Memory 1 TB
Clock rates 32-bits Number of transistors 5.5
Pentium Pro 150 MHz-200 MHz million
512 KB or 256 KB
integrated L2 cache
60 or 66 MHz system bus
clock rate
Clock rates 32-bits Number of transistors 7.5
Pentium II 233 MHz -450 MHz million
32 KB L1 cache
512 KB 12 bandwidth
 external L2 cache
Clock rates 32-bits 133 MHz system bus clock rate
Celeron 533 MHz- 1.4 GHz Number of transistors: from 9.5
million to 28.1 million

Clock rates 32-bits 2 MB L2 cache

Pentium M 900MHz 2.26 GHz million transistors from 77
-140 million

Clock rates 32-bits 64 KB L1 cache

Celeron M 1 MB L2 cache (integrated)
310 2.00 GHz

Clock rates 32-bits 2 MB (Shared on Duo) L2

Intel Core cache
Intel Core Duo T2700
2.33 GHz

Intel Core Duo T2600

2.16 GHz

Intel Core Duo T2500

2 GHz

Intel Core Duo T2450

2 GHz

Intel Core Duo T2400

1.83 GHz

Intel Core Duo T2300

1.66 GHz

Intel Core Duo T2050

1.6 GHz

Intel Core Duo

T2300e 1.66 GHz

Intel Core Duo T2080

1.73 GHz

Intel Core Duo L2500

 1.83 GHz

Intel Core Duo L2400

1.66 GHz

Intel Core Duo L2300

1.5 GHz

Intel Core Duo U2500

1.2 GHz

Intel Core Solo T1350

1.86 GHz

Intel Core Solo T1300

1.66 GHz

Intel Core Solo T1200

1.5 GH

Clock rates 32-bits System Bus clock rate

Pentium 4 1.4 GHz-3.4 GHz 400 MHz

800 MHz system bus

6500 to 10,000 MIPS

ItaniumXeon Clock rates 1.4, 1.5, 32-bits System Bus clock rate
1.7 GHz 400 MHz
Mobile Pentium Clock rates 32-bits
55 million transistors
4-M 1.4 GHz-2.6 GHz
cache L2 512 KB
BUS a 400 MHz
Pentium 4E Clock rates 32-bits Number of transistors 125
533 MHz and million on 1 MB Models
800 MHz system Number of transistors 169
bus million on 2 MB Models
7500 to 11,000 MIPS
Clock rate 733 MHz 64-bits 2MB cache
Itanium and 800 MHz
 Clock rate 64-bits McKinley 900 MHz 1.5 MB
Itanium 2 900 MHz 1.6 GHz cache, Model 0x0
McKinley 1 GHz, 3 MB
cache, Model 0x0
Deerfield 1 GHz, 1.5 MB
cache, Model 0x1
Madison 1.3 GHz, 3 MB
cache, Model 0x1
Madison 1.4 GHz, 4 MB
cache, Model 0x1
Madison 1.5 GHz, 6 MB
cache, Model 0x1
Madison 1.67 GHz, 9 MB
cache, Model 0x1
Hondo 1.4 GHz, 4 MB
cache, dual-core MCM,
Model 0x1
Clock rate
Pentium 4F 2.83.8 GHz 2 MB cache

Intel 64-bit

Clock rate 2.66 GHz 64-bit Dual-core microprocessor

Pentium D

Note: MIPS Millions of Instruction per second

 2. Program for dividing in 8085 microprocessor
LABLE MNEMONIC ADDRESS CONTENTS
START MVI A,78H 0400 3E
0401 78
MVI B,04H 0402 06
0403 04
MVI C,00H 0404 0E
0405 00
NEXT CMP B 0406 B8
JMP END 0407 FA
0408 0F
0409 04
SUB B 040A 90
INR C 040B 0C
JMP NEXT 040C C3
040D 06
040E 04
END STA 0803 040F 32
0410 03
0411 08
MOV A,C 0412 79
STA 0802 0413 32
0414 02
0415 08
HLT 0416 76