EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN

ASSIGNMENT #1

UNIVERSITI MALAYSIA PERLIS

SCHOOL OF MICROELECTRONIC ENGINEERING

EMT 353/3
DIGITAL INTEGRATED CIRCUIT DESIGN

ASSIGNMENT #1

SEMESTER 1
ACADEMIC SESSION 2016/2017

GROUP MEMBERS

NAME MATRIC NO. COURSE TASK

RK 05
BEH YONG JIAN 141010413 Technology view
Microelectronic Engineering
RK 05
CHIA SHAN BOON 141010415 Schematic Design
Microelectronic Engineering
RK 05
LAU TENG HUI 141010425 HDL Design
Microelectronic Engineering
RK 05
ONG CHEE CHUNG 141010475 RTL view
Microelectronic Engineering
 EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
ASSIGNMENT #1

ASSIGNMENT #1 (10%)
DUE DATE: 11 NOVEMBER 2016 (W9)

TASK#1: Schematic versus HDL-based design (Verilog HDL)

Figure 1: A 4bit 4-1 multiplexer

Figure 1 shows a 4-to-1 multiplexer with 4-bit input each and 4-bit output. Represent the multiplexer
using:-

(i) Schematic design entry technique with gate level representation.

(a) Gate Level Representation

Figure 1.1: Gate Level

 EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
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Figure 1.2: Symbol Level

Figure 1.3: Waveform

 EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
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(ii) HDL-based design technique

a. if-else:
a1. Complete if-else:

module mux4_ifelse
(
input [3:0]A,B,C,D, //4-bit input A,B,C,D
input [1:0]Sel, //2-bit input Sel
output reg [3:0]Y //4-bit output
);
always @ (A or B or C or D or Sel) //cyclic behavioural model
begin
if (Sel==2'b00) //Sel=00,Y=inputA
Y = A;

else if (Sel==2'b01) //Sel=01,Y=inputB

Y = B;

else if (Sel==2'b10) //Sel=10,Y=inputC

Y = C;

else //Sel=11,Y=inputD
Y = D;
end
endmodule

Figure 1.4: Complete if-else source code

a2. Incomplete if-else:

Condition 1: If without Else but specified all possible conditions

module mux4_ifelse
(
input [3:0]A,B,C,D, //4-bit input A,B,C,D
input [1:0]Sel, //2-bit input Sel
output reg [3:0]Y //4-bit output
);
always @ (A or B or C or D or Sel) //cyclic behavioural model
begin
if (Sel==2'b00) //Sel=00,Y=inputA
Y = A;

else if (Sel==2'b01) //Sel=01,Y=inputB

Y = B;

else if (Sel==2'b10) //Sel=10,Y=inputC

Y = C;

else if (Sel==2'b11) //Sel=11,Y=inputD

Y = D;
end
endmodule

Figure 1.5: Incomplete if-else source code (Condition 1)

 EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
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Condition 2: If without Else but only certain conditions are specified

] module mux4_ifelse
(
input [3:0]A,B,C,D, //4-bit input A,B,C,D
input [1:0]Sel, //2-bit input Sel
output reg [3:0]Y //4-bit output
);
always @ (A or B or C or D or Sel) //cyclic behavioural model
begin
if (Sel==2'b00) //Sel=00,Y=inputA
Y = A;

else if (Sel==2'b01) //Sel=01,Y=inputB

Y = B;

else if (Sel==2'b10) //Sel=10,Y=inputC

Y = C;
Figure 1.6: Incomplete if-else source code (Condition 2)
end
endmodule
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b. case statement:
b1.Complete case:

module mux4_case
(
input [3:0]A,B,C,D, //4-bit input A,B,C,D
input [1:0]Sel, //2-bit input Sel
output reg [3:0]Y //4-bit output
);

always @ (A or B or C or D or Sel) //cyclic behavioural model

begin
case (Sel)
0: Y = A; //Sel=00,Y=inputA
1: Y = B; //Sel=01,Y=inputB
2: Y = C; //Sel=10,Y=inputC
3: Y = D; //Sel=11,Y=inputD
default: Y = 1'bX; //'default' to prevent latches
endcase
end
endmodule

Figure 1.7: Complete case source code

b2. Incomplete case:

module mux4_case
(
input [3:0]A,B,C,D, //4-bit input A,B,C,D
input [1:0]Sel, //2-bit input Sel
output reg [3:0]Y //4-bit output
);

always @ (A or B or C or D or Sel) //cyclic behavioural model

begin
case (Sel)
0: Y = A; //Sel=00,Y=inputA
1: Y = B; //Sel=01,Y=inputB
2: Y = C; //Sel=10,Y=inputC
endcase
end
endmodule

Figure 1.8: Incomplete case source code

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c. Demonstrate the effect of complete and incomplete case (a) and case (b) respectively.
Case(a) if-else:
a1. Complete if-else:

Figure 1.9: Complete if-else Register Transfer Level (RTL)

a2. Incomplete if-else:

Condition 1: If without Else but specified all possible conditions

Figure 1.10: Incomplete if-else Register Transfer Level (RTL) (Condition 1)

 EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
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Condition 2: If without Else but only certain conditions are specified

Figure 1.11: Incomplete if-else Register Transfer Level (RTL) (Condition 2)

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Case(b) case:
b1. Complete case:

Figure 1.12: Complete case Register Transfer Level (RTL)

b2. Incomplete case:

Figure 1.13: Incomplete case Register Transfer Level (RTL)

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Differences between If-else statement and Case statement

If else Statement Case Statement
Different options that can be chosen by a set of
Sequential statements.
select signals.

Multiple conditions. Function similar to multiplexer

Creates priority-encoded logic Creates balanced logic.

Use for speed critical paths Use for complex decoding

Evaluated againsr a common controlling

Contain a set of different expression
expression

Differentiate between Incomplete

Incomplete If else Statement Incomplete Case Statement
Synthesis tool assumes that previous value of a
Incomplete declaration for input combinations
variable is maintained.
will result latch.
(LATCH INFERENCE)
This is undesirable since it would create This undesirable since it would create
unnecessary logic usage. unnecessary logic usage.
(REDUNDANT LATCH) (REDUNDANT LATCH)

1 is interpreted as true.
Remain previous value hence latch is inferred.
0, x, z are interpreted as false.

(iii) Differentiate between the schematic and HDL-based design technique and relate to abstraction
levels in digital design.
Schematic
Schematic gives far more insight into
what's happening at a gate-level design
and gate level implementation.
easier to optimize the design for the
specific device.
Flexible in design.
A schematic capture tool allows the user to
draw a schematic diagram of a circuit in
which circuit elements, such as logic
gates, are depicted as graphical symbols
and connections between circuit elements
are drawn as lines.
Tools provided a library which is a
collection of graphical symbols that
represents gates of various types.
It allows hierarchical design to create a
circuit that includes within it other smaller
circuits.
Very difficult to modify the design.
Harder to port it to a different device,
unlike the HDL is multiple compatible.
A lot of debugging is needed because it
does not isolate from implementation-
level errors.
The verification and simulation
capabilities are more limited.
Reference
1. Ciletti M. D., Verilog 2001 for Beginners, Prentice Hall, 2008.
2. Lab 0 Introduction To Quartus II and Modelsim: From Design to Hardware Prototyping.
EMT 353/3 DIGITAL INTEGRATED CIRCUIT DESIGN
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HDL
HDL good perform in complex but well-
defined designs.
HDLs represent extensive parallel
operations.
Do not need to redesign circuit when new
technology emerges.
Tools for HDL have extraordinary
sophistication, with plenty of verification
and simulation.
Logic synthesis tool will optimize the
circuit in area and timing for the new
technology.
functional verification of the design can be
done early in the design cycle.
Designing with HDLs is analogous to
computer programming.
A textual description with comments is an
easier way to develop and debug circuits
compared to schematics.
HDL aren't the best to tweak the last inch
of performance or utilization from FPGA.