Comparative Analysis of Static and Dynamic CMOS Logic Design

Rajneesh Sharma1 and Shekhar Verma2

1
Asst. Prof., 2Lecturer,
Electronics Engineering Department, Domain Robotics, Lovely Professional University, Jalandhar (PB) India

Abstract
The choice of the CMOS logic to be used for implementation
of a given specification is usually dependent on the
optimization and the performance constraints that the finished
chip is required to meet. This paper presents a comparative
study of CMOS static and dynamic logic. Effect of voltage
variation on power and delay of static and dynamic CMOS
logic styles studied. The performance of static logic is better
than dynamic logic for designing basic logic gates like NAND
and NOR. But the dynamic casecode voltage switch logic
(CVSL) achieves better performance. 75% lesser power delay
product is achieved than that of static CVSL. However, it
observed that dynamic logic performance is better for higher
fan in and complex logic circuits.
P D P = Pa vg a vg
avg Average delay
In this paper, static and dynamic 2 input NAND, NOR
and dynamic cascode voltage switch logic (DCVSL) NAND
are implemented with voltage ranging from 1V to 1.8V.
ELDO simulation results for 180nm technology nodes are
given.
This paper is organized as follows. Section II presents the
operating principles Static and Dynamic logics. Section III
compares the performance measures. Section IV discusses the
results and section V concludes this paper.

Index Terms: Static CMOS circuits, Dynamic CMOS Static and Dynamic Logic
circuits, Logic synthesis, Power delay product. Static logic
Static logic circuits allow versatile implementation [3] of logic
functions based on static, or steady-state, behavior of simple
Introduction CMOS structures. A typical static logic gate generates its
It is well known that, for theoretical reasons, dynamic logic is output levels as long as the power supply is provided. This
less low-power consuming and have high speed than static approach, however, may require a large number of transistors
logic. In particular, dynamic CMOS gates are supposed to be to implement a function, and may have cause considerable
more advantageous than static ones mainly because of a total time delay. A basic function of static CMOS logic is explained
absence of output glitching and a reduced parasitic with example of 2- input NAND gate [3]. There is conducting
capacitance. However, the need of precharging operations path between the output node and the ground only if input
introduces some extra dissipated power that does not affect voltage VA and VB are equal to logic high value. If one of the
static CMOS logic. In this project we observe experimentally inputs at low logic value then there is a path between voltage
how the choice of the CMOS technology influences the supply and output node is created i.e. except during switching,
behavior, in terms of power consumption and delay, of digital output connected to either VDD or GND via a low resistance
circuit. An appropriate choice of logic can lead to design high path.
performance, low power VLSI design.
A comparative study of CMOS static and dynamic logic
[1-2] present power consumption which show that the power
values for dynamic logic are lower than those for static logic.
However the performance comparison on the basis of power
delay product is not present so far. Power delay product (PDP)
is a fundamental parameter which is often used for measuring
the quality and the performance of CMOS logic. As a physical
quantity, the power-delay-product can be interpreted as the
average energy required for a gate to switch its output voltage
from low to high and from high to low. The amount of energy
required to switch the output has been calculated as the
product of power and delay. It is mainly dissipated as heat
when the NMOS and PMOS transistor conduct current during
switching. It is desirable to minimize the power delay product
(PDP) [3]. Figure 1. NAND logic using Static CMOS

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Basic features of Static CMOS logic are [3]
Very low static power dissipation
High noise margins (full rail to rail swing)
Low output impedance, high input impedance
No steady state path between VDD and GND
Delay is function of load capacitance and transistor
resistance
Comparable rise and fall times (under the appropriate
transistor sizing conditions)
Dynamic logic
In high density, high performance digital implementations
where reduction of circuit delay and silicon area is a major
objective, dynamic logic circuits offer several significant
advantages over static logic circuits. Fig. 2, shows a
generalized CMOS dynamic logic circuit [3]. The operation of
all dynamic logic gates depend upon on temporary storage of
increasing and the delay decreased. Delay is inversely
proportional to supply voltage and thereby it increases
whereas power directly proportional therefore it decreases.
The optimum power delay product for static NOR and NAND
is 1.93610-21 and 3.07410-22 respectively as seen (as shown
in results) is very less as compare to dynamic NOR and
NAND. However Dynamic CVSL results in 6.12910-21
power delay product whereas PDP value of static DCVSL
result 20.1410-21, so dynamic CVSL perform 75% better than
static. In the process technology utilized for this analysis, the
attractive point for static logic circuit operation lies near 1.4V
and for dynamic logic lies near 1V. Therefore it is concluded
that dynamic logic can operate at much lower values of supply
voltage.
60

PowerDelayProduct(x1021 Ws)
charge in parasitic [6]. This operational property necessitates
periodic updating of internal node voltage levels, since stored 50
charge in capacitor cannot retain indefinitely. Consequently,
40
dynamic logic circuits require periodic clock signals in order
to control charge refreshing. In the following, a dynamic 30 StaticNOR
CMOS circuit technique which allows us to significantly
reduce the number of transistors used to implement any logic 20 DominoNOR
function is introduced. The circuit based on first precharging
the output node capacitance and subsequently, evaluating the 10
output level according to the applied inputs. The precharge 0
phase is setting the circuit at a predefined initial state while the
actual logic response is determined during the evaluation 1 1.2 1.4 1.6 1.8
phase [7]. Static CMOS offers good performance but cannot SupplyVoltageVDD (V)
keep up with dynamic logic styles in terms of propagation
delay [8]. The shorter delays mostly have to be traded off for
increased power dissipation. Fig. 3. Variation of PDP with supply voltage

VDD
CLK
Table 1. Static 2 Input NOR
OUT
X VDD (V) Power ( pW) Average PDP
N-Logic Delay (pS) (x10-21 Ws)
Block 1 14.237 193.035 2.748
1.2 20.260 99.362 2.013
1.4 27.773 69.721 1.936
1.6 37.024 78.766 2.916
1.8 48.299 84.957 4.103
GND

Fig. 2. Generalized Dynamic Logic circuit. Table 2. Dynamic 2 Input NOR

VDD (V) Power ( pW) Average Delay PDP

Results and Discussion (pS) (x10-21 Ws)
The performance analysis of static and dynamic CMOS 1 24.318 858.54 20.848
circuits is carried out. ELDO simulation results for 180nm 1.2 34.446 747.5 25.748
technology nodes are given. The effect of voltage variation on 1.4 46.990 689.7 32.409
power dissipation and delay is studied .The result of static and
1.6 62.342 655.75 40.88
dynamic 2 input NAND, NOR and dynamic cascode voltage
1.8 80.929 634.65 51.361
switch logic (DCVSL) NAND are given with voltage ranging
from 1V to 1.8V. It is observed from simulation result that
with increased voltage, power dissipation of the circuits

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 Comparative Analysis of Static and Dynamic CMOS Logic Design

1404 Table 5. Static 2 input DCVSL NAND

StaticNAND
1204 DynamicNAND VDD(V) Power (pW) Average Delay (nS) PDP(x10-21Ws)
1004 1 20.0715 0.295 5.924
804 1.2 27.9937 1.115 31.212
1.4 37.655 0.652 24.536
PDP

604 1.6 49.3151 0.408 20.135

404 1.8 62.9988 0.360 22.707

204
4 Table 5. Dynamic 2 Input DCVSL NAND
1 1.2 1.4 1.6 1.8
VDD(V) Power (pW) Average Delay (pS) PDP (x10-21Ws)
SupplyVoltageVDD (V)
1 21.439 290.32 6.224
1.2 30.336 203.05 6.159
Fig. 4. Variation of PDP with supply voltage 1.4 41.368 148.179 6.129
1.6 54.859 119.04 6.302
1.8 71.19 108.08 7.694
Table 3. Power Delay Product (PDP) of Static NAND

VDD(V) Power(pW) Average Delay(pS) PDP(x10-24Ws) Conclusions and Futurework

1 2.919 173.6 506.7 In this work the impact of voltage variation on delay and
1.2 3.860 69.6 388.9 power in static and dynamic CMOS circuits has been carried
1.4 4.904 69.6 341.1 out. It has been observed from the results that the choice of
1.6 6.047 55.2 333.8 static and dynamic CMOS logic depends upon the
1.8 7.285 42.2 307.4 requirements of application. For simpler logic implementation,
e.g. NAND, NOR etc., we can use static logic because they
provide comparable performance with respect to dynamic
Table 4. Power Delay Product (PDP) of Dynamic NAND logic at low cost and less complexity, whereas dynamic logic
preferable in complex logic circuit design, e.g.
VDD(V) Power(pW) Average Delay(pS) PDP(x10-24Ws) microprocessor, microcontroller etc. The present work is very
1 2.206 313.6 691.5 useful for comparative study of analysis and simulation of
1.2 2.935 277.7 815.0 static and dynamic CMOS circuits. An appropriate choice of
1.4 3.752 249.2 934.3 logic along with voltage variation can lead to the design of
1.6 4.658 224.2 1300.1 high performance, low power VLSI chips.
1.8 5.648 42.2 1173.7 This work shall be further carried out on bigger circuits
like XOR, adder etc. so that we can analyze this comparative
study more judiciously.

35
StaticDCVLNAND
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