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321
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321
2. Make leakage current or resistance measurements to determine that exposed parts are
acceptably insulated from the supply circuit before returning the unit to the customer.
Use the following checks to perform these measurements:
A. Leakage Current Hot Check-With the unit completely reassembled, plug the AC line cord
directly into a 120V AC outlet. (Do not use an isolation transformer during this test.) Use a
leakage current tester or a metering system that complies with American National Standards
Institute (ANSI) C101.1 "Leakage Current for Appliances" and Underwriters Laboratories (UL)
6500 / IEC 60056 paragraph 9.1.1. With the unit AC switch first in the ON position and then in
OFF position, measure from a known earth ground (metal waterpipe, conduit, etc.) to all ex-
posed metal parts of the unit (antennas, handle bracket, metal cabinet, screwheads, metallic
overlays, control shafts, etc.), especially any exposed metal parts that offer an electrical return
path to the chassis. Any current measured must not exceed 0.5 milliamp. Reverse the unit
power cord plug in the outlet and repeat test. ANY MEASUREMENTS NOT WITHIN THE
LIMITS SPECIFIED HEREIN INDICATE A POTENTIAL SHOCK HAZARD THAT MUST BE
ELIMINATED BEFORE RETURNING THE UNIT TO THE CUSTOMER.
B. Insulation Resistance Test Cold Check-(1) Unplug the power supply and connect a jumper
wire between the two prongs of the plug. (2) Turn on the power switch of the unit. (3) Measure
the resistance with an ohmmeter between the jumpered AC plug and each exposed metallic
cabinet part on the unit. When testing 3 wire products, the resistance measured to the product
enclosure should be between 2 and infinite MOhms. Also, the resistance measured to exposed
input/output connectors should be between 4 and infinite MOhms. When testing 2 wire prod-
ucts, the resistance measured to exposed input/output connectors should be between 4 and
infinite MOhms. If it is not within the limits specified, there is the possibility of a shock hazard,
and the unit must be repaired and rechecked before it is returned to the customer.
PROPRIETARY INFORMATION
1. Power Supply
Note: Refer to the 321 II console schematic sheets, 270593, for the following information.
The bass module provides un-regulated power V_UNREG to console via connector J100 pins 1
and 2 [sheet 10, B2]. The power supply electronics are comprised of 4 main sections; switching
power supplies, linear power supplies, power supply synchronization, and power fail detection.
The consoles input voltage, V_UNREG, comes from the bass module and is nominally 26VDC.
This voltage varies with load and line levels, but is limited to 31.5V maximum (assuming line
voltage of 140V AC). This voltage is always present whenever the bass module is plugged into
the wall and so the consoles power supplies are likewise active. All the voltage level source are
listed in following table:
Node Name Output Type Input from Outputs to
Voltage
V_UNREG +26 Full wave Bass module +12V and +5V switching power supply
rectifier at line of
120VAC
+12V +12 Switching V_UNREG DVD drive, Tuner board, VFD display, Video control
relay.
+9V +9 Linear +12V Analog MUX, DAC output filter op-amps, Summing
op-amps and Zone speaker differential input op-
amps.
+5V +5 Switching V_UNREG +3.3V and +1.8V switching power supply; DVD
drive, Hard disk driver, IR receiver, DAC, SPDIF
receiver.
+3.3V +3.3 Linear +5V Processor CS98200s I/O power, Flash, SDRAM
ICs, Ethernet controller, SPDIF receiver,
+1.8V +1.8 Linear +3.3V Processor CS98200s core and PLL circuit power;
power on/monitor reset chip.
Note: The 1.8V and 3.3V linear regulators are derived from the +5V switching power supply.
The 9V linear regulator is derived from the +12V switching power supply.
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The +12V and +5V switching power supplies use ST L4973D3.3 regulator ICs (U17 [sheet 14,
B5] and U2 [A6]). The power supplies are designed as step-down Buck converters. The voltage
fed back to the chip on pin 13 determines the output voltage; the chips control circuitry will work
to keep this voltage at +3.3V. The +5.1V and +12V supplies use resistor divide-down networks
to obtain the +3.3V feedback voltage.
The reference designators listed below correspond to the +12V switching power supply; the
designs of the +5V regulator is nearly identical.
A number of additional series inductors and parallel capacitors exist to provide filtering func-
tions.
The compensation networks used for these switching power supplies have been chosen to
provide stability under all conditions and to provide minimal RF interference to the tuner.
The supplies function in both continuous and discontinuous mode depending on the load.
U18 [C3] is the +9V linear regulator. VR1 [A3] and VR2 [A2] are the 3.3V and 1.8V linear regula-
tor, respectively.
In order to control the noise interference to the AM tuner, a variable frequency to alternate
switching synchronization scheme was implemented. When the console is in the Tuner mode,
the SPDIF receiver (U8001 [sheet 12, B4]) delivers a 2.8224MHz clock signal (SPDIFIN_BCK)
from the 11.2896MHz crystal oscillator. SPDIFIN_BCK drives the binary count (U3 [sheet 14,
C4]) and generates a required synchronizing pulse (F_SYNCH) and feed to pin 20 of U17 [C5]
and pin 20 of U2 [B6]. Q4 [D3] and Q5 [D3] are for buffering and level shifting of the synchroniz-
ing pulse. The synchronization pulse alternation is controlled by tuner board based on the AM
station to be tuned.
It is important to detect a power failure and alert the mircoprocessor to save any relevant infor-
mation and mute the power amplifiers so that no audio pops will be heard. The power failure
detection circuit (Q2, Q3, R11, R35, R40 and R15 [sheet 14, C7]) that we employ controls an
edge-triggered interrupt to the CS98200 microprocessor (U7003, pin 146 [sheet 5, C5]) to do
just that. If the voltage on V_UNREG falls below roughly 13.2V, the microprocessor will be
alerted that there is a power failure occuring. The interrupt will be unasserted (go high) when
V_UNREG goes above roughly 16.1V. This large hytsterisis is set so that dips in V_UNREG
caused by loud volumes will not inadvertantly trip a power fail interrupt. In a brownout condition,
the system will mute with the power dip and then recover gracefully when the normal line level is
restored (V_UNREG goes above 15.39V).
2.1 Processor
The CS98200 (U7003) from Cirrus Logic is the DVD decoder IC that functions as the console's
main processor. The CS98200 is a highly-integrated processor that provides all of the audio and
video processing functions needed for the next generation of feature-rich DVD players, DVD
receivers and Internet DVD applications such as MP3, Dolby Digital, Dolby ProLogic II, and
DTS Digital Surround decoding. It supports most popular CD formats, disk control, video
decoding and up to eight channels of audio output. The CS98200 also integrates six 10-bit
video digital-to-analog converters (DACs) and TV encoding with progressive scan functionality.
Progressive scan video provides high resolution and eliminates the "flickering" effect present in
traditional video playback.
The CS98200 contains two embedded 32-bit RISC processors, one of which is used as the
main processor in the 321 Series II system. This processor controls all GPIO, sub-circuits and
interfaces, with the exception of those offloaded to the ST micro on the Tuner Board. All of the
Main Board software runs on this processor. The second embedded CS98200 processor is
responsible for overseeing ATAPI, Memory and Host interfaces, DVD ROM Drive disc playback,
Hard Disk Drive store/playback and audio/video decode and generation. Software for this
processor is provided by Cirrus. An external FLASH and SDRAM are shared between the two
RISC processors.
2.3 FLASH
U6203 [sheet 6, C3] is a 32Mbit with 16-bit bus wide Flash memory IC but only 8-bit wide data
bus is used in the system due to the limitation of CS98200. U6203 shares the memory address
with SDRAM (U6200) but the data is a dedicated one from CS98200. Flash access is asynchro-
nous and does not use a memory clock.
U6204 and U6205 [sheet 6, 4A-D] are buffers between the SDRAM and FLASH, and they have
their Output Enable pins tied to common pull-down resistors, with test points, allowing the
manufacturing plant to disable these buffers (thus releasing the FLASH address/data bus)
during programming. Half of buffer U6204 (2A/B[1..8]) is used to condition the 8 memory
control signals, and is given its own enable and direction-control signals (with independent test
points). This allows the manufacturing plant to maintain control of the SDRAM during both write
and read-back phases of In-circuit test.
2.4 ROMULATOR
J6200 [sheet 6, B/C2] is the ROMULATOR connector for the debug purposes of software
development. The console Main board provides a footprint for the required 60-pin ROMULATOR
connector but not populated in production. This connector will allow access to the FLASH
address and data busses, as per the Cirrus reference design. Pin 59 shall be tied into the
console reset circuitry, allowing it to access the CS98200 and keep the console FLASH in reset
while running off the ROMULATOR.
U6203 can be programmed not only from the ROMULATOR connector during development but
also from CD/DVD driver in the field. During re-programming in the field via CD/DVD driver, the
operating and new program are held in SDRAM. Power failures during field Flash update could
result in the console being made completely inoperable.
The CS98200's (U7003) built-in SPI interface is used to control two subsystems in the
console, the VFD (interface connector is J6500 [sheet 13, B8]) and the Tuner Assembly
(interface connector is J6000 [D8]). U6802 [A-C6] is the buffer between CS98200 and the
two subsystems. These subsystems must timeshare the SPI resource.
For the outbound data (data stream from CS98200 to subsystems), both subsystems have a
signal which uniquely identifies when the SPI data sent from the CS98200 is valid for them.
For the VFD module, the VFD_STROBE indicates it is the target. For the Tuner Assembly,
it is SPI_SEL (which becomes TNRBD_SEL once buffered). These signals are the key to
timesharing the SPI bus. Note the differing polarities associated with the signals.
For the outbound data (data stream from subsystems to CS98200), each subsystem inter-
acts with the CS98200 differently, as follows:
The VFD module allows for bi-directional communication, but timeshares a single wire in
half-duplex mode to accomplish this. To receive SPI data from the VFD, the CS98200 must
therefore use the SPI configuration option which allows receiving on the same pin used for
transmission (pin 196). See the CS98200 register spec for details.
The Tuner Assembly will use SPI in true bi-directional, full duplex mode, although the
CS9200 will be the master of all transfers. The TNRBD_DATAIN signal, which ties to the
CS98200's SPI receiver, is used for receiving. Again, see the CS98200 register spec for
SPI configuration details.
The console VFD module interface with the Main board is by a flexible cable via connector
J6500 [sheet 13, B8] which has 5-pin as listed in following table:
Note: (1) There is a buffer, U6802 with open collector between VFD and the CS98200. The
buffer is required to level-shift the 3.3V logic levels associated with the SPI interface to the 5V
logic levels required by the VFD module.
(2) The VFD module has built-in 1.5K Ohm pull-up resistors on the Clock, Data and Strobe
signals. There are no such pull-ups on the console Main Board; therefore, these signals will not
be measurable at connector J6500 unless the VFD is attached.
The console has 6 buttons on the top leading edge. The buttons are physically located on a
small assembly which connects to the Main Board via ribbon cable into J6700 [sheet 8, D8].
Software continually monitors these buttons to detect and de-bounce a key press. Pull-down
resistors are provided to hold KEY inputs to logical 0 (ground) when no buttons are pressed.
Interconnections to the buttons are in the form of a 2x3 row/column matrix of key closures.
Each button is therefore identified by its unique row/column position.
The arrangement of buttons on the front of the console is as follows. Each circular button
represents a key closure which shorts a given KEYOUT row signal to a given KEYIN column
signal when a button is pressed. For example, ON/OFF shorts the KEYOUT0 signal to KEYIN0
when pressed:
ON/OFF SOUR
+ ENTER EJECT
VOLUME
KEYIN0 KEYIN1
The console is capable of being controlled by the universal IR remote controls (basic and
premium) developed specifically for the 321 Series II, as well as 3rd party remote controls
which either include the 321 II codes or can learn them (such as a Crestron universal re-
mote). A narrow-band IR receiver module is provided on a printed circuit sub-assembly to
permit mounting in the front of the console. This module amplifies the incoming IR data stream
and removes its 37.9 kHz AM sub-carrier. The CS98200 handles the decoding of inbound
control commands from IR receiver module. Hardware assistance/noise filtering is provided in
the chip for this.
3.3 Ethernet
The 321 Series II premium console includes an Ethernet connector J9640 [sheet 9, B/C2] and
a Cirrus CS8900A 10baseT Ethernet Controller IC U9641 [sheet 9, B/C6] which interfaces to the
CS98200 via the parallel Host bus. Since this bus is timeshared with the ATAPI drives, RISC0 is
expected to handle all interactions with the chip, providing essentially a transmit and receive
FIFO for RISC1 to use for sending/receiving Ethernet packets, as well as a software API for
high-level control of the chip (power up/down, etc.).
The LINK LED, LAN LED and isolation transformer are included inside the Ethernet connector,
J9640, visible from the back of the console. The green LED (D9640) is connected directly to
the LINK LED output of the CS8900A Ethernet Controller IC (U9641) via R9656. The yellow
LED is directly connected to the LAN LED output via R9657.
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There are total of 7 analog input sources: 6 external analog inputs and one internal analog
input. Those 6 external analog inputs are: 1 tuner from Tuner board via J6000 [sheet 13, D8],
3 external (AUX, CAB/SAT and TV) from connector J201 [sheet 10, B-D8], 2 network speaker
(Zone1 and Zone2) from J202 [sheet 11, C3] via differential input buffer U8406 [B/C1]. The
internal analog input is from the mix-down DAC U9200 [C8] which convert I2S audio stream
from the CS98200 to an analog signal which is one of the two inputs to the summing circuit
U9100 [C5].
The 6 external analog sources are selected by the TEA6422 (U4000 [sheet 10, B5]) analog
audio MUX. The MUX is controlled via the CS98200's I2C bus. The MUX has the ability to
direct any one of the 6 input sources to any one of the 3 output.
Only the 3rd output of the TEA6422 (U4000) analog audio MUX is used (the 1st and 2nd output
channels are unused) and the 3rd output of the TEA6422 is summed into the NJM4556 buffer
amplifiers (U9100 [sheet 11, C5]). The mix-down DAC outputs are also summed into these
buffer amplifiers. When one of the 6 external analog audio sources is selected as the console
analog output, the 3rd output of the TEA6422 is active and the output of the mix-down DAC is
placed into reset through the reset bit in the I2C registers in order to reduce the noise level to
minimum. In a similar way, when the CS98200-generated down-mix is selected as the console
analog output, the 3rd output of the TEA6422 is muted and the output of the mix-down DAC
takes active.
The analog output goes to the bass module via the connector J100 [sheet 10, B2]. The
TEA6422 analog input MUX supports 2Vrms signal levels. The maximum amplitude of the
differential outputs of the AK4382 DAC is approximately 2Vrms. External analog input signals
may be up to 2Vrms without experiencing distortion or clipping-- absolute maximum allowable
input levels are about 3dB higher.
There are total of 6 digital input sources: 4 external digital inputs and 2 internal digital input.
Those 4 external digital inputs are: AUX, CABSAT and TV from connector J201 [sheet 12, C8]
and optical signal from J8000 [B8]. The 2 internal digital input sources are from the DVD ROM
driver via connector J3200 [sheet 7, B/C5] and hard disk driver (HDD installed on premium
product only) via connector J9341 [B/C4].
The 4 external digital sources are directed to the AK4112 U8001 [sheet 12, B/C5] SPDIF re-
ceiver. The SPDIF receiver is controlled via the CS98200's I2C bus. The 2 internal digital input
sources (both DVD ROM driver and HDD) feed the audio data streams to CS98200 via the
ATAPI bus for decoding and processing.
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The AK4112 (U8001) SPDIF receiver has two output options for all the 4 external digital input
sources: (1) bypass one of the 4 external SPDIF input steams to the digital MUX U8002, and
(2) recover the SPDIF input stream, convert to I2S and feed to CS98200. Those two output
options can be selected independently. The audio streams from both DVD ROM driver and HDD
are decoded and processed by CS98200 and then output to the digital MUX U8002 [sheet 12,
C3]. The digital MUX U8002 selects one of its two inputs and feeds the output to the bass
module via isolation pulse transformer T8600 [sheet 12, C1] and connector J100 [sheet 10, B2].
The 321 Series II console provides a digital output stream for the Smart Speaker compatible
speaker system. This output is capable of sending up to 192 kHz S/PDIF streams when driven
by the CS98200. The outbound S/PDIF signal is roughly 2 Vpp, allowing diode-termination
techniques in the Smart Speaker. When external analog sources (or the AM/FM tuner) are
played, the required data is not available on the digital audio output. When CD/DVD discs are
played, the frame rate will be generated by the CS98200 to be compatible with the disc. When
external digital inputs are played, the AK4112B receiver will phase-lock to the inbound SPDIF
stream, derive bit/frame clocks from it, and provide these clocks to the CS98200 for use in
clocking the S/PDIF output stream.
The CS98200 has some ways to decide which input type should be played for each source.
When playing the external inputs, the external digital inputs have preference, and shall be
played whenever an input stream is found to be present. If none is available, the associated
analog inputs shall be selected, thought the digital inputs shall continue to be monitored for
streams that might appear later. Digital signals are routed through the CS98200, which exam-
ines them for available data in any of the supported formats (PCM, MP3, AC3, MPEG2 or DTS).
As for the selection between optical and electrical digital input, the console external optical input
is assigned through the on-screen display (OSD) to a particular input source. To allow this, the
hardware has provided the optical signal a unique input into the AK4112B S/PDIF MUX/receiver.
When playing the source assigned to the optical input, the software should first check for the
presence of an optical input signal-if none is present, the coax digital input (S/PDIF) should be
examined. If, again, no signal is present, the external analog inputs should be played. The
external analog inputs may be played while detection of a valid digital stream is in process.
5. Video Path
The video DACs inside CS98200 may be configured for either S-video and CVBS outputs or
Component Video (YPrPb or RGB) output. The component output can be configured either
interlaced or progressive scan (the console's video low-pass filters have been designed to
support both standard and progressive-scan video outputs). A separate set of Component Video
output jacks is provided. The Y jack includes a switch normally closed to ground that is
opened when a cable is inserted into the jack. The resulting signal COMP_SENSE is moni-
tored by the CS98200.
13
The Component Video (YPrPb) output should be selected whenever the COMP_SENSE signal
is high. Also, when Component Video is selected, the VIDEO_SEL line shall remain low at all
times. This prevents attenuation of the video signal if both sets of outputs (Composite, S-Video
and YPrPb) are connected to other equipment.
6. Tuner Electronics
The tuner function is implemented on a dedicated PCB which has no other essential functions
or hardware. This has the advantage of the console working without needing the tuner board in
circuit. The topology of the tuner circuit itself is very similar to the 321 Series I tuner. There are
three variations of the final assembly. See SD270575 for details.
Note: Refer to the Tuner PCB schematic sheets, 270575, for the following information.
Interfacing the Tuner PCB to the Main is accomplished through a 13 connection flat-flex cable to
connector J1 [sheet 2, C8]. Below is a table describing the pin functionality
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Detailed control of the tuner is implemented by the ST72324 (U7001 [sheet 3, C6]) micropro-
cessor upon instructions from the CS98200 SPI bus on the main board. U7001 is responsible
for:
Handling all control commands from the main board.
Communicating with the PLL IC (U2074 [sheet 2, C/D3]) via the CCB bus to set its various
I/O pins as well as setting the desired local oscillator frequency.
Querying the RDS chip (U2200 [sheet 2, D6]), if present, for relevant messages.
Processing the seek algorithms based on S-Meter and audio levels, as well as IF-count.
Storing the seek/stop and stereo levels during tuner alignment for use in the field.
The general purpose input and output ports on the PLL IC (U2074) are set up as follows:
15
The FM RF signal from the antenna is input via the F or PAL-type input connector J2001 [sheet
1, B8] and goes to the FM front-end module. The antenna supplied with the console is the
standard quarter-wavelength dipole antenna.
The FM front-end [sheet 1, B/C8] contains a tuned RF amplifier, FM local oscillator and a mixer.
The 10.7 MHz IF output signal (pin 7 of the module) passes through a 10.7 MHz ceramic filter,
CF2000 [C7], an FM IF amplifier Q2001 [C6] and then through a second ceramic filter, CF2001
[C6]. Transistor Q2001 and related circuitry form the FM IF amplifier produces about 15 dB of
voltage gain and provides the proper impedance matching for the ceramic filters. These FM IF
filter stages reject unwanted FM stations and noise.
The software that controls the FM tuner has provisions for an IF offset to optimize tuner perfor-
mance for a given range of IF filters. The possible values of IF offset are -25kHz, 0, and
+25kHz, with the available offsets determined by twice the reference frequency (2 x 12.5kHz).
The software measures (counts) the IF frequency, and this offset is added to the count. In
tuner alignment, the value that minimizes THD at 98.1 MHz for an un-modulated signal is
chosen and stored before other stop levels are set.
The output signal from CF2001 is fed to the LA1837 AM/FM detector IC, U2000 [C4] at pin1.
This device contains the FM IF limiter, FM detector, FM stereo MPX decoder, and the S-meter
circuitry used for seek processing. The FM IF input signal to the LA1837 goes through several
gain/limiter stages and then to a single-tuned, coil-based discriminator circuit. The discriminator
coil, T2001 [C5], is adjusted for minimum second harmonic audio distortion. The recovered FM
composite signal appears on pin 23 of U2000.
The composite audio signal is filtered by C2018 [C2] and fed back into pin 22 of U2000. The
value of C2018 is chosen to optimize FM stereo separation. The stereo MPX decoding is also
performed by U2000 and the decoded left and right signals are output on pins 20 and 21. The
pilot PLL VCO is completely internal to the LA1837 detector IC, not requiring an external 456
kHz ceramic resonator as in older designs. The pilot PLL loop filter is formed by C2014, R2016,
and C2016 on pin 14.
FM de-emphasis for the left audio channel is set by C2026, R2022 and the output impedance of
pin 21 of U2000 (3.3k). FM de-emphasis for the right audio channel is set by C2027, R2023 and
the output impedance of pin 20 of U2000 (3.3k). For a US unit the capacitor values are set to
produce 75S de-emphasis, and for Europe/Japan they are set to produce 50S de-emphasis.
The resultant de-emphasized and amplified audio signal appears on pins 16 and 17. Signals
above the audio band, including the 38 kHz sub-channel demodulation components are cut off
at the bass module by the input filters in A/D converters and the audio DSP is used to create a
notch filter at 19 kHz to reject the 19 kHz pilot tone, thus removing the need for external MPX
filters.
16
The FM and AM S-meter signals, pin 11 and 12 of the LA1837 respectively, are analog voltage
levels that indicate the FM IF and AM RF input signal levels. These signals are connected to the
A/D inputs of the ST72324. During factory tuner alignment the appropriate test signal levels are
injected into the UUT and the resultant ADC values for FM stop level, FM mono/stereo level and
AM stop level are stored in the EEPROM U7000 [sheet 3, D3].
The stop level is the voltage level above which the signal strength is deemed strong enough to
warrant stopping on a channel during seek. This does not mean that the unit will always stop on
a station if the S-meter level is high enough since an IF count is also performed during to en-
sure that the correct IF frequency has been obtained.
The stereo level is the level above which a channel that has been automatically forced into
mono will return to being decoded as stereo (if stereo material is present).
When first tuning to a station the unit defaults into mono for one half second to prevent a mono
station from coming through as noisy stereo. If the initial S-meter read is greater than the
stereo level the unit switches into stereo. After the initial S-meter read the unit switches be-
tween stereo and mono in the following way. Every 500ms the S-meter is read and the unit
switches from stereo to mono if it reads one S-meter level below the force-mono level. The unit
switches from mono to stereo after ten consecutive readings of S-meter level above the stereo
level. The reasoning for using one sample to force-mono but ten consecutive samples for
stereo is to ensure that a unit with S-meter reading levels close to the threshold do not switch
between noisy stereo and clear mono too often. The set voltage between the force-mono and
stereo thresholds also helps to prevent unnecessary switching between mono and stereo,
mainly due to modulation noise on the S-meter capacitor.
Note: Switching stereo on via the On Screen Display will enable the above automatic force-
mono function while switching it off disables this automatic function and ALWAYS forces the
unit into monaural decoding. Also note that the stereo icon on the front display and the stereo
status flag on the OSD indicate the state of the ST-LED line, which indicates detection of the
19 kHz pilot tone present in stereo broadcasts. In force-mono (automatic or otherwise) this will
always be low even if the actual broadcast is in stereo.
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The signal from the external AM loop antenna enters through the 2.5 mm AM jack, J2000 [sheet
1, D8], and is fed to the AM front end module, T2000 [D6]. The antenna input is balanced by
placing C2000 [D7] between one side of the input and ground, reducing electric field interfer-
ence. The front end module contains the varactor-tuned RF and Local Oscillator (LO) tracking
circuits. This part is pre-tuned by the manufacturer for proper alignment with AM antenna
PT199824-002, and is further adjusted during factory alignment, if necessary. The RF tuned
output is fed to the AM buffer FET transistor Q2002 [D6] and the buffered output is sent to pin
27 of U2000 [C3] which contains the AM RF amplifier, mixer, IF amplifier, AM detector, and AM
S-meter circuitry. The 450 kHz AM IF output signal that appears on pin 2 is filtered by the IF
filter, T2001 [C5], and fed back into the IC on pin 4. The AM IF signal is demodulated by U2000
and the audio output is sent to pins 20 and 21, to pass through the low pass filter used in FM for
de-emphasis.
In order to avoid having harmonics of the main board switching power supplies interfere with the
AM tuner the switching frequency is controlled by F_SYNCH, a clock output from U3 [console
schematic sheet 14, C4] on the main board. The signal Supply_Freq_Sel (via lookup table
based on AM station) is used to vary the output of F_SYNCH between two frequencies that will
avoid the selected channel frequency and its image the best.
The AM seek stop processing and factory alignment is performed in a similar fashion to FM
mode processing. The nominal AM stop level is 56 dBV/m @ 1080 kHz.
The AM and FM local oscillators are controlled by the PLL IC, U2074 [sheet 2, C3]. The micro-
processor selects the AM or FM band and the particular frequency. The 7.2 MHz clock refer-
ence is generated by the microprocessor which is the stable crystal oscillator frequency divided
by 2. The 7.2 MHz oscillator is divided down to produce a 12.5 kHz reference frequency in FM
mode and a 10 kHz (9 kHz for European and Japan units) reference frequency in AM mode.
U2074 [sheet 2, C/D3] divides down the AM or FM LO input, compares it to the appropriate
reference frequency and generates an error signal that is output on pin 19.
This error signal is integrated and amplified by an active lead-lag filter formed using an internal
FET inside U2074 and associated components connected to pins 19, 20 and 21. C2096, C2097,
R2079, R2080 and R2081 control the gain and pole-zero locations of the filter. The values of
these components are chosen to ensure stability of the PLL while providing sufficient speed,
moderate overshoot, and symmetric up/down settling time. The resulting signal output at pin 21
is used as a tuning voltage and is fed back to the AM and FM front-ends.
The AM tuning voltage is further filtered by R2078 and C2095 and is fed back to the common
node of the varactors inside the AM front end, T2004. The tuning voltage varies the capaci-
tance of the varactor diodes, which in turn simultaneously tunes both the AM antenna and the
AM LO. In FM mode, the tuning voltage is filtered by R2077 [sheet 2, D1] and the input capaci-
tance of pin 5 of the FM front-end (0.047uF) [sheet 1, B/C8]. As in the AM case, the tuning
voltage is fed to varactors which tune the LO frequency and RF filtering.
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European tuners contain additional components for the decoding of Radio Data System (RDS)
information. The LC72722 Radio Data System (RDS) decoder IC, U2200 [sheet 2, D6], is a
single-chip system IC that implements the signal processing required by both the European
RDS standard and US RDBS system. RDS/RDBS systems can send digital information over
the airwaves along with the standard FM signal by adding a digitally modulated 57 kHz sub-
carrier to the normal FM composite signal. The LC72722 includes a bandpass filter, demodula-
tor, synchronization, and error correction circuits. The input (pin 2) to the RDS IC comes from
Q2003 [sheet 1, C1], which buffers the FM composite signal at pin 23 of the LA1837. The time
base for the decoder is a crystal oscillator formed by the 4.332 MHz crystal, Y2200, the inverter
internal to the IC across pins 12 and 13, and the two shunt capacitors, C2205 and C2206.
Control of the RDS IC is achieved by using the same bus interface used for the PLL IC.
The following information describes the operation of the PS321 Series II bass module.
Note: Refer to the bass module amp and DSP schematic diagrams, 270921, for the following
information.
1. Components
Control and audio input to the bass module is by means of a 13-pin interface connector and
associated bass module to console cable. This interface provides up to 15 watts (average) of
unregulated DC power for operation of the connected console. The bass module is controlled
through a single-wire serial connection which utilizes the Smart Speaker protocol on a 4800
Baud, half-duplex, bi-directional connection. Audio from the console is transported to the bass
module via stereo analog and/or S/PDIF input. The analog and digital audio inputs may be
used in conjunction to allow the transport of multi-channel audio information. A separate MUTE
line is also provided to allow the console to immediately mute the audio output. Additionally,
there is a control line which completely powers down the DSP section of the bass module to
reduce power consumption, but it is not implemented in production.
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The 13-pin interface connector is wired in a one-to-one fashion with the console connector.
The pins/signals are as follows:
2.1.3 S/PDIF
The S/PDIF input is a fully differential input which is terminated by a pair of back-to-back diodes
only. Supported sample rates are 44.1 kHz and 48 kHz.
2.1.5 DSP_SHUTDOWN
This is a positive logic control input which, when asserted logic high, shuts down the SMPS
feeding the entire DSP and signal processing path. It is not implemented (via depopulated
components) in the production design.
2.1.6 Vunreg
This is a DC supply which provides unregulated power for use by the console. Approx. 30W
peak is available from this supply. It is internally fused at 4A.
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The bass module contains all the active audio processing and amplification electronics of the
321 Series II System. The rear end cap of the bass module provides access to the following
components:
Line cord socket
Power Switch (European only)
System Connector (13-pin)
Array Speaker Connector (DB9-S)
All the above components are mounted on the I/O Printed Circuit Assembly, part number
270926-001, which is, in turn, secured to the end cap via a metal bracket. The dash suffix is
used to denote the various AC voltage variants.
All other electronics reside on the DSP/Amplifier PCB Assembly. The DSP/Amp PCB is secured
to the extruded aluminum heat sink (which is glued to the back baffle of the module enclosure)
with a metal bracket. This bracket provides sufficient compression force to the PCB to maintain
good thermal contact to the heat sink of the audio power amplifiers, rectifier diodes, and pre-
regulator FET.
The power transformer for the system is directly mounted to the end baffle of the module above
the heat sink.
The I/O printed circuit assembly contains the AC input connector J1 [C4], the line switch S1 [D3]
and line fuse F1 [C3]. Connector J2/J5 [D2], depending on the dash (-xxx) variation, provides
the primary power connection to the power transformer. A location for a MOV (VR1 [C3]) is
provided, but is not populated in production.
Connectors J6 [B7] and J7 [D8] connect the I/O PCB to the DSP PCB. J6 connects to a 16-
position ribbon cable which carries the S/PDIF and audio inputs and control signals to/from the
DSP board. J7 connects to a 10-position cable that brings the array speaker amplifier outputs
and Vunreg/GND onto the I/O PCB. C7-9 provide RF ground coupling between the various
ground pins and structures on the board. C1, C3, C4, C5, and C10 are DC blocking caps on
the differential audio inputs and associated GND. C6 is the bulk storage capacitor for the
Vunreg supply. All of the signals described in section 3.1 are connected to the 13-pin system
connector J3 [B2] on this board.
Note: Refer to the DSP/Amplifier PCB schematic diagrams, 270921, for the following informa-
tion.
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U100 [sheet 4, B5], L70 [B4], D11, and C30, C31 form a buck switching regulator for the 5 volt
supply. The nominal switching frequency is established by components R16 and C33 [B6]. A
modulating signal derived from the transformer secondary is coupled to the oscillator circuit via
C37. R18 and R19 establish the magnitude of the modulating signal. C38 filters unwanted
harmonics and line noise from the signal. Q6 [A6] allows the Inhibit pin to be pulled low from
the console, which disables the power supply, forming the DSP_SHUTDOWN function.
U101 [A3] generates the 3.3 volt supply from the 5 volt supply. C42 prevents oscillation of the
output of U502 as well as assisting to manage voltage ripple due to load fluctuations. U6000
[sheet 1, D5] monitors the 3.3V and issues a reset of the DSP if this supply ever drops below a
regulation threshold of 3.08V.
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The Clip signals of the amplifier ICs driving the array speakers (U150, U250) are summed into
the /ARRAYCLIP signal. R454 [sheet 5, D2] holds the signal false (high) if neither amplifier IC
is asserting the clip signal. A similar arrangement is used for the bass amplifier with the /
BASSCLIP signal.
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2.2.2.9 Communications
TAP Interface
The components used to access TAP directly onto the bass module DSP/Amplifier PCB are not
populated on the production versions of this board. Any testing or troubleshooting will be per-
formed using the Smart Speaker commands as listed in the test procedures in this troubleshoot-
ing guide. The following is for informational purposes only.
The TAP interface uses the serial ports (signals TAPIN and TAPOUT) on the Sharc micropro-
cessor (U7000 [sheet 1, C4]). The connection is made through J6200 [sheet 3, A8]. Q6200,
R6200 and similar convert RS-232 level input communication signals to logic level. Q6201
drives the output line to 0 and 3.3V. These parts are not used, and are shown as NV (no value)
on the schematic sheets.
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Booting - On a cold start, the supplies come up with the 3.3V supply being the last to achieve
regulation. This supply is monitored with the reset IC, MAX823 (U6000 [sheet 1, D5]) such that
when a threshold is reached, about 3.1V, the IC brings the DSP system out of RESET. When
this occurs, the DSP boots from the FLASH IC and enters the Standby mode.
Standby - After a cold start or an off signal, the DSP puts the system into a standby mode
where the system draws about 3-4 W off the primary AC. Mainly, the amplifiers are put into
standby mode (low quiescent draw), the CS8415A (U4400 [sheet 1, A7]) and CS4228 (U4000
[C2]) are reset, and the DSP enters the IDLE16 mode (NOT reset) as this is the lowest power
drain mode for the DSP. In this mode, the TAP input works as described above and the PWM
input looks for any communication via Smart Speaker. On any edge on the COMM line, the
DSP enters its quasi-power-down (quasi-standby) mode and sees if a valid command was
received, if not, then the unit enters the standby mode again. LED action shows what is going
on during this time. Also once a second, the system must come alive briefly to toggle the
watchdog timer to prevent a RESET to occur.
Also, on entering standby, the volume parameter is set to the last value, but is bounded in the
range of 20 to 80.
Oscillator - The system clock is derived from the oscillator formed by Y7000 [sheet 1, A6] and
an inverter of U6100. There is an onboard inverter on the SHARC but it was determined to not
have enough gain to reliably start-up the oscillator. R7000 was empirically determined to keep
the power dissipation in the crystal to less than .5mW. C7008, 7009 make up the loading
capacitance to set the correct frequency, 33.333MHz. The SHARC doubles this clock to
66.666MHz which sets the maximums MIPS load of the software.
Reprogramming - Software updating is accomplished via the S/PDIF input. The file is a
converted binary image into a stereo PCM format that comprises a header followed by the
image to be flashed (the length of this file is about 2 seconds). This allows the software to be
upgraded from a CD-ROM inserted into the console. When the appropriate Smart Speaker
commands are sent, the DSP reboots into ERC then looks again for an update header before
reading in the actual update image. When the image is read in, the code takes a few seconds
to determine the validity with a checksum. If the checksum fails, then no update occurs. (If
there are still updates being presented, then the process will begin again.) If the checksum
passes, the unit then writes the image to the FLASH, a process which takes about 45 seconds
and the LEDs blink very rapidly (10 Hz, see above). The update disc/file can then be stopped
during this time safely. When this has completed, the system then reboots into the new code as
if it were a cold start (into standby).
The ERC (Emergency Recovery Code) has been written to a protected area of the FLASH such
that in case a software update crashed or anything else that causes the FLASH to be corrupted,
the ERC will always be available, and therefore rewriting the FLASH is always possible using
the same update procedure.
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Bose Corporation
The Mountain
Framingham Massachusetts USA 01701
P/N: 273029-TG Rev. 00 3/2005 (H)
http://serviceops.bose.com