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VLSI Basic
it's the site made for the ASIC physical design engineer for clear the every VLSI basics of Physical design.
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Su n d a y, 3 1 J a n u a r y 2 0 1 6 Blog Archive

2017 (2)
DRC 2016 (3)

DRC is nothing but Design Rule Check. After routing, In Physical Verification steps we do January (3)
DRC clean up. It means it should follows all foundry rules/run sets to create appropriate DRC
mask. We already know that chip manufacturing process is not ideal. DRC ensure that Electrical Rules Checking (ERC)
design will still work properly even there may be lot of misalignment and various side
Layout vs Schematic Verification (LVS)
effects of fabrication process. There are multiple reason behind this. We will discuss all the
major reason behind this.
2015 (9)

Aim of physical Design cycle is to deliver GDS II to foundry such a way that it should be 2014 (31)
Timing & Physically clean. Here physically clean it means your GDS II should meet
DRC/LVS/ERC/Antenna. There are EDA tools are available in market which reads your GDS II Search This Blog
and do simulation with run sets and give your DRC errors which needs to clean.
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All foundries have their own design rules for masking. They have consistent process to
convert GDS II in to real layout/final product. As per technology and process information Popular Posts
they define some set of rules which has to follow by Physical Design Engineer while
delivered GDS II. Clock Tree
Design Rules defines shapes/size/spacing and many other complex rules of each metal Synthesis
layers. It starts from your substrate to Newell to top metal layers.
Clock Skew
All rules are define in one rule deck file, Its nothing but your drc runset file.For routing
purpose, minimum set of rules will be define your technology file. Which extension is .tf. What is "Clock
Each foundry have its own manufacturing design rules. DRC rules becoming complex as we Reconvergence
Pessimism
are going submicron technology.
Removal" (CRPR)?
DRC doesnt ensure that your device will work properly, It ensure it will get manufactured
properly. SDC (Synopsys
Once Design is DRC clean, then only correct parasitic extraction we can get. Design
Constraints)

DRC Flow Min Pulse Width

DRC clean up comes in Physical Verification steps (After routing). If you are working on
below 90nm , Metal Fill is required. So once you finish metal fill you will have corrected Die Size
DRCs errors. Below DRC flow input/output and some basic examples are given. Estimation

Cmos Latch up
INPUT
GDS II of your block/section/chip in format of .stm or .oasis CPPR (Common
Path Pessimism
Removal)
DRC runset file. Extenuation of runset file depend on which EDA tools you are
working on. Normally its in .ev or .rs Noise Margin

OUTPUT Crosstalk
Reasons
Marker based error file.
If you are using Synopsys Tools ( IC Validator ) It generates .vue file.
This files can be loaded and we can go to one by one markers and clean drcs.

Basic Examples.
1. DRC_M2: Minimum distance BW M2 should be 0.070.
Error Description: Here spacing BW metal2 is 0.046 which should be 0.070.
Solution: Stretch metal/fill by keeping spacing 0.070 BW them.
 2. DRC_M4 : Width1 to width2 spacing should be 0.040
ErrorDescripon:Heretwodierentwidthofmetal4widthtowidthspacingisnotasper
rule

EDA TOOLS
Synopsys : IC Validator or Hercules
Mentor Graphics : Caliber

Posted by Brijesh Thakkar at 17:04

+1 Recommend this on Google

 1 comment

Add a comment as abhishek singh

Top comments

Manish Sagarvanshi 7 months ago - Shared publicly

Nice Explanation.

1 Reply

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