module ebitcsa (a,b,cin,sum,co);

input [7:0]a;

input [7:0]b;

input cin;

output [7:0]sum;

output co;

wire [7:0]sum;

wire co;

wire s1,c1,s2,c2,s3,c3,s4,s11,s44,c4,c11,s22,c22,s33,c33,c44;

//assuming carry in 0

fa x1(a[0],b[0],0,s1,c1);

fa x2(a[1],b[1],c1,s2,c2);

fa x3(a[2],b[2],c2,s3,c3);

fa x4(a[3],b[3],c3,s4,c4);

fa x5(a[4],b[4],c4,s5,c5);

fa x6(a[5],b[5],c5,s6,c6);

fa x7(a[6],b[6],c6,s7,c7);

fa x8(a[7],b[7],c7,s8,c8);

//assuming carry in 1

fa x9(a[0],b[0],1,s11,c11);

fa x10(a[1],b[1],c11,s22,c22);

fa x11(a[2],b[2],c22,s33,c33);

fa x12(a[3],b[3],c33,s44,c44);

fa x13(a[4],b[4],c44,s55,c55);
fa x14(a[5],b[5],c55,s66,c66);

fa x15(a[6],b[6],c66,s77,c77);

fa x16(a[7],b[7],c77,s88,c88);

//select either carry 1 or 0 using carry out of FA

//mux for sum select

mux x17(s1,s11,cin,sum[0]);

mux x18(s2,s22,cin,sum[1]);

mux x19(s3,s33,cin,sum[2]);

mux x20(s4,s44,cin,sum[3]);

mux x21(s5,s55,cin,sum[4]);

mux x22(s6,s66,cin,sum[5]);

mux x23(s7,s77,cin,sum[6]);

mux x24(s8,s88,cin,sum[7]);

//mux for carry select

mux x25(c8,c88,cin,co);

endmodule

module fa(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

wire d,e,f;

xor(sum,a,b,c);
and(d,a,b);

and(e,b,c);

and(f,a,c);

or(carry,d,e,f);

endmodule

module mux(a,b,s,q);

input a;

input b;

input s;

output q;

wire q;

assign q=s?b:a;

endmodule