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--
-- Company:
-- Engineer:
--
-- Create Date: 04/10/2017 03:57:53 PM
-- Design Name:
-- Module Name: BCD - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BCD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Z1 : out STD_LOGIC;
Z2 : out STD_LOGIC;
Z3 : out STD_LOGIC;
Z4 : out STD_LOGIC;
Z5 : out STD_LOGIC;
Z6 : out STD_LOGIC;
Z7 : out STD_LOGIC);
end BCD;
architecture Behavioral of BCD is
begin
Z1 <= (A or D) and (not B or not C) and (A or B or C or D);
Z2 <= (not B or not D) and (not A or B or not C) and (A or B or C);
Z3 <= (not C or not D) and (A or not B or C);
Z4 <= (not A or B or C) and (A or B or not C) and (not A or not B or not C);
Z5 <= (not A) and (not B or not C);
Z6 <= (not A or not B) and (not B or not C) and (not A or C or D);
Z7 <= (not A or not B or not C) and (B or C or D);
end Behavioral;