Introduction to

Integrated Circuit Design

Chapter 2
The MOSFET model: fundamentals,
weak and strong inversion, DC and
small-signal models for IC design,
mismatch

1
Semiconductors

Four types of charge are present inside a
semiconductor: the fixed positive charge of ionized
donors, the fixed negative charge of ionized
acceptors, the positive mobile charge of holes, and
the negative mobile charge of electrons.

We consider all donors and acceptors ionized
+
ND = N D and N A = N A

On this basis, the net positive charge density is

= q ( N D N A + p n)

2
Boltzmanns Law (1)

In equilibrium electrons and holes follow Boltzmanns
law and their concentrations (number per unit
volume) are proportional to -( Energy / kT )

e

k=1.38x10-23 J/K - Boltzmann constant

T - absolute temperature (K).

electron and hole densities in equilibrium are related
to electrostatic potential by
q ( 1 2 )
p ( 1)
=e kT
p ( 2)

q=1.6x10-19 C
3
 Boltzmanns Law (2)

n0 and p0 - equilibrium electron and hole concentrations
in the neutral bulk (=0 )
q q

p = p0 e kT
= p0 e u
n = n0 e kT
= n0 eu

u = / t - normalized electrostatic potential

t = kT / q - thermal voltage

the mass-action law is
np = ni2

ni - concentration of electrons (and holes) in the intrinsic

semiconductor
4
Example: Calculate the built-in potential for a Si p-n
junction with NA = 1017 atoms/cm3 and ND = 1018
atoms/cm3 ,T=300K
In equilibrium, if we choose the potential origin = 0 where the
semiconductor is intrinsic (i.e., where p0=n0=ni), then

p0 = ni e / t
n0 = ni e / t
/ t
Far from the junction in the n-side n0 N D = ni e nregion
Far from the junction in the p-side p region / t
p0 N A = ni e
The built-in potential is given by

ND NA ND N A
bi = n region p region = t ln t ln = t ln 2
ni n
i n
i
bi 26 ln (1015 ) 900 mV

5
Electrostatic in one dimension
Gauss law
is the volumetric charge density
x
0 x
FA = A ( x)dx
0
F
Q
F =0 A F=

x
Q = ( x)dx charge /unit
F is the electric field 0 area
x
Gauss law
F ( x) F ( x + x ) A F ( x + x ) F ( x ) = Ax
dF
A =
dx
d 2
= Poisson equation
2
dx
 The metal-insulator-metal capacitor
A-area of the capacitor
V1

V1 V2 Q
Fi = =
+Q M ti i
++++++++++++++++++
ti + or
I
0 ---- --------------- V1 V2 =
Q Q
=
Q M
M Ci Ci
x
V2 i
Ci = insulator capacitance/unit area
ti
ti - insulator thickness A i
Ci = insulator capacitance
i - permittivity of insulator ti
Q - charge/unit area 7
The MOS capacitor
Gate

Metal

Oxide

Semiconductor

Reference
terminal
(substrate or
Electronics 8
bulk)
The ideal two-terminal MOS structure
ox
VG Charge =
C ox
conservation t ox

QG + QS = 0 QS
QG M VG = s
Cox
tox O
0 tox - oxide thickness
+ QS Potential balance
S ox - permittivity of oxide equation
S x S - surface potential
_ Cox - oxide capacitance/unit area
QG (QS) - gate (semiconductor)
NA charge/ unit area
P-type silicon
NA acceptor concentration
Example: oxide capacitance
(a) Calculate the oxide capacitance per unit area for tox= 5 and 20
nm. The permittivity of silicon oxide is ox = 3.90. 0= 8.8510-14
F/cm is the permittivity of free space.

(b) Determine the area of a 1pF metal-oxide-metal capacitor for the

two oxide thicknesses given in (a).
(c) Determine the gate charge/unit area in C/cm2 and the number of
S =1 V
elementary charges of the 1 pF capacitor for VG -
Answer: (a) Cox = 690 nF/cm2 = 6.9 fF/m2 for tox=5 nm and Cox =
172 nF/cm2= 1.7 fF/m2 for tox= 20 nm. (b)The capacitor areas
are 145 and 580 m2 for oxide thicknesses of 5 and 20 nm,
respectively. (c) 0.6910-6 C/cm2 and 6.2.106 for capacitor area
of 145 m2 and 0.1710-6 C/cm2 and 6.2.106 for capacitor area of
580 m2.
Example: charge density z
y
t x
W

L
Assume that the electron concentration is n = 1016 cm-3 , L=W=1 um, t=0.1
um
(a) Calculate the volumetric charge density

(b) Calculate the total number of electrons and the corresponding charge
inside the volume

(c) Calculate the (areal) charge density seen from the z-direction

Answer: (a) = -1.6 10-3 C/cm3 (b) Number of electrons = 103, charge = -
1.6 x 10-16 C (c) charge density Qn= -1.6 x 10-8 C/cm2 .

11
 The flat-band voltage (VFB)
The flat-band voltage is the gate-to-bulk voltage required
to impose S =0 (and QS =0). When VGB=VFB silicon is
neutral everywhere.

VFB = VGB =Q =0
s S

1. Charges inside the

Why is the flat-band
voltage not equal to zero?
insulator and at the
semiconductor-insulator
interface
2. Contact potential
between the gate and the
semiconductor substrate

12
 The flat-band voltage (VFB)
1. Charges inside the insulator and at the semiconductor-
insulator interface induce a semiconductor charge at zero bias.
(x) G
Qo QG+QS+Qo =0
- Q-G - - - -
Metal Oxide Silicon +-Q+o + + + + + + + +
x VGB=0VFB
- - Q - -
QG QS S
B

(x)
QG+QS+Qo =0 G
Qo
Metal Oxide
- - Q- G - - - - - - -
Silicon
x +-Q+o +
- + + + + + + +
QS =0
QG
VGB=VFB QS=0
B
-tox 0
13
 The flat-band voltage (VFB)
2. In equilibrium (with the two terminals shortened), the contact
potential between the gate and the semiconductor substrate of the
MOS induces charges in the gate and the semiconductor for VGB=0.
(x)
QG+QS =0

Oxide Silicon
Metal VGB=0
x
Q
G

(x)
QG=QS =0

Metal Oxide Silicon

VGB=VFB
x

-tox 0 14
The flat-band voltage (VFB)
The effect of contact potential and oxide charges can be counterbalanced by
applying a gate-bulk voltage called the flat-band voltage VFB.

G
ln p, p
NA
n
silicon
metal oxide ni
QS=0
n ni2 / N A

VGB=
-tox 0 x
VFB
p-substrate
B The potential balance equation then
becomes
QS
VG VFB = s
Cox
15
Example: flat-band voltage
(a) Determine the expression for the flat-band voltage of n+ polysilicon-
gate on p-type silicon (b) Calculate the flat-band voltage for an n+
polysilicon-gate on p-type silicon structure with NA = 1017 atoms/cm3.
Answer: (a) In equilibrium, by analogy with an n+ p junction, the potential
of the n+-region is positive with respect to that of the p-region. The flat-
band condition is obtained by applying a negative potential to the n+
gate with respect to the p-type semiconductor of value
(b) N
VFB _ n + p = bi _ n + p = 0.56 V t ln A
ni
( )
VFB = 0.56 V t ln 107 = 980 mV
n+ gate
G
n+ gate
G
+ + + + + +

- - - - - -
980 mV
p-substrate p-substrate

B B

16
Regions of operation of the MOSFET:
Accumulation (p-substrate)

G VGB < V FB
QG Q S > 0
- - - - - - - - - - -
Qo
s < 0
+ + + +
VGB ++++++++++++++
QS Holes + accumulate in
the p-type semiconductor
surface

17
Regions of operation of the MOSFET:
Depletion (p-substrate)
G
QG
+ + + + + + +
+
VGB
- -- - -Q - - -
- - - - S
NA
p

ni
B n
s > 0 ni2 / NA
Depletion approximation
F qNA
F= ( xd x) ; 0 < x xd
qN A s
=qNA; 0 < x xd xd
s =0 ; x > xd
=0 ; x > xd
xd
0 0 xd x
x
oxide silicon
d qN A 2
qNA F = with ( xd ) = 0 ( x ) = ( xd x )
dx 2 s
oxide silicon qN A 2
( x = 0 ) = s = xd
2 s

s
2ss
QB qNAxd = qNA = 2qs NAs
qNA
0 xd x
oxide silicon

19
 Regions of operation of the MOSFET:
Inversion (p-substrate)
When s = F p ( x = 0) = n( x = 0) = ni

+ + + + + ln p,
NA
+ + + + n
VGB
----------------
QS
p
silicon
-- - -- - -
metal oxide ni
n ni2 / N A
Many electrons -tox x
0
approach the surface!
qs
ni2 qkTs
s > F p( x = 0) = N Ae kT
= n( x = 0) = e
NA
QS < 0 2qs
N A2 kT N A
e kT
= 2 s = ln = F
ni q ni
Strong inversion : the concentration of minority
carriers (n) becomes higher than that of holes (majority
carriers) deep in the bulk q ( x )

p = N Ae kT

ni2 qkT( x)
NA n= e
NA

ni2 q
ni2 kT kT N A
NA n = NA = e = 2 ln = 2F
NA q ni

The semiconductor operates

in strong inversion when
S>2F

21
Operating regions of the MOSFET: Summary
p NA
NA

log p, n
log p, n p silicon
silicon
ni ni
n
2
n / NA ni2 / N A
i
n x
0 Accumulati x 0 Depletion
0 < s < F ; QS < 0
s < 0; QS > 0
on

NA
NA

log p, n
p
log p, n

p silicon
silicon ni
ni
n n
2 ni2 / N A
n / NA
i
0 x
0 x Strong
Weak inversion 2F < s ; QS < 0
inversion F < s < 2F ; QS < 0

22
All-region MOSFET model (p-substrate)-1

d 2 dF
= =
dx 2 dx s

dF q
= ( p n + ND N A )
dx s

The figure shows the case of positive (inwards) applied field. The
maximum electron concentration occurs at the silicon surface, where
the electron energy is minimal. The opposite holds for holes.

F is the electric field

23
E is the electron energy
 All-region MOSFET model-2:
Poisson-Boltzmann equation
dF q
= ( p n + ND N A )
dx s
2
d dF q u u
2
= = ( p 0e n0 e + n0 p0 )
dx dx s
1 dF 2 q u
dx = d / F = ( p 0e n0 eu + n0 p0 )
2t du s
The Poisson-Boltzmann equation needs to
satisfy the following boundary conditions
d
= 0, =0 for x=
dx
( e u + u 1) (eu u 1)

2qt
2
F = [ po (eu + u 1) + n0 (eu u 1)]
s
Electric field in the semiconductor as a
function of the potential (p-type silicon)

2qt
F2 = [ po (e u + u 1) + n0 (eu u 1)]
s
 Relationship between surface potential
and applied gate voltage VG
QS = s Fs = sign(us ) 2q t s p 0(e u s + us 1) + n0 (eus us 1)

QS
VG = s
Cox
 Small-signal equivalent circuit of the
MOS capacitor-1 dQS 1
dQG dQS =
C gb =
=
C gb = dQ d 1
dVG dVG d s S s +
Cox dQS Cox
1
=
C gb
1 1
+
Cs Cox
Cs = dQS ds

d ( QB + QI )
Cs = = Cb + Ci QS Cs
d s

27
 Small-signal equivalent circuit of the
MOS capacitor-2
To calculate the semiconductor capacitance, the total charge per unit area in
the semiconductor is obtained from Gauss law and the expression for the
electric field F as

QS = s Fs = sign(us ) 2q t s p 0(e u s + us 1) + n0 (eus us 1)

Differentiating with respect to the surface potential

q q q
Cs = n0 (e u s 1)+ p 0(1 e u s ) = ( ns n0 ) + ( p 0 p s ) = Ci + Cb
Fs Fs Fs

in accumulation in inversion

q s p0 us /2 q s n0 us /2 Q
Cs Cb e Cs Ci e i
2t 2t 2t
us Cc C gb
Cox us + Cc C gb
Cox
MOS ideal C-V curve (VFB =0) p-type silicon

q s p0
Cfb =
t

in depletion
2q s p 0 Cox
Cs = =
2 s 2 s

Cox
=
Cgb 2q s p0
4V
1 + 2G =
Cox 29
The effect of measurement frequency
on the C-V characteristics
 Main approximation for compact MOS
modeling: the charge-sheet model
Minority carriers occupy a zero-thickness layer at the Si-SiO2
interface, where = s

s /t dQI QI
QI e Ci = =
d s t
Charge-sheet + depletion approximation for the bulk charge gives

QB qNAxd = 2qs NAs

2q s N A Cox = 2q s N A / Cox
Cb =
2 s 2 s is the body-effect coefficient

31
 Surface potential for negligible inversion
charge :sa = s sa Q I = 0 VG
Potential balance QI = 0 Cox
_
QB +
VG VFB = sa = sa + sa s = sa
Cox
Ci = 0 _
dVG Cb Cb QB
= 1+ = 1+ = n (sa ) = n (VG )
dsa 2 sa Cox +

VG Threshold voltage VG = VT 0 s 2F
sa
n
VT 0 VFB + 2F + 2F
VG VT 0
sa 2F + = 2F + VP
n
Where VP is called the pinch-off voltage
32
 Example: threshold voltage
Estimate VT0 for an n-channel transistor with n+ polysilicon gate,
NA=1017 atoms/cm3 and tox=5 nm.
Answer: The flat-band voltage is -0.98 V; F=0.419;
Cox= 690 nF/cm2. The body-effect factor is

= 2q s N A / Cox = 0.264 V

VT 0 VFB + 2F + 2F = 0.98 + 0.838 + 0.264 0.838= 0.1V

For this low value of the threshold voltage, the off-current (for VGS=0)
is too high for digital circuits.
Solution to control the magnitude of the threshold voltage without an
exaggerated increase in the slope factor a non-uniform
high-low channel doping.

33
The three-terminal MOS structure
VG
VC Carrier concentrations in Si
substrate follow Boltzmanns
n+ p law:
n, p exp(-Energy/kT)

The origin of potential is taken deep in the bulk

q q ( VC )

p = p0 e kT
= p0 e u ; n = n0 e kT
= n0 eu uC
electrons are no longer in equilibrium with holes due to the bias of
the source-bulk junction VC

pn = ni2 e uC = ni2 e VC / t
34
Unified Charge Control Model(UCCM)-1

VS VG VD Cox + Cb = nCox
n = n(VG )
n+ n+ dQI = nCox d s
p

QI
< 1 WI QI
d s Ci t
nCox Ci =
= t
dVC Ci + Cox
+ Cb SI
1

1 t
dVC = dQI
nCox QI

VS VC VD

35
Unified Charge Control Model (UCCM) -2
1 t Integrating from an arbitrary channel
dQI = dVC potential VC to a reference potential VP
nCox QI
yields UCCM
Cb
n = 1+ = n (VG )
Cox QIP
QI QI
VP VC = t + ln
= QI V
QIP
C =VP nCox t
QIP

Choosing the thermal charge = nCox t

QIP
as the pinch-off charge
QI
The normalized inversion (areal) charge = qI
density is
QIP

Normalized UCCM V P V C = t ( q I 1 + ln q I )
36
 The regional strong and weak
inversion approximations
QIP
QI QI
VP VC = t + ln
nCox t
QIP

VP VC t VP VC t
strong inversion weak inversion
QI
QI nCox (VP VC ) VP VC t ln 1

QIP
or, equivalently
VP VC +t
t
QI = QIP
e

37
The MOS transistor

38
 Charge sheet current density
x
t z
W
VS VD y

ID

L d dn
Assume that the electron concentration is n(x) J n = qn n + qDn
dy dy
The inversion charge per unit area is QI = qnt

drift diffusion
d s dQI
The drain current is I D = WtJ n = nW QI t
dy dy
Assume that the electron concentration is constant n= n0
VDS ID W
I D = nWQI = G = n QI
L VDS L
where G is the channel conductance
Drain current: Pao-Sah model

Idrift I diff
QI VG
Ci = ds t dQI dVC
t I D = WQI = WQI
dy QI dy dy
dVC d s
+ _
dQI
W VD
ID =
L VS
QIdVC
dQI = Ci ( dVC ds )

I D W
dQI g md = = QI (VD ,VG )
ds = dVC + t VD L
QI VG ,VS

40
40
Charge control current model
d s dQI
I D = nWQI + nW t
dy dy

dQI = (Cox
+ Cb )ds = nCox
d s

n=n(VG) is constant
along the channel
nW dQI
ID = (QI t nCox
)

nCox dy
Integrating along the channel yields

nW QIS
2 QID
2
ID = t ( QIS QID )

L
2nCox
41
Forward and reverse currents
symmetry of the rectangular geometry MOSFET
I D = I F I R = I (VG ,VS ) I (VG ,VD )

W QIS2 ( D )
I F ( R) = n t QIS ( D )

L 2 nC
ox

IR= reverse current

IF= forward current

CMOS Analog Design Using All-Region MOSFET 42

Modeling
 Normalization (areal) charge
nW dQI
ID = (QI t nCox
) QI = nCox
t Drift = Diffusion

nCox dy
Normalization charge
Drift Diffusion

qIS ( D ) = QIS ( D ) / ( nCox t )

2
( 2
) (
I F ( R ) = I S qIS ( D ) + 2qIS ( D ) = I S 1 + qIS ( D ) ) 1
2
(
i f ( r ) = I F ( R ) / I S = 1 + qIS ( D ) ) 1
t2 W W I D = I F I R = I S i f ir
I S = Cox n = I SQ
2 L L
IS and ISQ are the normalization (specific)
current and the sheet normalization
current, slightly dependent on bias.
43
Specific current t2 W W
The specific (normalization) current I S = Cox n = I SQ
2 L L
ISQ : process parameter slightly dependent on VG and T
ISQ 25 nA (p-channel)
ISQ 75 nA (n-channel)
in 0.35 m CMOS

44
 Charge-based definition of pinch-off
voltage VP QIP
= QI (VC = VP ) = nCox
t

in weak inversion
QI = Cbt e(
sa 2F VC ) /t
= Cox (n 1)t e(
sa 2F VC ) /t
(see Appendix 1)
n 1
or normalizing and taking the ln t ln qI = t ln + sa 2F VC
n
in weak inversion UCCM QI
reduces to VP VC t ln 1 = t ( ln qI 1)

QIP

UCCM is
asymptotically correct n
VP = sa 2F t 1 + ln
in weak inversion if n 1

VP sa 2F (see slides 32 and 75-76)

45
 Pinch-off voltage vs. gate voltage
4.00E+00 2
4.0 2.0
2
i f = I F / I S = (1 + 1) 1 = 3
3.00E+00
3.0 1.5
1.5
pinch-off voltage

slopefactor
2.0
2.00E+00

1
1.0
1.0
1.00E+00

0.5
0.5
0
0.00E+00 VP dVP dsa Cox 1
= =
dVG dVG Cb + Cox n
-1.0
-1.00E+00 0 0
0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

0 1.0 2.0 3.0 4.0 5.0 VG (V)

VT0 (equilibrium threshold voltage)

Useful approximation: VG VT 0
VP
n
46
Normalized charge-based MOSFET model
uP uS ( D ) = 1 + i f ( r ) 2 + ln ( 1 + i f (r ) 1 )
Inversion charge per unit area qI

q I = 1+ i 1

u P u = q I 1 + ln q I
q IS

q ID

MI
2 WI
i = (1 + q I ) 1 if ir
Current i uS uD Potential u
id = i f ir uP
uG uT 0
n
I D = I S id
The I-V relationship
VP VS = t 1 + i f 2 + ln
( )
1+ i f 1

1,00E-03
10-3 VD = VG
ID (A)
1,00E-04
VD
VS = 0 V
ID
1,00E-05

0.5
1.0
10-6
1,00E-06
1.5
2.0 VG VS
1,00E-07

2.5

1,00E-08 3.0

10 -9
1,00E-09
0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00
0 1 2 3 4 4,50E+00
VG (V)
Common-source characteristics
48
Weak inversion model
Weak inversion VG VT 0
if(r)<1 n
VS ( D ) = t 1 + i f ( r ) 2 + ln
( )
1 + i f (r ) 1

-1 if(r)/2
VG VT 0
VS / t W
I D = I0 e n 1 e VDS / t I0 = n t2e1 = 2 I S e1
nCox
L

49
Strong inversion model (1)
VG VT 0
n
VS ( D ) = t 1 + i f ( r ) 2 + ln
( )
1 + i f (r ) 1

Strong inversion VG VT 0
VS ( D ) t i f ( r ) = t I F ( R ) I S
if(r)>>1 n

W 2 2

I D = I F I R nCox ( G T0
V V nVS) ( G T0
V V nVD)
2nL

Moderate inversion
1<if(r) <100 Both sqrt(.) and ln(.) terms are important

50
Strong inversion model (2)
ID
VDS

VG
ID/IF

VDSsat=VP=(VG-VT0)/n VDS

Transistor output characteristic

51
Strong inversion model (3)
Cox W Cox W
ID ID = (VG VT 0 ) ID ID = (VG VT 0 nVS )
2n L 2n L

SCE, , n,
model
VT0 VG (VG VT 0 ) n
VDD VS
ID VDD
ID

VG
VG
VS

52
Transconductances - 1
Transconductances I D = g mg VG g ms V S + g md V D + g mb V B
I D I I I
g mg g ms + g md + g mb = 0 g mg = , g ms = D , g md = D , g mb = D
VG VS VD VB

( IF IR ) IF W
Calculation of gms g ms = = = QIS
VS VS L

W
g md
= QID
L Pao-Sah ID (UCCM)
(i f ir )
g mg = I S
VG i f i f g ms g md
= g mg = g m =
UCCM VG nVS n
ir i g in saturation
= r g m = ms
VG nVD n
53
Transconductances - 2
2I S W
g ms ( d ) =
t
( )
1 + i f (r ) 1 =
L
nCox t ( 1 + i f (r ) 1 )
g g md gm 2
g m = ms =
n I D nt ( 1 + i f + 1 + ir )
For VDS/t<<1 we have ifir In saturation

gm 1 gm 2
=
I D nt 1 + i f I D nt ( 1+ if +1 )
 Transconductances - 3

VDD
ID

VG VS

Gate transconductance VS= 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V .

W=L=25 m, tox=280
55
The gms/IF ratio (in saturation)
g ms ( d ) t 2 1 WI (if <1)
Transconductance = 2
-to-current ratio I F (R) 1 + i f (r ) + 1 SI (if >>1)
i f (r )
102

gms/IF

W=25 m
tox = 28 nm (IS = 26 nA)
Seqncia1
101 L=25 m, tox= 280
tox = 5.5 nm (IS = 111 nA)
Seqncia2

L=20 m, tox= 55
model
Seqncia3

100
1,00E-03 1,00E-01
10-4 10-2 100 102 if 104

56
.

gm/ID in the linear region: VT-extraction

gm 1
=
ID VDS 0
nt 1 + i f

Thus, at threshold (if =3) gm/ID

is at
gm 1 dI D of its maximum value,
=
I D I D dVG
I D (i f = 3,VDS = t / 2) g mst / 2
2I S
=
t
( )
1 + 3 1 t / 2 = I S

Considering VDS = (1/2)kT/q

gm/ID =0.531 (gm/ID)max
ID =0.88IS
MOSFET: low-frequency small-signal
model in weak inversion
G

IR
g md = g md vd
t

id
gmbvb
S D

gmsvs
g ms g md I D
gm = = g ms =
IF
n nt t
gmvg
B

g ms = g m + g mb + g md
58
Low-voltage operation of the common-
source amplifier
VDD Intrinsic gain stage
IB ( IB ideal current source) weak inversion operation

VO
ID VDS

M1 g g g md 1 g ms g ms
= e t
AV = m = ms = 1
+ g md ng md n g md g md
VI

1 t
VDS

AV = e 1
n

or

VDS = t ln (1 + n AV ) 59
Lowvoltage operation of the (C)MOS
inverter V DD
VDD
M2
iD
VDS = t ln (1 + n AV ) vout
+
- vin M1
vout
VDD
Av
Minimum supply voltage for
amplification AV = 1 VTH = VDD/2
ideal MOSFET n = 1 vin
VTH VDD

VDS = VDD VDS = VDD / 2

VDD min = (ln 2)t VDD min = 2(ln 2)t

60
Low-voltage operation of the common-
gate amplifier

qVDS
vo g ms
Av ,cg = = =e kT
vi g md

The common-gate amplifier provides a voltage gain

of greater than unity for VDS>0. Very useful
property for lowering the supply voltage limit for
the operation of oscillators (later). Common- gate
Colpitts oscillator
61
 MOSFET model at a glance
t2 W W
I D = I S i f ir I S = Cox n = I SQ
2 L L

VG VT 0
VP VS ( D ) = t 1 + i f ( r ) 2 + ln
( 1 + i f (r ) 1
) VP
n

2I S W
g ms ( d ) =
t
( 1 + i f (r ) )
1 = nCox t
L
( 1 + i f (r ) 1 )
gm 2
g g md =
g m = ms
n
I D nt ( 1 + i f + 1 + ir )
Noise and mismatch

The spontaneous fluctuations over time of the current
and voltage inside a device, which are basically
related to the discrete nature of electrical charge, are
called electrical noise.

Time-independent variations between identically
designed devices in an integrated circuit due to the
spatial fluctuations in the technological parameters
and geometries are called mismatch.

Mismatch (spatial fluctuation) and noise (temporal
fluctuation) are similar phenomena, both depending
on process, device dimensions, and bias.

Mismatch can be seen as dc noise.

63
 Systematic and random mismatch

Mismatch is the name given to the time-independent differences
between identically designed and identically used devices.

The performance of most analog, or even digital, circuits relies on
the concept of matched behavior between identically designed and
used devices.

In analog circuits, unwanted differences in the effective value of
equally designed components, such as threshold voltage
differences of millivolts or less, can critically reduce the
performance and/or yield of a circuit.

Even for digital circuits, transistor mismatch can lead to
propagation delay differences in clock trees, reducing the
robustness of the circuit.

The shrinkage of the MOSFET dimensions and the reduction in the
supply voltage make matching limitations even more important.

64
Global manufacturing variations

GLOBAL variation total variation of a
parameter over a chip, a wafer (a batch) caused
by equipment variations & spatial drift, e. g.

Dimensional errors (photo-mask sizes, lens
aberrations)

Photo-resist thickness variations

Mechanical strain variation

Because GLOBAL variations are correlated
across die, they are minimized by design tricks:

common centroid components

distance reduction between identically designed pairs

same orientation, etc.

65
 Random local variations

LOCAL variation variation in a component with
respect to an identical adjacent component,
caused by atomistic stochastic effects

ion implantation, dopant diffusion and clustering

Interface states, fixed charges

edge roughness, poly-Si grain effects

Simulation: generate random mismatch that
depends on dimensions, process parameters,
and bias.

Designers must understand the limitations
imposed by LOCAL variations on performance.

66
Pelgroms model of mismatch - 1

number of atoms per unit volume in silicon is NSi=51022 cm-3

probability p of having an acceptor atom in the place of a silicon
atom NA
p= 1
N Si

number N of crystal atoms in the depletion region under the gate
N = (WLxd ) N Si

fluctuation in the number of acceptor atoms under the gate of an
n-channel transistor (binomial distribution)
W
N = Np N2 = Np(1 p)
source
N = Np = (WLxd ) N A L

N2 = Np (1 p ) Np = N = (WLxd ) N A xd
drain
since p<<1(Poisson distribution)

67
Pelgroms model of mismatch - 2
( number of acceptors under gate )
(VT 0 ) = q )
= q WLxd N A / (WLCox

WLCox

In most applications: standard deviation of the difference

between the threshold voltages of two identical transistors
(VT0=VT1-VT2)

q 2 xd N A AVT
( VT 0 ) = 2 (VT 0 ) = =
WL
Cox WL

q 2 xd N A
AVT =
Cox

68
Pelgroms model of mismatch - 3

The standard deviation of the n-channel MOSFET threshold voltage

vs. the inverse square root of the gate area for a .18 m process
69
VTO matching coefficient vs. process

The threshold-voltage matching coefficient over process generations

70
 Mismatch: Experimental results 1
Test circuit Saturation level dependence
VG VD
IB ID

MREF Mi

VB

Measured: ; Model: ---

Test chip: 24 NMOS transistors (W=30m, L= 1.2m) in the ES2 1.2m
CMOS DLM process
71
Mismatch: Experimental results 2
Dependence on inversion level

Linear:
(VDS=50mV); Saturation: (VDS=1V) regions.

; Model
72
 References

C. Galup-Montoro and M. C. Schneider, "Mosfet Modeling For Circuit
Analysis And Design", International Series on Advances in Solid State
Electronics and Technology, World Scientific, 2007

Mrcio Cherem Schneider and Carlos Galup-Montoro, "CMOS Analog

Design Using All-Region MOSFET Modeling", Cambridge University
Press, 2010

73
Appendix 1: Calculation of the inversion
charge density in WI
ni2
n = n0eu uc = 2 N Aeu uc = N Aeu 2uF uc
NA
sa
xi
nd
QI = q ndx = q
0 0 d
dx
d QB
=
dx s
q s kT usa
u 2 uF uc s kTN A

QI = NA e du = eusa 2uF uc
QB q 0 2q s N Asa
2q s N A kT usa 2uF uc
= Cbt e( sa F C ) t
2 V /
QI = e
2 sa q

74
 Appendix 2: Modeling the bulk charge
from accumulation to inversion
s + t (e s / t 1)
Charge-sheet approximation QB = sgn(s )Cox

Potential balance VG VFB s = ( QI + QB ) / Cox

sa = s Q =0
I

(VG VFB sa )2 = 2 [ sa + t (e sa t
1 )]

n = 1
1 dQB
= 1+
Cb
= 1+
(
sgn (sa ) 1 e sa / t )
Cox ds s =sa
Cox (
2 sa + t esa t 1 )

75
Modeling from accumulation to inversion:
Surface potential and pinch-off voltage (VP)

76