A Systematic Network-on-Chip Trafc Modeling
and Generation Methodology
Zhe Wang, Weichen Liu, Jiang Xu, Xiaowen Wu, Zhehui Wang, Bin Li , Ravi Iyer , Ramesh Illikkal
The Hong Kong University of Science and Technology, Intel Labs, Hillsboro, OR, USA.
AbstractThe Network-on-chip (NoC) based multiprocessor
system-on-chip (MPSoCs) is becoming a promising architec-
ture to meet modern applications ever-increasing demands for
computing capability under limited power budget. NoC trafc
patterns are essential tools for NoC performance assessment
and architecture design exploration. In this paper, we present
a systematic NoC trafc modeling and generation methodology
and a set of realistic NoC trafc patterns called MCSL, which are
generated through the methodology. The proposed methodology
can faithfully capture both the communication behaviors of real
applications in NoCs and the temporal dependencies among them.
And it optimizes application memory requirements, mapping
and scheduling to maximize overall system performance and
utilization before extracting trafc patterns through cycle-level
simulations. Extensive experiments are conducted to verify the
effectiveness of the methodology, and evaluate the performance
of the generated trafc patterns. The results show that the MCSL
trafc patterns can be used to study NoC characteristics more
accurately than traditional random trafc patterns.
I. I NTRODUCTION
Network-on-Chip (NoC) [1] is becoming a popular com-
munication architecture for Multiprocessor System-on-Chips
(MPSoCs) to meet the ever increasing computation and
communication requirements of emerging applications. Large
amount of efforts from both academia and industry have been
invested in NoC designs. Trafc models, or trafc patterns,
play an important role in both the NoC architecture design
exploration and performance evaluation. Random trafcs were
widely used to approximate the communication characteristics
of real applications in early works. However, researchers
pointed out that traditional random trafc modeling approaches
can hardly faithfully reect the features of real application
trafcs [2]. To this end, trafc modeling should be based on
realistic applications to guarantee faithfulness and accuracy.
In this paper, we present a systematic trafc modeling
and generation methodology based on realistic multiprocessor
applications and a trafc pattern suite for efcient NoC-
based MPSoC evaluations. The proposed trafc modeling and
generation methodology utilizes the COSMIC benchmarks [3],
especially takes advantage of the TCG models it provided, to
accurately and efciently capture the communication charac-
teristics of real applications. It optimizes the memory allo-
cation and the task mapping and scheduling for application
execution to maximize overall system performance and re-
source utilization. Two types of trafc patterns are generated
through our methodology, the recorded trafc patterns (RTP)
and statistical trafc patterns (STP). The former provides
This project is supported by Intel and GRF620911.
c
978-1-4799-5230-4/14/$31.00 2014 IEEE 675
detailed communication traces for comprehensive NoC studies,
while the latter helps to accelerate NoC explorations at the cost
of accuracy. We publicly release them as the MCSL (Multi-
Constraint System-Level) NoC trafc patterns online [4]. A set
of experiments are conducted to analyze the generated trafc
patterns, and evaluate their performance as well as power
efciency. The results show that the MCSL trafc patterns
can be used to study NoC characteristics more accurately than
traditional random trafc patterns.
The rest of the paper is organized as follows. In Section II,
we illustrate the trafc modeling and generation methodology.
Section III shows the experimental results on the analysis
and evaluation of the realistic trafc patterns. And section IV
concludes the work.
II. T RAFFIC MODELING AND GENERATION METHODOLOGY
An overview of the trafc modeling and generation method-
ology is shown in Fig. 1. The generation process starts
with the COSMIC application models. Since multiprocessor
applications are often performance-sensitive, it is necessary to
perform optimizations and performance evaluation for trafc
generation. As shown in Fig. 1, the trafc patterns are gen-
erated through four steps: memory space allocation, mapping
and scheduling, performance evaluation and trafc generation.
Two types of trafc patterns are generated, called RTP and
STP. The generation steps interact with each other closely.
They are essential for the methodology since these decisions
substantially affect the nal trafc pattern. We specically
optimized the memory space allocation and task mapping
and scheduling for different architecture models, and the
optimized decisions can take full advantage of the parallel
hardware resources and improve overall system performance
and resource utilization. The methodology is designed with the
exibility, scalability and extensibility on the choice of these
algorithms.
A. The COSMIC benchmark suite
COSMIC benchmark suite provides faithful models for re-
alistic applications to facilitate multiprocessor system studies.
We take advantage of the TCG models which is provided in the
COSMIC, to perform accurate and efcient trafc modeling
and generation for real applications. It allows us to bypass
operating systems (OS) and compilers to quickly explore novel
MPSoC architectures.
The applications are modeled by a weighted directed acyclic
graph model, called task communication graph (TCG). The
TCG is dened as a tuple Gt = (V, E), where V is the set of
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Fig. 1. An overview of the trafc generation methodology.
weighted vertices denoting the computational tasks, and E is
the set of weighted directed edges denoting the communication
channels among tasks. Each task vi V has a worst-case
execution time ti , which is measured in the number of clock
cycles. Each edge ei = (vi,s , vi,d , wi ) E has a source task
vi,s , a destination task vi,d and the amount of data wi sent
from vi,s to vi,d , which is measured in number of words (32
bits in this work). More details about the COSMIC benchmark
suite can be found at [3].
B. Architecture model
The architecture model captures the hardware resources in
MPSoCs including processing blocks (PBs) and NoCs. In
this work, we target regular NoC topologies, such as mesh,
torus and fat tree, and homogeneous MPSoCs. Detailed NoC
congurations are listed in Table. I. Formally, we dene an
architecture model as a graph Gp = (P, N ), where P is a set
of PBs, and N is an NoC architecture. The trafc generation
methodology takes the architecture model as an input for trafc
generation. And the proposed methodology is able to support
more NoC topologies and congurations.
C. Memory space allocation
We assume that a virtual private memory is assigned for
each communication edge to store the data generated by the
source task. When the application is executed repeatedly in
an iterative fashion, insufcient memory space allocated to the
edge can limit the parallelism of the application and impact its
performance. Therefore, it is important to determine the mem-
ory requirement on the edges to maximize the performance
while the total size of memory totally used are minimized.
Basically, we apply genetic algorithms to nd the minimum
memory space that will make no negative impact to the
application performance. There are two objectives to be op-
timized: maximizing application throughput in higher priority
and minimizing total memory size in lower priority. We apply
genetic algorithms to explore possible memory size alloca-
tions, evaluate them by calculating the theoretical application
throughput under the memory constraint, and conduct these
two steps iteratively until a satisable result is obtained.
676
The algorithm is given in Alg. 1. It runs iteratively on a
set of randomly generated candidates (called population, each
candidate is called an individual) until a predened threshold
on the number of generations is reached or a satisfying result is
obtained. An individual/candidate is a possible memory size
assignment, which is a vector of memory sizes for all the
edges in the application model. In each generation (Lines 3
9), mutation and crossover are applied to the individuals to
generate new candidates, and selection is used to select better
individuals in the population by calculating the tness values
of the candidates. We use uniform order-based crossover and
scramble sub-list mutation on the individuals to generate
offspring [5]. For selection, we dene the combination of
throughput and total memory size as the tness value, where
throughput is with higher priority to optimize. We keep the
population size unchanged by selecting a constant number
of candidates in each generation. There are two constant
parameters in the algorithm, pop size for the number of
individuals in the population, and gen num for the number
of generations for the algorithm to run.
D. Task mapping and scheduling
The trafc generation methodology uses a centralized
scheduling strategy to manage the entire chip resources and
coordinate processing blocks (PBs). In this way, the scheduling
and control decisions made are globally optimized. Formally,
given an TCG application model Gt (V, E), and an architecture
model Gp (P, N ), the application mapping and scheduling
problem is to nd a mapping M : V P for each task in V
to a PB in P , as well as a static order schedule S : V N for
the set of tasks assigned to the same PB, where each task is
assigned a unique number indicating its execution order, such
that the performance is optimized.
We develop a load balanced mapping and static order
scheduling approach. The basic idea is to distribute processing
and network transmission workloads evenly to achieve high
utilization of the hardware resources. The mapping strategy is
to assign tasks to PBs one by one in the topological order
dened by the dependency relations in the graph, and the
schedule on each PB is determined by the sequence of the
tasks on the same PB generated during the mapping. The
Algorithm 1 The genetic algorithm for memory space alloca-
tion
Require: application model Gt (V, E)
1: dene pop size, gen num, best sol
2: pop parents = Initialization( pop size )
3: while gen num is not reached do
4: pop of f spring = pop parents
5: Crossover( pop of f spring )
6: Mutation( pop of f spring )
7: pop parents = Selection(pop of f spring, pop size)
8: best sol = UpdateBestSolution( pop parents )
9: end while
10: return the best memory space allocation best sol

objective is to minimize the application execution time per
iteration with network communication overhead taken into
consideration. The tasks are evaluated and assigned one by
one in the order dened by the dependency relationships in
the TCG model. For each task v, the weight of assigning it to
a processor p is calculated in the following cost function:
w(v, p) = c1 t(v, p) + c2 q n(v, p), (1)
in which t(v, p) is the required time for task v to nish
execution on p, dened by the time for executing previously
assigned tasks on p plus the execution time of v on p, and
n(v, p) is the total amount of network transmission, dened
by the number of packets generated by v and sent to other PBs.
q is an architecture-specic scaling factor which balances the
two terms which can be measured in different units, and c1 , c2
are constant factors which can be manually adjusted to tradeoff
the weight of the two parts in the overall cost.
E. Generation of trafc patterns
The RTP contains detailed and accurate traces of task
executions and communications. It is used for precise and
comprehensive NoC studies. RTPs are generated by cycle-
level simulations for real applications on different NoC based
MPSoCs with the memory space allocation and mapping and
scheduling results. It contains more accurate computation and
communication traces, where all the task execution and packet
generation events are recorded. The RTPs are reusable on
NoCs with different congurations but the same topology.
Since the exact packet delays among PBs are related with
specic NoC congurations, the RTPs keep the packet de-
pendencies instead of exact timings. When the trafc patterns
are applied to a different NoC conguration, all the temporal
relations can be reconstructed correctly.
The STP gives a concise representation of the trafc by
mathematical modeling. It can be used to support long simu-
lation runs, and is useful for system-level statistical evaluation
and analysis. With the results obtained above, the STPs are
synthesized with the statistical behaviors of task executions,
packet generations and transmissions in different execution
instances. Three key components, the task execution times,
the communication data volumes and the time intervals that
the communication data are assembled into different packets,
are described by statistical formulations in the STPs. The
generated patterns are useful for evaluating NoCs with similar
topologies, and other NoC metrics can be exibly recorded in
the STP by the proposed generation methodology.
III. P ERFORMANCE EVALUATION AND ANALYSIS
Extensive performance evaluations are conducted to verify
the effectiveness of the proposed trafc generation methodol-
ogy and the generated realistic trafc patterns. We generate
trafc patterns for 8 real applications included in the COS-
MIC benchmark suite, which are FFT-1024 complex, Fppp,
TURBO, MolecularDynamics, Robot, RS-32 28 8 dec, RS-
32 28 8 enc and Sparse. Different NoC congurations are
677
TABLE I
T HE N O C CONFIGURATIONS USED FOR TRAFFIC GENERATION .
Topology Size (number of processors)
2x2, 2x4, 3x3, 4x4, 5x5, 4x8, 6x6, 7x7, 8x8,
Mesh 9x9, 10x10, 11x11, 8x16, 12x12, 13x13,
14x14, 15x15, 16x16
2x2, 2x4, 3x3, 4x4, 5x5, 4x8, 6x6, 7x7, 8x8,
Torus 9x9, 10x10, 11x11, 8x16, 12x12, 13x13,
14x14, 15x15, 16x16
Fattree 4, 8, 16, 32, 64, 128, 256
studied in this work, whose specics are listed in Table. I. We
rstly compare the real trafcs with the uniform trafcs to
demonstrate that the former reects the actual communication
behaviors more accurately. Then we evaluate specic perfor-
mance for each real application on MPSoCs with different
NoC architecture. At last, we show the energy efciency of
the FFT executed on various NoC based MPSoCs. Due to
space limitation, only the experimental results on the systems
with network sizes of 16, 32 and 64 are showed.
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Fig. 2. Average performance results for trafc patterns on mesh/torus/fat
tree-based 16-processor, 32-processor and 64-processor MPSoCs.
Fig. 2 shows the normalized average network performance
results (network throughput and packet delay) of trafc pat-
terns on different NoC congurations. The results of STP on
16-processor systems are normalized to 1, and the uniform
trafc patterns (UNI) are generated by setting their injection
rates as those of the corresponding RTPs. From the gure,
we can observe that the performance of STP and RTP are
very close to each other, but the difference on packet delays
between the uniform trafc and corresponding RTPs (STPs)
can be as large as 99.2%. This signicant difference shows
reinforce the conclusion that the uniform trafc patterns can
hardly reect the characteristics of real application trafc. A
possible explanation to this is that the uniform trafcs do not
consider the real application execution dependencies, while the
proposed methodology make dedicated analysis on them and
incorporates them in the generated trafc patterns.
Due to space limitation, we only show the RTP performance
for each application on different MPSoC architectures. Fig. 3
shows the normalized performance result for each application
on different sized MPSoCs with the three NoC topologies.
The performance result of each application on 16-processor
fat tree based MPSoC is normalized to 1. The gure shows
that as larger amount of processing resources are provided,
generally the network throughput increases, the packet delay
and execution time per iteration decreases. Some applications,
 
 

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(a) Network throughput (b) Packet delay (c) Execution time per iteration

Fig. 3. Normalized performance result for each application on mesh/torus/fat tree-based 16-processor, 32-processor and 64-processor MPSoCs.

such as FFT, MolecularDynamics and Sparse, can better take IV. C ONCLUSION
advantage of the parallel resources than the other applications In this paper, a systematic NoC trafc modeling and gen-
do. For example in Fig. 3(b) the FFT, the average packet delay eration methodology is presented and a set of real application
for 64-processor mesh system is 51.6% less than that on 16- trafc patterns are generated and publicly released as the
processor mesh system, and it gets signicant performance MCSL NoC trafc patterns. The proposed methodology can
improvement as the processor number grows exponentially in capture both the communication behaviors in NoCs and the
terms of execution time in Fig. 3(c) , where the execution temporal dependencies among them. The trafc generation
time on 64-processor mesh system is only 48% of that on 16- methodology uses the formal computation models provided in
processor mesh system. Regarding different NoC topologies, the COSMIC benchmark suite to capture both communication
the performance results are quite irregular. Not any type of and computation requirements of real applications. Memory
NoC topology can outperform the others in all situations. space allocation and application mapping and scheduling are
optimized to better reect the communication behaviors in

W practical MPSoC designs. We generate two types of trafc
E

W
patterns, RTP and STP. The former offer detailed commu-



nication traces for comprehensive NoC studies, while the
latter help to accelerate NoC explorations at the cost of

accuracy. The generated MCSL trafc patterns can be easily


incorporated into existing NoC simulators to substantially
improve NoC simulation accuracy. Experiments are conducted

&D d to evaluate the performance of the MCSL trafc patterns, and
verify the effectiveness of the proposed methodology. And the
Fig. 4. Normalized energy consumption of FFT run on mesh/torus/fat tree-
based MPSoCs with different sizes. experimental results show that the MCSL trafc patterns more
accurately reect the characteristics of real applications than
the corresponding uniform trafc patterns.
Due to space limitation, only the energy consumption results
of FFT are showed in Fig. 4. The power model that we used R EFERENCES
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