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ECE 111 - Digital Systems Lab
ECE 111 - Digital Systems Lab
Systems Lab
Introduction to VHDL
Stelios Neophytou
VHDL
VHDL is a hardware description language used to
specify logic designs.
Sponsored (early 80s) by IEEE and US DoD.
Features:
Hierarchical designs
Interface and behavior specified precisely (and
separately)
Algorithmic or hardware-oriented behavior specifications
Concurrency, timing, clocking can be modeled;
design can be simulated accurately.
port statement
defines inputs
and outputs X
My_Component Z
Comments Y
VHDL keywords
Identifiers
Port Mode
Data Type
Comments
VHDL keywords
Corresponding
Identifiers Z = XY
entity
Port Mode
Data Type
12-Apr-10 Introduction to VHDL 5
VHDL Language elements
Comments: start with --, go to end of line
Keywords (reserved words): entity, port, is, in,
out, end, architecture, begin, end, when, else, etc.
Identifiers (user-defined variables)
ARCHITECTURE
ARCHITECTURE test_int
test_int OF
OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: INTEGER;
INTEGER;
BEGIN
BEGIN
aa :=
:= 1;
1; --
-- OK
OK
aa :=
:= -1;
-1; --
-- OK
OK
aa :=
:= 1.0;
1.0; --
-- illegal
illegal
END
END PROCESS;
PROCESS;
END
END test_int;
test_int;
Integer (cont.):
We can also define range of integers.
Examples:
type CountValue is range 0 to 15;
type Twenties is range 20 to 29;
type Thirties is range 39 downto 30;
TYPE
TYPE binary
binary ISIS (( ON,
ON, OFF
OFF );
);
...
... some
some statements
statements ......
ARCHITECTURE
ARCHITECTURE test_enum
test_enum OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: binary;
binary;
BEGIN
BEGIN
aa :=
:= ON;
ON; ---- OK
OK
...
... more
more statements
statements ... ...
aa :=
:= OFF;
OFF; ---- OK
OK
...
... more
more statements
statements ... ...
END
END PROCESS;
PROCESS;
END
END test_enum;
test_enum;
12-Apr-10 Introduction to VHDL 14
Booleans
type boolean is (false, true);
variable A,B,C: boolean;
C := not A
C := A and B
C := A or B VHDL Object
C := A nand B
C := A nor B
C := A xor B Assignment operator
C := A xnor B for variables
VARIABLE
VARIABLE XX :: data_bus;
data_bus;
VARIABLE
VARIABLE YY :: BIT;
BIT;
YY :=
:= X(12);
X(12); --
-- YY gets
gets value
value of
of element
element at
at index
index 12
12
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VHDL Architecture Structure
architecture name_arch of name is
Signal assignments
begin
Concurrent statements Processes contain sequential
statements, but execute
Process 1 concurrently within the
architecture body
Concurrent statements
Process 2
Concurrent statements
end name_arch;
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VHDL Process
P1: process (<sensitivity list>)
<variable declarations>
begin
<sequential statements>
end process P1;
Within a process:
Variables are assigned using :=
Optional process label and are updated immediately.
Signals are assigned using <=
and are updated at the end of
the process.
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12-Apr-10 Introduction to VHDL 21
If-Then-Else statement
[ if_label:]
if boolean_expression then
{ sequential_statement; }
{ elsif boolean_expression then
{ sequential_statement; } }
[ else
{ sequential_statement; } ]
end if [ if_label ];
Notation:
[ ] -- optional
{ } -- repeatable
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12-Apr-10 Introduction to VHDL 22
CASE statement
[ case_label:]
case expression is
{ when choices =>
{ sequential statement; }
}
end case [case_label];
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12-Apr-10 Introduction to VHDL 23
2-to-4 decoder in VHDL:
Gate-level diagram
end decoder_2_to_4;
Sel y
a(3:0) 00 a
8-line
b(3 :0) 01 b
4x1 y(3 :0)
c(3 :0) MUX 10 c
d(3 :0) 11 d
sel(1:0)
entity mux4g is
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
c: in STD_LOGIC_VECTOR (3 downto 0);
d: in STD_LOGIC_VECTOR (3 downto 0);
sel: in STD_LOGIC_VECTOR (1 downto 0);
y: out STD_LOGIC_VECTOR (3 downto 0)
);
end mux4g;
entity adder_4_b is
port(B, A : in std_logic_vector(3 downto 0);
C0 : in std_logic;
S : out std_logic_vector(3 downto 0);
C4: out std_logic);
end adder_4_b;
begin
sum <= ('0' & A) + ('0' & B) + ("0000" & C0);
C4 <= sum(4);
S <= sum(3 downto 0);
end behavioral;
begin
stage0: fulladd port map (Cin,x0,y0,s0,c1);
stage1: fulladd port map (c1,x1,y1,s1,c2);
Custom order
stage2: fulladd port map (c2,x2,y2,s2,c3);
stage3: fulladd port map (Cin=>c3,Cout=cout,x=>x3,y=>y3,s=>s3);
end structural;
entity dec2to4 is
port (w: in std_logic_vector(1 downto 0);
e: in std_logic;
y: out std_logic_vector(0 to 3));
end dec2to4;