Laboratory Report 3

Flip Flops and Counters

ECE-111
Digital Systems Lab
Instructor: Neophytou Stelios

Author Name: Mohd Shaidul Ekram

Experiment Conducted on: 09/03/2016

Report Submitted on: 20/04/2016

School of Sciences and Engineering

Department of Electrical & Computer Engineering
University of Nicosia
Nicosia, Cyprus

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 Table of Contents
MAIN OBJECTIVES...............................................................................................3

INTRODUCTION....................................................................................................3

EQUIPMENT USED................................................................................................3

EXPERIMENTAL METHOD AND

PROCEDURE......................................................................................................... 4

Part 1........................................................................................................................4

Part 2........................................................................................................................6

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1. The Objectives of this Experiment :-

Building counters using flip flops. Designing two different counters, one synchronous
and one asynchronous. The 4-bit Up/Down asynchronous counter will be built using D-
Flip Flops. The 4-bit synchronous counter with enable will be designed using J-K Flip
Flops.

2. A General Introduction
A counter is a sequential circuit that has a number of different uses in computer systems.
The main operation of a k bit counter is to circulate among some or all of the 2k possible
values, one every clock cycle. Counters are usually built using flip flops. A flip flop is a
memory element that can store only one bit (either a 0 or a 1) at a time.

An Up counter is a counter that counts in the increasing order of the binary numbers and
a down counter counts in a decreasing order of binary number.

An asynchronous counter is a counter where not all the flip flops are synchronized with
an external clock signal. The least significant flip-flop is driven by the external clock
signal and the clock inputs of all the other flip flops are driven by the output of the
previous level flip flop. Additionally, an up/down counter is a counter that can be set to
count both upwards and downwards, usually by giving the appropriate value to an extra
input.

A synchronous counter is a counter where all flip flops are synchronized with an external
clock signal. The difference here is that the clock is driving all the clock inputs of the flip
flops, the remaining inputs of the flip flops should be used to control the toggling of each
flip flop. A counter with an Enable input is a counter which has an extra input (enable)
that activates or terminates the counting procedure.

3. Instruments Used

The Spartan -3 FPGA starter kit board

4. Experimental Mechanism and Technique

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 Part 1 Software Part

Counter Designs

A 4 bit asynchronous up/down counter

A 4 bit synchronous counter

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 Counter Design Simulation

Simulation of the synchronous counter

Assigning Pin location constraints

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 In this section, we assign the pins on the FPGA to inputs and outputs of
both the designs.

Part 2 - Hardware Part

Downloading the design to the Spartan 3 board

In this section, we downloaded the design made in the

software part to the Spartan 3 board.