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AM29F100
AM29F100
AM29F100
Am29F100
1 Megabit (128 K x 8-bit/64 K x 16-bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation Embedded Algorithms
5.0 V 10% for read, erase, and program operations Embedded Erase algorithm automatically
Simplifies system-level power requirements pre-programs and erases the chip or any
combination of designated sector
High performance
Embedded Program algorithm automatically
70 ns maximum access time
programs and verifies data at specified address
Low power consumption
Minimum 100,000 program/erase cycles guaranteed
20 mA typical active read current for byte mode
20-year data retention at 125C
28 mA typical active read current for word mode
Reliable operation for the life of the system
30 mA typical program/erase current
Package options
25 A typical standby current
44-pin SO
Flexible sector architecture 48-pin TSOP
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
Compatible with JEDEC standards
one 64 Kbyte sectors (byte mode)
Pinout and software compatible with
One 8 Kword, two 4 Kword, one 16 Kword, and
single-power-supply flash
one 32 Kword sectors (word mode)
Superior inadvertent write protection
Any combination of sectors can be erased
Supports full chip erase Data# Polling and Toggle Bits
Provides a software method of detecting program
Top or bottom boot block configurations available
or erase cycle completion
Sector protection
Ready/Busy pin (RY/BY#)
Hardware-based feature that disables/re-enables
program and erase operations in any Provides a hardware method for detecting
combination of sectors program or erase cycle completion
Sector protection/unprotection can be Erase Suspend/Erase Resume
implemented using standard PROM Suspends an erase operation to read data from,
programming equipment or program data to, a sector that is not being
Temporary Sector Unprotect feature allows in- erased, then resumes the erase operation
system code changes in protected sectors
Hardware RESET# pin
Hardware method of resetting the device to
reading array data
Am29F100 2
PRODUCT SELECTOR GUIDE
Family Part Number Am29F100
BLOCK DIAGRAM
DQ0DQ15
RY/BY# RY/BY#
Buffer
VCC
Erase Voltage Input/Output
VSS Generator Buffers
WE# State
Control
BYTE#
Command
RESET# Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#
Y-Decoder Y-Gating
STB
Address Latch
A0A15
A-1
18926D-1
3 Am29F100
CONNECTION DIAGRAMS
A15 1 48 NC
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 37 VCC
NC 13 Standard TSOP 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
NC 16 33 DQ2
NC 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0
18926D-2
NC 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 NC
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 37 RESET#
DQ11 13 Reverse TSOP 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 NC
DQ9 17 32 NC
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1
18926D-3
Am29F100 4
CONNECTION DIAGRAMS
NC 1 44 RESET#
RY/BY# 2 43 WE#
NC 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 NC
CE# 12 SO 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC
18926D-4
5 Am29F100
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
AM29F100 T -70 E C B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
(Contact an AMD representative for more information.)
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package
(SO 044)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F100
1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
AM29F100T-150,
AM29F100B-150
Am29F100 6
DEVICE BUS OPERATIONS
This section describes the requirements and use of the of the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. The appropriate device bus operations
self does not occupy any addressable memor y table lists the inputs and control levels required, and the
location. The register is composed of latches that store resulting output. The following subsections describe
the commands, along with the address and data infor- each of these operations in further detail.
mation needed to execute the command. The contents
Temporary Sector
X X X VID AIN DIN DIN High-Z
Unprotect
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A15:A0 in word mode (BYTE# = VIH), A15:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the Sector Pro-
tection/Unprotection section.
7 Am29F100
An erase operation can erase one sector, multiple sec- If the device is deselected during erasure or program-
tors, or the entire device. The Sector Address Tables ming, the device draws active current until the
indicate the address space that each sector occupies. operation is completed.
A sector address consists of the address bits required
In the DC Characteristics tables, ICC3 represents the
to uniquely select a sector. See the Command Defini-
standby current specification.
tions section for details on erasing a sector or the
entire chip, or suspendi ng/res uming the eras e
RESET#: Hardware Reset Pin
operation.
The RESET# pin provides a hardware method of reset-
After the system writes the autoselect command se- ting the device to reading array data. When the system
quence, the device enters the autoselect mode. The drives the RESET# pin low for at least a period of tRP,
system can then read autoselect codes from the inter- the device immediately terminates any operation in
nal register (which is separate from the memory array) progress, tristates all data output pins, and ignores all
on DQ7DQ0. Standard read cycle timings apply in this read/write attempts for the duration of the RESET#
mode. Refer to the Autoselect Mode and Autoselect pulse. The device also resets the internal state ma-
Command Sequence sections for more information. chine to reading array data. The operation that was
ICC2 in the DC Characteristics table represents the ac- interrupted should be reinitiated once the device is
tive current specification for the write mode. The AC ready to accept another command sequence, to en-
Characteristics section contains timing specification sure data integrity.
tables and timing diagrams for write operations. Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
Program and Erase Operation Status the TTL standby mode; if RESET# is held at V SS
During an erase or program operation, the system may 0.5 V, the device enters the CMOS standby mode.
check the status of the operation by reading the status
The RESET# pin may be tied to the system reset cir-
bits on DQ7DQ0. Standard read cycle timings and I CC
cuitry. A system reset would thus also reset the Flash
read specifications apply. Refer to Write Operation
memory, enabling the system to read the boot-up firm-
Status for more information, and to each AC Charac-
ware from the Flash memory.
teristics section for timing diagrams.
If RESET# is asserted during a program or erase oper-
Standby Mode ation, the RY/BY# pin remains a 0 (busy) until the
When the system is not reading or writing to the device, internal reset operation is complete, which requires a
it can place the device in the standby mode. In this time of t READY (during Embedded Algorithms). The
mode, current consumption is greatly reduced, and the system can thus monitor RY/BY# to determine whether
outputs are placed in the high impedance state, inde- the reset operation is complete. If RESET# is asserted
pendent of the OE# input. when a program or erase operation is not executing
(RY/BY# pin is 1), the reset operation is completed
The device enters the CMOS standby mode when CE# within a time of t READY (not during Embedded Algo-
and RESET# pins are both held at V CC 0.5 V. (Note rithms). The system can read data t RH after the
that this is a more restricted voltage range than VIH.) RESET# pin returns to V IH.
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re- Refer to the AC Characteristics tables for RESET# pa-
quires standard access time (tCE) for read access when rameters and timing diagram.
the device is in either of these standby modes, before it
is ready to read data. Output Disable Mode
When the OE# input is at VIH, output from the device is
The device also enters the standby mode when the RE-
disabled. The output pins are placed in the high imped-
SET# pin is driven low. Refer to the next section,
ance state.
RESET#: Hardware Reset Pin.
Am29F100 8
Table 2. Sector Addresses Tables (Am29F100T)
A15 A14 A13 A12 (x8) Address Range (x16) Address Range
Autoselect Mode
The autoselect mode provides manufacturer and de- address must appear on the appropriate highest order
vice identification, and sector protection verification, address bits. Refer to the corresponding Sector Ad-
through identifier codes output on DQ7DQ0. This dress Tables. The Command Definitions table shows
mode is primarily intended for programming equipment the remaining address bits that are dont care. When all
to automatically match a device to be programmed with necessary bits have been set as required, the program-
its corresponding programming algorithm. However, ming equipment may then read the corresponding
the autoselect codes can also be accessed in-system identifier code on DQ7DQ0.
through the command register.
To access the autoselect codes in-system, the host
When using programming equipment, the autoselect system can issue the autoselect command via the
mode requires V ID (11.5 V to 12.5 V) on address pin command register, as shown in the Command Defini-
A9. Address pins A6, A1, and A0 must be as shown in tions table. This method does not require VID. See
Autoselect Codes (High Voltage Method) table. In addi- Command Definitions for details on using the autose-
tion, when verifying sector protection, the sector lect mode.
9 Am29F100
Table 4. Am29F100 Autoselect Codes (High Voltage Method)
A15 A11 A8 A5 DQ8 DQ7
to to to to to to
Description Mode CE# OE# WE# A12 A10 A9 A7 A6 A2 A1 A0 DQ15 DQ0
01h
X
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
X
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care
Sector Protection/Unprotection protected again. Figure 1 shows the algorithm, and the
Temporary Sector Unprotect (Figure 15) diagram
The hardware sector protection feature disables both
shows the timing waveforms, for this feature.
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. START
Am29F100 10
Hardware Data Protection proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection Write Pulse Glitch Protection
against inadvertent writes (refer to the Command Defi- Noise pulses of less than 5 ns (typical) on OE#, CE# or
nitions table). In addition, the following hardware data WE# do not initiate a write cycle.
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by Logical Inhibit
spurious system level signals during V CC power-up and Write cycles are inhibited by holding any one of OE# =
power-down transitions, or from system noise. VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
Low V CC Write Inhibit CE# and WE# must be a logical zero while OE# is a
logical one.
When V CC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC Power-Up Write Inhibit
power-up and power-down. The command register and If WE# = CE# = V IL and OE# = VIH during power up, the
all internal program/erase circuits are disabled, and the device does not accept commands on the rising edge
device resets. Subsequent writes are ignored until V CC of WE#. The internal state machine is automatically
is greater than V LKO. The system must provide the reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se- The Read Operations table provides the read parame-
quences into the command register initiates device ters, and Read Operation Timings diagram shows the
operations. The Command Definitions table defines the timing diagram.
valid register command sequences. Writing incorrect
address and data values or writing them in the im- Reset Command
proper sequence resets the device to reading array Writing the reset command to the device resets the de-
data. vice to reading array data. Address bits are dont care
All addresses are latched on the falling edge of WE# or for this command.
CE#, whichever happens later. All data is latched on The reset command may be written between the se-
the rising edge of WE# or CE#, whichever happens quence cycles in an erase command sequence before
first. Refer to the appropriate timing diagrams in the erasing begins. This resets the device to reading array
AC Characteristics section. data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
Reading Array Data
The reset command may be written between the se-
The device is automatically set to reading array data
quence cycles in a program command sequence
after device power-up. No commands are required to
before programming begins. This resets the device to
retrieve data. The device is also ready to read array
reading array data (also applies to programming in
data after completing an Embedded Program or Em-
Erase Suspend mode). Once programming begins,
bedded Erase algorithm.
however, the device ignores reset commands until the
After the device accepts an Erase Suspend command, operation is complete.
the device enters the Erase Suspend mode. The sys-
The reset command may be written between the se-
tem can read array data using the standard read
quence cycles in an autoselect command sequence.
timings, except that if it reads at an address within
Once in the autoselect mode, the reset command must
erase-suspended sectors, the device outputs status
be written to return to reading array data (also applies
data. After completing a programming operation in the
to autoselect during Erase Suspend).
Erase Suspend mode, the system may once again
read array data with the same exception. See Erase If DQ5 goes high during a program or erase operation,
Suspend/Erase Resume Commands for more infor- writing the reset command returns the device to read-
mation on this mode. ing array data (also applies during Erase Suspend).
The system must issue the reset command to re-en-
Autoselect Command Sequence
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the Reset Com- The autoselect command sequence allows the host
mand section, next. system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
See also Requirements for Reading Array Data in the The Command Definitions table shows the address
Device Bus Operations section for more information. and data requirements. This method is an alternative to
11 Am29F100
that shown in the Autoselect Codes (High Voltage should be reinitiated once the device has reset to read-
Method) table, which is intended for PROM program- ing array data, to ensure data integrity.
mers and requires VID on address bit A9.
Programming is allowed in any sequence and across
The autoselect command sequence is initiated by writ- sector boundaries. A bit cannot be programmed
ing two unlock cycles, followed by the autoselect from a 0 back to a 1. Attempting to do so may halt
command. The device then enters the autoselect the operation and set DQ5 to 1, or cause the Data#
mode, and the system may read at any address any Polling algorithm to indicate the operation was suc-
number of times, without initiating another command cessful. However, a succeeding read will show that the
sequence. data is still 0. Only erase operations can convert a 0
to a 1.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A
read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re- START
turns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for
valid sector addresses.
Write Program
The system must write the reset command to exit the Command Sequence
autoselect mode and return to reading array data.
Am29F100 12
Chip Erase Command Sequence mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
Chip erase is a six-bus-cycle operation. The chip erase
terrupts can be re-enabled after the last Sector Erase
command sequence is initiated by writing two unlock
command is written. If the time between additional sec-
cycles, followed by a set-up command. Two additional
tor erase commands can be assumed to be less than
unlock write cycles are then followed by the chip erase
50 s, the system need not monitor DQ3. Any com-
command, which in turn invokes the Embedded Erase
mand other than Sector Erase or Erase Suspend
algorithm. The device does not require the system to
during the time-out period resets the device to
preprogram prior to erase. The Embedded Erase algo-
reading array data. The system must rewrite the com-
rithm automatically preprograms and verifies the entire
mand sequence and any additional sector addresses
memory for an all zero data pattern prior to electrical
and commands.
erase. The system is not required to provide any con-
trols or timings during these operations. The Command The system can monitor DQ3 to determine if the sector
Definitions table shows the address and data require- erase timer has timed out. (See the DQ3: Sector Erase
ments for the chip erase command sequence. Timer section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware Once the sector erase operation has begun, only the
reset during the chip erase operation immediately ter- Erase Suspend command is valid. All other commands
minates the operation. The Chip Erase command are ignored. Note that a hardware reset during the
sequence should be reinitiated once the device has re- sector erase operation immediately terminates the op-
turned to reading array data, to ensure data integrity. eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
The system can determine the status of the erase op-
array data, to ensure data integrity.
eration by using DQ7, DQ6, or RY/BY#. See Write
Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are
device returns to reading array data and addresses are no longer latched. The system can determine the sta-
no longer latched. tus of the erase operation by using DQ7, DQ6, or RY/
BY#. Refer to Write Operation Status for information
Figure 3 illustrates the algorithm for the erase opera-
on these status bits.
tion. See the Erase/Program Operations tables in AC
Characteristics for parameters, and to the Chip/Sector Figure 3 illustrates the algorithm for the erase opera-
Erase Operation Timings for timing waveforms. tion. Refer to the Erase/Program Operations tables in
the AC Characteristics section for parameters, and to
Sector Erase Command Sequence the Sector Erase Operations Timing diagram for timing
Sector erase is a six bus cycle operation. The sector waveforms.
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two Erase Suspend/Erase Resume Commands
additional unlock write cycles are then followed by the The Erase Suspend command allows the system to in-
address of the sector to be erased, and the sector terrupt a sector erase operation and then read data
erase command. The Command Definitions table from, or program data to, any sector not selected for
shows the address and data requirements for the sec- erasure. This command is valid only during the sector
tor erase command sequence. erase operation, including the 50 s time-out period
during the sector erase command sequence. The
The device does not require the system to preprogram
Erase Suspend command is ignored if written during
the memory prior to erase. The Embedded Erase algo-
the chip erase operation or Embedded Program algo-
rithm automatically programs and verifies the sector for
rithm. Writing the Erase Suspend command during the
an all zero data pattern prior to electrical erase. The
Sector Erase time-out immediately terminates the
system is not required to provide any controls or tim-
time-out period and suspends the erase operation. Ad-
ings during these operations.
dresses are dont-cares when writing the Erase
After the command sequence is written, a sector erase Suspend command.
time-out of 50 s begins. During the time-out period,
When the Erase Suspend command is written during a
additional sector addresses and sector erase com-
sector erase operation, the device requires a maximum
mands may be written. Loading the sector erase buffer
of 20 s to suspend the erase operation. However,
may be done in any sequence, and the number of sec-
when the Erase Suspend command is written during
tors may be from one sector to all sectors. The time
the sector erase time-out, the device immediately ter-
between these additional cycles must be less than 50
minates the time-out period and suspends the erase
s, otherwise the last address and command might not
operation.
be accepted, and erasure may begin. It is recom-
13 Am29F100
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device erase
suspends all sectors selected for erasure.) Normal START
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7 to determine if a sector is actively erasing Write Erase
or is erase-suspended. See Write Operation Status Command Sequence
for information on these status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within Data Poll
non-suspended sectors. The system can determine from System
the status of the program operation using the DQ7 or Embedded
DQ6 status bits, just as in the standard program oper- Erase
ati on. S ee Wr i te Ope rati on Status for more algorithm
in progress
information. No
Data = FFh?
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes Yes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
Erasure Completed
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
18926D-8
valid operation. See Autoselect Command Sequence
for more information. Notes:
The system must write the Erase Resume command 1. See the appropriate Command Definitions table for erase
(address bits are dont care) to exit the erase suspend command sequence.
mode and continue the sector erase operation. Further 2. See DQ3: Sector Erase Timer for more information.
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de- Figure 3. Erase Operation
vice has resumed erasing.
Am29F100 14
Table 5. Am29F100 Command Definitions
Bus Cycles (Notes 24)
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXXX F0
Word 5555 2AAA 5555
Manufacturer ID 4 AA 55 90 XX00 01
Byte AAAA 5555 AAAA
Autoselect (Note 7)
Legend:
X = Dont care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A15A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 7. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read operation.
3. Except when reading array or autoselect data, all bus cycles 8. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See Autoselect Command Sequence for
more information.
4. Data bits DQ15DQ8 are dont cares for unlock and
command cycles. 9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. No unlock or command cycles required when reading array mode. The Erase Suspend command is valid only during a
data. sector erase operation.
6. The Reset command is required to return to reading array 10. The Erase Resume command is valid only during the Erase
data when device is in the autoselect mode, or if DQ5 goes Suspend mode.
high (while the device is providing status data).
15 Am29F100
WRITE OPERATION STATUS
The device provides several bits to determine the sta- Table 6 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ3, DQ5, DQ6, DQ7, and Figure 4 shows the Data# Polling algorithm.
RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress. START
These three bits are discussed first.
Am29F100 16
RY/BY#: Ready/Busy# system would note and store the value of the toggle bit
after the first read. After the second read, the system
The RY/BY# is a dedicated, open-drain output pin that
would compare the new value of the toggle bit with the
indicates whether an Embedded Algorithm is in
first. If the toggle bit is not toggling, the device has com-
progress or complete. The RY/BY# status is valid after
pleted the program or erase operation. The system can
the rising edge of the final WE# pulse in the command
read array data on DQ7DQ0 on the following read
sequence. Since RY/BY# is an open-drain output, sev-
cycle.
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
If the output is low (Busy), the device is actively erasing
tem also should note whether the value of DQ5 is high
or programming. (This includes programming in the
(see the section on DQ5). If it is, the system should
Erase Suspend mode.) If the output is high (Ready),
then determine again whether the toggle bit is toggling,
the device is ready to read array data (including during
since the toggle bit may have stopped toggling just as
the Erase Suspend mode), or is in the standby mode.
DQ5 went high. If the toggle bit is no longer toggling,
Table 6 shows the outputs for RY/BY#. The timing dia- the device has successfully completed the program or
grams for read, reset, program, and erase shows the erase operation. If it is still toggling, the device did not
relationship of RY/BY# to other signals. complete the operation successfully, and the system
must write the reset command to return to reading
DQ6: Toggle Bit I array data.
Toggle Bit I on DQ6 indicates whether an Embedded The remaining scenario is that the system initially de-
Program or Erase algorithm is in progress or complete, termines that the toggle bit is toggling and DQ5 has not
or whether the device has entered the Erase Suspend gone high. The system may continue to monitor the
mode. Toggle Bit I may be read at any address, and is toggle bit and DQ5 through successive read cycles, de-
valid after the rising edge of the final WE# pulse in the termining the status as described in the previous
command sequence (prior to the program or erase op- paragraph. Alternatively, it may choose to perform
eration), and during the sector erase time-out. other system tasks. In this case, the system must start
During an Embedded Program or Erase algorithm op- at the beginning of the algorithm when it returns to de-
eration, successive read cycles to any address cause termine the status of the operation (top of Figure 5).
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is DQ5: Exceeded Timing Limits
complete, DQ6 stops toggling. DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
After an erase command sequence is written, if all sec-
these conditions DQ5 produces a 1. This is a failure
tors selected for erasing are protected, DQ6 toggles for
condition that indicates the program or erase cycle was
approximately 100 s, then returns to reading array
not successfully completed.
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected The DQ5 failure condition may appear if the system
sectors, and ignores the selected sectors that are tries to program a 1 to a location that is previously pro-
protected. grammed to 0. Only an erase operation can change
a 0 back to a 1. Under this condition, the device
If a program address falls within a protected sector,
halts the operation, and when the operation has ex-
DQ6 toggles for approximately 2 s after the program
ceeded the timing limits, DQ5 produces a 1.
command sequence is written, then returns to reading
array data. Under both these conditions, the system must issue the
reset command to return the device to reading array
DQ6 also toggles during the erase-suspend-program
data.
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
DQ3: Sector Erase Timer
The Write Operation Status table shows the outputs for After writing a sector erase command sequence, the
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit system may read DQ3 to determine whether or not an
algorithm, and to the Toggle Bit Timings figure in the erase operation has begun. (The sector erase timer
AC Characteristics section for the timing diagram. does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
Reading Toggle Bit DQ6 out also applies after each additional sector erase com-
Refer to Figure 5 for the following discussion. When- mand. When the time-out is complete, DQ3 switches
ever the system initially begins reading toggle bit from 0 to 1. The system may ignore DQ3 if the sys-
status, it must read DQ7DQ0 at least twice in a row to tem can guarantee that the time between additional
determine whether a toggle bit is toggling. Typically, a sector erase commands will always be less than 50 s.
17 Am29F100
See also the Sector Erase Command Sequence
section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll- START
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is 1, the internally controlled erase cycle has
Read DQ7DQ0
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is 0, the device will accept additional sector
erase commands. To ensure the command has been Read DQ7DQ0 1
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3. Toggle Bit No
= Toggle?
Yes
No
DQ5 = 1?
Yes
Toggle Bit No
= Toggle?
Yes
Program/Erase
Operation Not Program/Erase
Complete, Write Operation Complete
Reset Command
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
18926D-10
Am29F100 18
Table 6. Write Operation Status
DQ7 DQ5
Operation (Note 1) DQ6 (Note 2) DQ3 RY/BY#
Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits for more information.
19 Am29F100
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES
Storage Temperature Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . 65C to +125C Case Temperature (TA) . . . . . . . . . . . . . .0C to +70C
Ambient Temperature Industrial (I) Devices
with Power Applied. . . . . . . . . . . . . . 55C to +125C
Case Temperature (TA) . . . . . . . . . . . .40C to +85C
Voltage with Respect to Ground
VCC (Note 1). . . . . . . . . . . . . . . . . . . .2.0 V to +7.0 V Extended (E) Devices
Output Short Circuit Current (Note 3) . . . . . . 200 mA VCC for 5% devices . . . . . . . . . . . +4.75 V to +5.25 V
Notes: VCC for 10% devices . . . . . . . . . . +4.50 V to +5.50 V
1. Minimum DC voltage on input or I/O pin is 0.5 V. During Operating ranges define those limits between which the
voltage transitions, inputs may overshoot VSS to 2.0 V functionality of the device is guaranteed.
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on input and I/O pins is VCC + 0.5 V. During volt-
age transitions, input and I/O pins may overshoot to VCC
+ 2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on A9 pin is 0.5V. During
voltage transitions, A9 pins may overshoot VSS to 2.0 V
for periods of up to 20 ns. See Figure 6. Maximum DC in-
put voltage on A9 is +12.5 V which may overshoot to 13.5
V for periods up to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
20 ns
20 ns 20 ns
VCC
+0.8 V +2.0 V
VCC
0.5 V +0.5 V
2.0 V 2.0 V
20 ns 20 ns 20 ns
18926D-11 18926D-12
Am29F100 20
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max 1.0 A
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max 1.0 A
Byte 40 mA
ICC1 VCC Active Current (Notes 1, 2) CE# = VIL, OE# = VIH
Word 50 mA
ICC3 VCC Standby Current (Note 2) CE# = VIH, OE# = VIH 1.0 mA
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
VOH Output High Voltage IOH = 2.5 mA, VCC = VCC Min 2.4 V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
21 Am29F100
DC CHARACTERISTICS (continued)
CMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max 1.0 A
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max 1.0 A
Byte 40
ICC1 VCC Active Current (Notes 1, 2) CE# = VIL, OE# = VIH mA
Word 50
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
Am29F100 22
TEST CONDITIONS
Table 7. Test Specifications
5.0 V
All
Test Condition -70 others Unit
2.7 k
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 k
Input Rise and Fall Times 5 20 ns
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
23 Am29F100
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbol Speed Options
JEDEC Std Parameter Description Test Setup -70 -90 -120 -150 Unit
CE# = VIL
tAVQV tACC Address to Output Delay Max 70 90 120 150 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 150 ns
Read Min 0 ns
tOEH Output Enable Hold Time (Note 1) Toggle and Data
Min 10 ns
Polling
Notes:
1. Not 100% tested.
2. Output Driver Disable Time.
3. See Figure 8 and Table 7 for test specifications.
tRC
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
18926D-14
Figure 9. Read Operations Timings
Am29F100 24
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
18926D-15
Figure 10. RESET# Timings
25 Am29F100
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter Speed Options
CE#
OE#
BYTE#
tELFL
BYTE# DQ0DQ14 Data Output Data Output
Switching (DQ0DQ14) (DQ0DQ7)
from word
to byte
mode DQ15/A-1 DQ15 Address
Output Input
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte DQ0DQ14 Data Output Data Output
to word (DQ0DQ7) (DQ0DQ14)
mode
DQ15/A-1 Address DQ15
Input Output
tFHQV
18926D-16
Figure 11. BYTE# Timings for Read Operations
CE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
18926D-17
Figure 12. BYTE# Timings for Write Operations
Am29F100 26
AC CHARACTERISTICS
Erase and Program Operations
Parameter Symbol Speed Options
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
27 Am29F100
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
tGHWL
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
tBUSY tRB
RY/BY#
tVCS
VCC
18926D-18
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode
Am29F100 28
AC CHARACTERISTICS
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
tBUSY tRB
RY/BY#
tVCS
VCC
18926D-19
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data, (see Write Operation Status).
2. Illustration shows device in word mode.
29 Am29F100
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
18926D-20
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
18926D-21
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
Am29F100 30
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
12 V
RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
18926D-22
Figure 15. Temporary Sector Unprotect Timing Diagram
31 Am29F100
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Am29F100 32
AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
18926D-23
Figure 16. Alternate CE# Controlled Write Operation Timings
33 Am29F100
ERASE AND PROGRAMMING PERFORMANCE
Limits
Notes:
1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, VCC = 4.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTIC
Parameter Description Min Max
Input Voltage with respect to VSS on I/O pins 1.0 V VCC + 1.0 V
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Test Conditions Min Unit
150C 10 Years
Minimum Pattern Data Retention Time
125C 20 Years
Am29F100 34
PHYSICAL DIMENSIONS
SO 04444-Pin Small Outline Package (measured in millimeters)
44 23
13.10 15.70
13.50 16.30
1 22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17 0.10
2.80 0.21
2.45 MAX.
0
SEATING 8 0.60
0.35 0.10 PLANE 1.00
0.50 0.35
END VIEW
SIDE VIEW 16-038-SO44-2
SO 044
DF83
8-8-96 lv
35 Am29F100
PHYSICAL DIMENSIONS
TS 04848-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1 48
11.90
12.10
0.50 BSC
24 25
18.30 0.05
18.50 0.15
19.80
20.20
16-038-TS48-2
0.08 TS 048
1.20 0.20 DT95
MAX 8-8-96 lv
0.10
0.21
0
0.25MM (0.0098") BSC 5
0.50
0.70
Pin 1 I.D.
1 48
11.90
12.10
0.50 BSC
24 25
18.30 0.05
18.50 0.15
16-038-TS48
TSR048
0.08 DT95
1.20 0.20 8-8-96 lv
MAX 0.10
0.21
0
0.25MM (0.0098") BSC 5
0.50
0.70
Am29F100 36
REVISION SUMMARY
Revision D DC CharacteristicsCMOS Compatible
Distinctive Characteristics I CC1 , ICC2, I CC3: Deleted V CC = V CCMax; added
Note 2 Maximum ICC specifications are tested with
Added:
VCC = VCCmax.
20-year data retention at 125C
Reliable operation for the life of the system
DC CharacteristicsTTL/NMOS Compatible
ICC1, ICC2, ICC3: Deleted VCC = VCCMax; added Note 2
Maximum ICC specifications are tested with
VCC = VCCmax.
37 Am29F100