Hi3520 PDF

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Hi3520 H.264
02
2010-01-19
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518129
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20092010

Hi3520

About This Document.....................................................................................................................1

1 Product Description...................................................................................................................1-1
1.1 System Architecture ....................................................................................................................................1-1
1.1.1 Overview ...........................................................................................................................................1-1
1.1.2 Processor System...............................................................................................................................1-2
1.1.3 Graphics Processing ..........................................................................................................................1-2
1.1.4 Video Encoding and Decoding..........................................................................................................1-3
1.1.5 Encryption/Decryption Engine..........................................................................................................1-3
1.1.6 Memory Controller Interface.............................................................................................................1-3
1.1.7 Ethernet Interface ..............................................................................................................................1-4
1.1.8 Video Interface ..................................................................................................................................1-4
1.1.9 Audio Interface..................................................................................................................................1-4
1.1.10 MMC/SD/SDIO Controller .............................................................................................................1-5
1.1.11 PCI Interface....................................................................................................................................1-5
1.1.12 USB Interface..................................................................................................................................1-5
1.1.13 Other Peripheral Interface ...............................................................................................................1-5
1.1.14 Hardware Feature ............................................................................................................................1-6
1.2 Application Scenario ...................................................................................................................................1-6
2 Hardware .....................................................................................................................................2-1
2.1 Pin Description ............................................................................................................................................2-1
2.1.1 Power Pins.........................................................................................................................................2-2
2.1.2 SIO Pins ..........................................................................................................................................2-21
2.1.3 VDAC Pins......................................................................................................................................2-23
2.1.4 DDRA Pins......................................................................................................................................2-25
2.1.5 DDRB Pins......................................................................................................................................2-30
2.1.6 EBI Pins ..........................................................................................................................................2-33
2.1.7 GMAC Pins .....................................................................................................................................2-36
2.1.8 VO Pins ...........................................................................................................................................2-37
2.1.9 PCI Pins...........................................................................................................................................2-39
2.1.10 SYS Pins........................................................................................................................................2-43
2.1.11 I2C Pins ..........................................................................................................................................2-44

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2.1.12 JTAG Pins .....................................................................................................................................2-44

2.1.13 UART Pins ....................................................................................................................................2-44
2.1.14 USB Pins .......................................................................................................................................2-45
2.1.15 VI Pins...........................................................................................................................................2-46
2.2 Description of the Software Multiplexing Pins .........................................................................................2-48
2.2.1 VI Pin Multiplexing.........................................................................................................................2-48
2.2.2 VO Pin Multiplexing .......................................................................................................................2-52
2.2.3 I2C Pin Multiplexing.......................................................................................................................2-56
2.2.4 SIO Pin Multiplexing ......................................................................................................................2-56
2.2.5 EBI Pin Multiplexing ......................................................................................................................2-57
2.2.6 GMAC Pin Multiplexing.................................................................................................................2-57
2.2.7 PCI Pin Multiplexing ......................................................................................................................2-58
2.3 Description of Hardware Multiplexing Pins..............................................................................................2-59
2.3.1 EBI Pin Multiplexing ......................................................................................................................2-59
2.3.2 PCI Pin Multiplexing ......................................................................................................................2-62
2.4 Summary of IO Config Registers ..............................................................................................................2-63
2.5 Description of the IO Config Registers .....................................................................................................2-67
2.6 Recommended Sequence of Power-On and Power-Off...........................................................................2-108
2.7 External Interrupts...................................................................................................................................2-109
2.8 Electrical Specifications ..........................................................................................................................2-109
2.8.1 DC/AC Parameters ........................................................................................................................2-109
2.8.2 Recommended Operating Conditions............................................................................................ 2-110
2.9 PCB Routing Recommendations ............................................................................................................. 2-111
2.10 Timing Parameters................................................................................................................................. 2-111
2.10.1 Primitives of Timing Diagrams ................................................................................................... 2-111
2.10.2 Timings of the DDR2 Interface ................................................................................................... 2-111
2.10.3 Timing of the GMAC Interface ................................................................................................... 2-114
2.10.4 Timing of the VI Interface........................................................................................................... 2-119
2.10.5 Timing of the VO Interface ......................................................................................................... 2-119
2.10.6 Timings of the PCI Interface .......................................................................................................2-120
2.10.7 Timing of the I2C Interface ..........................................................................................................2-121
2.10.8 Timing of the MMC Interface .....................................................................................................2-122
2.10.9 Timing of the SSP Interface.........................................................................................................2-123
2.10.10 Timing of the UART Interface...................................................................................................2-125
2.10.11 Timings of SIO Interfaces..........................................................................................................2-126
2.10.12 Timing of the SMI Interface ......................................................................................................2-128
2.11 Package and Pinout................................................................................................................................2-128
2.11.1 Package........................................................................................................................................2-128
2.11.2 Pinout ..........................................................................................................................................2-131
2.11.3 Pin Arrangement Table ................................................................................................................2-136
3 System ..........................................................................................................................................3-1

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3.1 Reset ............................................................................................................................................................3-1

3.1.1 Overview ...........................................................................................................................................3-1
3.1.2 Reset Signal Control..........................................................................................................................3-1
3.1.3 Reset Configuration...........................................................................................................................3-2
3.2 Clock ...........................................................................................................................................................3-3
3.2.1 Overview ...........................................................................................................................................3-3
3.2.2 Clock Control ....................................................................................................................................3-3
3.2.3 Clock Configuration..........................................................................................................................3-5
3.3 Processor and Address Space Mapping of the Memory ............................................................................3-16
3.3.1 Processor .........................................................................................................................................3-16
3.3.2 Address Space Mapping of the Memory .........................................................................................3-17
3.4 Interrupt System ........................................................................................................................................3-30
3.4.1 Overview .........................................................................................................................................3-30
3.4.2 Features ...........................................................................................................................................3-30
3.4.3 Function Description .......................................................................................................................3-30
3.4.4 Register Summary ...........................................................................................................................3-34
3.4.5 Register Description........................................................................................................................3-35
3.5 Direct Memory Access Controller.............................................................................................................3-40
3.5.1 Overview .........................................................................................................................................3-40
3.5.2 Features ...........................................................................................................................................3-40
3.5.4 Operating Mode...............................................................................................................................3-44
3.6 CIPHER.....................................................................................................................................................3-67
3.6.1 Overview .........................................................................................................................................3-67
3.6.2 Features ...........................................................................................................................................3-67
3.6.4 Operating Mode...............................................................................................................................3-78
3.7 Timer .........................................................................................................................................................3-95
3.7.1 Overview .........................................................................................................................................3-95
3.7.2 Features ...........................................................................................................................................3-96
3.7.4 Operating Mode...............................................................................................................................3-97
3.8 Watchdog.................................................................................................................................................3-107
3.8.1 Overview .......................................................................................................................................3-107
3.8.2 Features .........................................................................................................................................3-107
3.8.3 Signal Description .........................................................................................................................3-108

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3.8.4 Function Description .....................................................................................................................3-108

3.8.5 Operating Mode.............................................................................................................................3-109
3.8.6 Register Summary ......................................................................................................................... 3-110
3.8.7 Register Description...................................................................................................................... 3-111
3.9 Real Time Clock...................................................................................................................................... 3-115
3.9.1 Overview ....................................................................................................................................... 3-115
3.9.2 Features ......................................................................................................................................... 3-115
3.9.3 Function Description ..................................................................................................................... 3-115
3.9.4 Operating Mode............................................................................................................................. 3-115
3.9.6 Regitsr Description........................................................................................................................ 3-117
3.10 System Controller..................................................................................................................................3-121
3.10.1 Overview .....................................................................................................................................3-121
3.10.2 Features .......................................................................................................................................3-121
3.10.3 Function Description ...................................................................................................................3-121
3.10.4 Register Summary .......................................................................................................................3-127
3.10.5 Register Description ....................................................................................................................3-129
3.11 Power Management and Low-Power Mode Control .............................................................................3-173
3.11.1 Overview .....................................................................................................................................3-173
3.11.2 System Operating Modes ............................................................................................................3-174
3.11.3 Clock Gating and Clock Frequency Adjustment .........................................................................3-174
3.11.4 DDR Low-Power Contorl............................................................................................................3-175
4 Memory Controller ....................................................................................................................4-1

4.1 DDR Controller ...........................................................................................................................................4-1
4.1.1 Overview ...........................................................................................................................................4-1
4.1.2 Features .............................................................................................................................................4-1
4.1.3 Signal Description .............................................................................................................................4-1
4.1.4 Function Description .........................................................................................................................4-4
4.1.5 Operating Mode...............................................................................................................................4-12
4.2 SMI Controller ..........................................................................................................................................4-29
4.2.1 Overview .........................................................................................................................................4-29
4.2.2 Features ...........................................................................................................................................4-29
4.2.3 Signal Description ...........................................................................................................................4-30
4.2.5 Operating Mode...............................................................................................................................4-35
4.3 NAND Flash Controller ............................................................................................................................4-52
4.3.1 Overview .........................................................................................................................................4-52

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4.3.2 Features ...........................................................................................................................................4-52

4.3.3 Description of NANDC Interfaces ..................................................................................................4-53
4.3.5 Operating Modes .............................................................................................................................4-56
5 GMAC ..........................................................................................................................................5-1
5.1 Overview .....................................................................................................................................................5-1
5.2 Feature.........................................................................................................................................................5-1
5.3 Signal Description .......................................................................................................................................5-2
5.4 Function Description ...................................................................................................................................5-3
5.4.1 Typical Application ...........................................................................................................................5-3
5.4.2 Frame Format ....................................................................................................................................5-4
5.4.3 Uplink and Downlink Frame Management .......................................................................................5-4
5.4.4 Flow Control of the GMAC ..............................................................................................................5-7
5.4.5 Packet Receive Interrupt Management..............................................................................................5-7
5.4.6 Packet Filtering .................................................................................................................................5-7
5.5 Operating Mode...........................................................................................................................................5-7
5.5.1 Reading and Writing the PHY...........................................................................................................5-7
5.5.2 Transmitting and Receiving Packets .................................................................................................5-7
5.6 GMAC Register Summary ..........................................................................................................................5-7
5.7 Register Description ....................................................................................................................................5-7
6 Video Interface ...........................................................................................................................6-1

6.1 VIU..............................................................................................................................................................6-1
6.1.1 Overview ...........................................................................................................................................6-1
6.1.2 Features .............................................................................................................................................6-1
6.1.3 Signal Description .............................................................................................................................6-2
6.1.4 Function Description .........................................................................................................................6-4
6.1.5 Operating Mode...............................................................................................................................6-20
6.2 VOU ..........................................................................................................................................................6-75
6.2.1 Overview .........................................................................................................................................6-75
6.2.2 Features ...........................................................................................................................................6-75
6.2.3 Signal Description ...........................................................................................................................6-77
6.2.5 Operating Mode...............................................................................................................................6-84
6.2.7 Register Description......................................................................................................................6-105
7 Audio Interface...........................................................................................................................7-1
7.1 Overview .....................................................................................................................................................7-1

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7.2 Features .......................................................................................................................................................7-1

7.2.1 Features of the PCM Interface...........................................................................................................7-1
7.2.2 Features of the I2S Interface ..............................................................................................................7-1
7.5 Operating Mode...........................................................................................................................................7-8
7.6 Register Summary ..................................................................................................................................... 7-11
7.7 Register Description ..................................................................................................................................7-13
8 MMC/SD/SDIO Controller ......................................................................................................8-1

8.1 Overview .....................................................................................................................................................8-1
8.2 Features .......................................................................................................................................................8-1
8.5 Operating Mode...........................................................................................................................................8-8
8.5.1 Pin Multiplexing................................................................................................................................8-8
8.5.2 Clock Gating .....................................................................................................................................8-8
8.5.3 Soft Reset ..........................................................................................................................................8-8
8.6 Register Summary .....................................................................................................................................8-18
9 PCI.................................................................................................................................................9-1
9.1 Overview .....................................................................................................................................................9-1
9.2 Features .......................................................................................................................................................9-1
9.5 Operating Mode...........................................................................................................................................9-6
9.5.1 Pin Multiplexing................................................................................................................................9-6
9.5.2 Clock Gating .....................................................................................................................................9-7
9.5.3 Clock Configuration..........................................................................................................................9-7
9.5.4 Soft Reset ..........................................................................................................................................9-8
9.5.5 Configuring the Operating Mode ......................................................................................................9-8
9.5.6 Transmitting Data Through the Window ...........................................................................................9-8
9.5.7 Transmitting Data Through the DMA Channel .................................................................................9-9
9.6 Register Summary ..................................................................................................................................... 9-11
9.6.1 Registers at the AHB Side ............................................................................................................... 9-11
9.6.2 Registers for the Header Region of the PCI Configuration Space ..................................................9-12
9.7.1 Registers at the AHB Side ...............................................................................................................9-14
9.7.2 Registers in the PCI Configuration Space .......................................................................................9-29
10 USB 2.0 Host............................................................................................................................10-1

10.1 Overview .................................................................................................................................................10-1
10.2 Features ...................................................................................................................................................10-1

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10.3 Function Description ...............................................................................................................................10-1

10.4 Operating Mode.......................................................................................................................................10-3
10.4.1 Interface Signals............................................................................................................................10-3
10.4.2 Typical Application .......................................................................................................................10-4
10.4.3 Clock Gating .................................................................................................................................10-4
10.4.4 Soft Reset ......................................................................................................................................10-5
10.5 Register Summary ...................................................................................................................................10-5
10.6 Register Description ................................................................................................................................10-5
11 Other Peripheral Interfaces..................................................................................................11-1

11.1 I2C Interface............................................................................................................................................. 11-1
11.1.1 Overview ....................................................................................................................................... 11-1
11.1.2 Features ......................................................................................................................................... 11-1
11.1.3 Signal Description ......................................................................................................................... 11-1
11.1.4 Function Description ..................................................................................................................... 11-2
11.1.5 Operating Mode............................................................................................................................. 11-4
11.1.7 Register Descriptions..................................................................................................................... 11-9
11.2 UART .................................................................................................................................................... 11-31
T
11.2.1 Overview ..................................................................................................................................... 11-31

11.2.2 Features ....................................................................................................................................... 11-31
11.2.3 Signal Description ....................................................................................................................... 11-31
11.2.4 Function Description ................................................................................................................... 11-33
11.2.5 Operating Mode........................................................................................................................... 11-35
11.2.6 Register Summary ....................................................................................................................... 11-38
11.2.7 Register Description .................................................................................................................... 11-39
11.3 SPI ......................................................................................................................................................... 11-52
11.3.1 Overview ..................................................................................................................................... 11-52
11.3.2 Features ....................................................................................................................................... 11-52
11.3.5 Operating Mode........................................................................................................................... 11-62
11.4 IR ........................................................................................................................................................... 11-73
11.4.1 Overview ..................................................................................................................................... 11-73
11.4.2 Features ....................................................................................................................................... 11-73
11.4.5 Operating Mode........................................................................................................................... 11-82

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11.5 GPIO...................................................................................................................................................... 11-98

11.5.1 Overview ..................................................................................................................................... 11-98
11.5.2 Features ....................................................................................................................................... 11-98
11.5.4 Function Description ................................................................................................................. 11-103
11.5.5 Operating Mode......................................................................................................................... 11-103
11.5.6 Register Summary ..................................................................................................................... 11-107
11.5.7 Register Description .................................................................................................................. 11-108
12 Test Interface...........................................................................................................................12-1
12.1 Overview .................................................................................................................................................12-1
12.2 Operating Modes .....................................................................................................................................12-1
12.3 JTAG Debugging.....................................................................................................................................12-1
12.3.1 JTAG Interface Signals..................................................................................................................12-1
12.3.2 Debugging Mode...........................................................................................................................12-2
13 Video Processing Module.....................................................................................................13-1

13.1 Video Codec ............................................................................................................................................13-1
13.1.1 Overview .......................................................................................................................................13-1
13.1.2 Features .........................................................................................................................................13-1
13.2 TDE .........................................................................................................................................................13-2
13.2.1 Overview .......................................................................................................................................13-2
13.2.2 Features .........................................................................................................................................13-2
A Acronyms and Abbreviations............................................................................................... A-1

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Figure 1-1 Logic block diagram of the Hi3520 ................................................................................................1-1

Figure 1-2 Block diagram of the Hi3520 in a 16-channel CIF DVR................................................................1-7
Figure 1-3 Block diagram of the Hi3520 in a 4-channel D1 DVR ...................................................................1-8

Figure 1-4 Block diagram of the Hi3520 in an 8-channel D1 DVR .................................................................1-9
Figure 2-1 Primitives of timing diagrams..................................................................................................... 2-111
Figure 2-2 Write timing of dqs_out relative to dq_out, CKP, and CKN ....................................................... 2-112
Figure 2-3 Write timing of dqs_out relative to CK....................................................................................... 2-112
Figure 2-4 Write timing of cmd/addr relative to CK .................................................................................... 2-112
Figure 2-5 DDR2 SDRAM output timing .................................................................................................... 2-113

Figure 2-6 100 Mbit/s receive timing of the MII interface ........................................................................... 2-114
Figure 2-7 10 Mbit/s receive timing of the MII interface ............................................................................. 2-115
Figure 2-8 100 Mbit/s transmit timing of the MII interface ......................................................................... 2-115
Figure 2-9 10 Mbit/s transmit timing of the MII interface ........................................................................... 2-115
Figure 2-10 Receive timing of the RGMII interface .................................................................................... 2-116
Figure 2-11 Transmit timing of the RGMII interface ................................................................................... 2-116

Figure 2-12 Read timing of the MDIO interface .......................................................................................... 2-117
Figure 2-13 Write timing of the MDIO interface.......................................................................................... 2-117
Figure 2-14 Timing parameter diagram of the MDIO interface ................................................................... 2-118
Figure 2-15 Transmit timing of the MDIO interface .................................................................................... 2-118
Figure 2-16 Timing of the VI interface......................................................................................................... 2-119
Figure 2-17 Timing of the VO interface ....................................................................................................... 2-119
Figure 2-18 Timing of the VO concatenated input interface ........................................................................2-120
Figure 2-19 Timing of the PCI interface (using the inside clock of the Hi3520) .........................................2-120
Figure 2-20 Timing of the PCI interface (using the external clock of the Hi3520) ......................................2-121
Figure 2-21 Transfer timing of the I2C interface ..........................................................................................2-121
Figure 2-22 Timing of the MMC Interface...................................................................................................2-122

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Figure 2-23 SSP_SPICK clock timing of the SSP interface .........................................................................2-123

Figure 2-24 Timing of the SSP interface in master mode (sph = 0)..............................................................2-123
Figure 2-25 Timing of the SSP interface in master mode (sph = 1)..............................................................2-124
Figure 2-26 Timing of the UART interface ..................................................................................................2-126
Figure 2-27 Receive timing of the I2S interface ...........................................................................................2-127
Figure 2-28 Transmit timing of the I2S interface ..........................................................................................2-127
Figure 2-29 Receive timing of the PCM interface........................................................................................2-127
Figure 2-30 Transmit timing of the PCM interface ......................................................................................2-128
Figure 2-31 Package dimensions (top view).................................................................................................2-129
Figure 2-32 Package dimensions (bottom view) ..........................................................................................2-129
Figure 2-33 Detail B .....................................................................................................................................2-130
Figure 2-34 Package dimensions (side view) ...............................................................................................2-130
Figure 2-35 Detail A .....................................................................................................................................2-130
Figure 2-36 Schematic colors in each pinout diagram..................................................................................2-132

Figure 2-37 Hi3520 pinout (rows AT, columns 116)................................................................................2-133
Figure 2-38 Hi3520 pinout (rows AT, columns 1732)..............................................................................2-134
Figure 2-39 Hi3520 pinout (rows UAM, columns 116) ...........................................................................2-135

Figure 2-40 Hi3520 pinout (rows UAM, columns 1732) .........................................................................2-136
Figure 3-1 Reset signal control diagram...........................................................................................................3-1
Figure 3-2 Functional block diagram of the clock management module..........................................................3-4

Figure 3-3 Address space mapping during the booting from the NOR flash..................................................3-18
Figure 3-4 Address distribution after the remapping is cleared during the booting from the NOR flash. ......3-20
Figure 3-5 Address space mapping during the booting from the NAND flash...............................................3-21
Figure 3-6 Address distribution after the remapping is cleared during the booting from the NAND flash. ...3-22
Figure 3-7 Address space mapping during the booting from the DDR...........................................................3-24
Figure 3-8 Address distribution after the remapping is cleared during the booting from the DDR................3-25
Figure 3-9 Functional block diagram of the INT............................................................................................3-31
Figure 3-10 Functional block diagram of the DMAC ....................................................................................3-41
Figure 3-11 Diagram of updating channel registers through LLI ...................................................................3-42

Figure 3-12 Structure of the DMAC LLIs ......................................................................................................3-60
Figure 3-13 3DES encryption of the 3-key operation and 2-key operation ....................................................3-68
Figure 3-14 3DES decryption of the 3-key operation and 2-key operation ....................................................3-69
Figure 3-15 ECB mode of the AES and DES algorithms ...............................................................................3-69

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Figure 3-16 ECB mode of the 3DES algorithm..............................................................................................3-70

Figure 3-17 CBC mode of the AES and DES algorithms ...............................................................................3-71
Figure 3-18 CBC mode of the 3DES algorithm..............................................................................................3-72
Figure 3-19 S-bit CFB mode of the AES and DES algorithms.......................................................................3-73
Figure 3-20 S-bit CFB mode of the 3DES algorithm .....................................................................................3-74
Figure 3-21 OFB mode of the AES algorithm ................................................................................................3-75
Figure 3-22 S-bit OFB mode of the DES algorithm .......................................................................................3-76
Figure 3-23 S-bit OFB mode of the 3DES algorithm .....................................................................................3-77
Figure 3-24 CTR mode of the AES algorithm ................................................................................................3-78
Figure 3-25 Application block diagram of the watchdog .............................................................................3-108
Figure 3-26 Process of switching the system mode......................................................................................3-124
Figure 3-27 Bit allocation of chip ID registers .............................................................................................3-127
Figure 4-1 Diagram of connecting the DDRC to one DDR2 SDRAM.............................................................4-5
Figure 4-2 Diagram of connecting the DDRC to two DDR2 SDRAMs...........................................................4-6

Figure 4-3 Connection between the SMI controller and the asynchronous static memory.............................4-32
Figure 4-4 Connection between the SMI controller and the control devices integrated with asynchronous static
memory interfaces ...........................................................................................................................................4-32
Figure 4-5 Timing diagram (read/write) of the SMI controller in timing parameter mode ............................4-34
Figure 4-6 Timing diagram (page read) of the SMI controller in timing parameter mode .............................4-34
Figure 4-7 Timing diagram (wait read/write) of the SMI controller in asynchronous wait mode ..................4-35
Figure 4-8 Block diagram of NANDC interfaces ...........................................................................................4-54

Figure 4-9 Typical timing when the NANDC reads the data of a page size from the NAND flash ...............4-55
Figure 4-10 Timing when the NANDC starts to be programmed...................................................................4-56
Figure 4-11 Data storage structure of the NAND flash with the page size of (512 + 16) bytes in 1-bit ECC
mode ................................................................................................................................................................4-60
Figure 4-12 Data storage structure of the NAND flash with the page size of 2 KB (2048 + 64) bytes..........4-61
Figure 4-13 Data structure after data is automatically stored in main areas and their corresponding spare areas
.........................................................................................................................................................................4-61
Figure 4-14 Data storage structure of the NAND flash with the page size of 2 KB (2048 + 64) bytes in 4-bit
ECC mode .......................................................................................................................................................4-62
Figure 4-15 Data storage structure of the NAND flash with the page size of (2048 + 26 x 4) bytes in 8-bit ECC
mode ................................................................................................................................................................4-62
Figure 5-1 Typical application..........................................................................................................................5-4
Figure 5-2 Ethernet II frame format .................................................................................................................5-4

Figure 5-3 General data flow............................................................................................................................5-5

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Figure 5-4 Data storage format in the downlink configuration FIFO...............................................................5-6

Figure 5-5 Data storage format in the uplink configuration FIFO....................................................................5-6
Figure 5-6 Data storage format in the downlink SDRAM................................................................................5-7
Figure 5-7 Data storage format in the uplink SDRAM.....................................................................................5-7
Figure 6-1 Functional block diagram of the VIU .............................................................................................6-1
Figure 6-2 Typical application of the VIU........................................................................................................6-4
Figure 6-3 Vertical timing of the 525-line 60 fields/s video system .................................................................6-7
Figure 6-4 Vertical timing of the 625-line 50 fields/s video system .................................................................6-7
Figure 6-5 2-Path BT.656 TDM timing ............................................................................................................6-8
Figure 6-6 4-Path BT.656 TDM timing ............................................................................................................6-8
Figure 6-7 Horizontal input timing of the HD interface ...................................................................................6-9
Figure 6-8 Vertical input timing of the HD interface........................................................................................6-9
Figure 6-9 ITU-R BT.601 horizontal timing...................................................................................................6-10
Figure 6-10 NTSC vertical sync timings ........................................................................................................6-10

Figure 6-11 PAL vertical sync timings ........................................................................................................... 6-11
Figure 6-12 DC horizontal timing ..................................................................................................................6-12
Figure 6-13 DC vertical pulse timing .............................................................................................................6-12

Figure 6-14 DC vertical line valid timing.......................................................................................................6-12
Figure 6-15 Horizontal sync timing of the 16-bit sync parallel interface .......................................................6-13
Figure 6-16 Vertical sync timing of the 16-bit sync parallel interface............................................................6-13
Figure 6-17 Relationships between the active video area and the horizontal/vertical blanking areas ............6-14
Figure 6-18 YCbCr 4:2:2 co-sited sampling format .......................................................................................6-14
Figure 6-19 YCbCr 4:2:2 interspersed sampling format.................................................................................6-15
Figure 6-20 YCbCr4:2:2 storage mode...........................................................................................................6-16
Figure 6-21 Big endian and little endian storage modes.................................................................................6-16
Figure 6-22 Package storage mode.................................................................................................................6-17
Figure 6-23 8-bit raw data storage mode ........................................................................................................6-17
Figure 6-24 Position of the data of blanking areas .........................................................................................6-18
Figure 6-25 Mappings between the external ports and internal channels of the VIU.....................................6-19
Figure 6-26 Clock configuration of the VIU ..................................................................................................6-20
Figure 6-27 Workflow of the VIU ..................................................................................................................6-22
Figure 6-28 Software configuration process...................................................................................................6-23

Figure 6-29 Process of reading the luminance statistical value through software ..........................................6-24

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Figure 6-30 Parameter diagram of the captured image...................................................................................6-36

Figure 6-31 Sequence of storing blanking area data in registers ....................................................................6-64
Figure 6-32 Multiplexing relationship between VOU interfaces....................................................................6-80
Figure 6-33 Processing the pixel alpha data of a graphics layer.....................................................................6-82
Figure 6-34 Three sets of coordinates of a video layer...................................................................................6-83
Figure 6-35 Process of configuring surface registers (recommended) ...........................................................6-85
Figure 6-36 Frame update mode of surface registers......................................................................................6-86
Figure 6-37 Field update mode of surface registers........................................................................................6-86
Figure 6-38 Updating the on-chip coefficients ...............................................................................................6-88
Figure 7-1 Connection diagram of the I2S interface in master mode................................................................7-4
Figure 7-2 Connections diagram of the I2S interface in the slave mode ...........................................................7-4
Figure 7-3 Connections of the I2S/PCM interface used for audio recording in master mode ...........................7-5
Figure 7-4 Connections of the I2S/PCM interface used for audio recording in slave mode .............................7-6
Figure 7-5 Timing diagram of the I2S interface ...............................................................................................7-6

Figure 7-6 Timing diagram of the PCM interface in standard mode ................................................................7-7
Figure 7-7 Timing diagram of the PCM interface in customized mode ...........................................................7-7
Figure 7-8 Receiving 2-/4-/8-/16-channel data through the I2S interface .........................................................7-7
Figure 7-9 Receiving 2-/4-/8-/16-channel data through the PCM interface .....................................................7-8
Figure 8-1 Typical application circuit of the MMC..........................................................................................8-3
Figure 8-2 Functional block diagram of the MMC...........................................................................................8-4

Figure 8-3 Non-data transfer commands of the MMC .....................................................................................8-5
Figure 8-4 Command format of the MMC .......................................................................................................8-5
Figure 8-5 Response format of the card device ................................................................................................8-5
Figure 8-6 Single-block and multiple-block read operations............................................................................8-6
Figure 8-7 Single-block and multiple-block write operations ..........................................................................8-7
Figure 8-8 Block data format in 1-bit transfer mode ........................................................................................8-7
Figure 8-9 Block data format in 4-bit transfer mode ........................................................................................8-8
Figure 9-1 Typical application of the PCI bus ..................................................................................................9-4
Figure 9-2 Architecture of the Hi3520 PCI module..........................................................................................9-5

Figure 9-3 Timing diagram of the memory (I/O) read operation......................................................................9-5
Figure 9-4 Timing diagram of the memory (I/O) write operation ....................................................................9-6
Figure 9-5 Timing diagram of configuration access of the PCI bus .................................................................9-6
Figure 10-1 Logic block diagram of the USB module ...................................................................................10-2

02 (2010-01-19) xiii

Hi3520

Figure 10-2 Reference design of the USB 2.0 host ........................................................................................10-4

Figure 11-1 Circuit diagram of the typical I2C application............................................................................. 11-2
Figure 11-2 Timing for I2C data transfer ........................................................................................................ 11-2
Figure 11-3 Frame format for I2C data transfer .............................................................................................. 11-3
Figure 11-4 Typical application block diagram 1 of the UART.................................................................... 11-33
T
Figure 11-5 Typical application block diagram 2 of the UART.................................................................... 11-34

T
Figure 11-6 Block diagram of the RTS signal output mode ......................................................................... 11-34
Figure 11-7 Frame format of the UART ....................................................................................................... 11-35
T
Figure 11-8 Application block diagram when the SPI is connected to a single slave device........................ 11-54
Figure 11-9 Application block diagram when the SPI is connected to two slave devices ............................ 11-54
Figure 11-10 Application block diagram of the SPI acting as a slave device ............................................... 11-55
Figure 11-11 Motorola SPI single frame format (spo = 0, sph = 0) .............................................................. 11-55
Figure 11-12 Motorola SPI continuous frame format (spo = 0, sph = 0)...................................................... 11-56
Figure 11-13 Motorola SPI single frame format (spo = 0, sph = 1).............................................................. 11-56
Figure 11-19 TI synchronous serial single frame format .............................................................................. 11-59

Figure 11-20 TI synchronous serial continuous frame format ...................................................................... 11-60
Figure 11-21 National Semiconductor Microwire single frame format........................................................ 11-60
Figure 11-22 National Semiconductor Microwire continuous frame format................................................ 11-61
Figure 11-23 Functional block diagram of the IR module............................................................................ 11-74
Figure 11-24 Frame format for transmitting a single NEC with simple repeat code .................................... 11-76
Figure 11-25 Frame format for transmitting continuous NEC with simple repeat codes by holding the key
down.............................................................................................................................................................. 11-77
Figure 11-26 Definitions of bit0 and bit1 in the NEC with simple repeat code............................................ 11-77
Figure 11-27 Code format for transmitting a single NEC with simple repeat code...................................... 11-77
Figure 11-28 Code format for transmitting continuous NEC with simple repeat codes by holding the key down
....................................................................................................................................................................... 11-77
Figure 11-29 Frame format for transmitting a single NEC with full repeat code ......................................... 11-78
Figure 11-30 Frame format for transmitting continuous NEC with full repeat codes by holding the key down
....................................................................................................................................................................... 11-78
Figure 11-31 Definitions of bit0 and bit1 in the NEC with full repeat code................................................. 11-78

xiv 02(2010-01-19)

Hi3520

Figure 11-32 Code format for transmitting a single NEC with full repeat code ........................................... 11-79
Figure 11-33 Frame format for transmitting a single TC9012 code ............................................................. 11-79
Figure 11-34 Frame format for transmitting continuous TC9012 code by holding the key down................ 11-80
Figure 11-35 Definitions of bit0 and bit1 of the TC9012 code..................................................................... 11-80
Figure 11-36 Code format for transmitting a single TC9012 code ............................................................... 11-80
Figure 11-37 Code format for transmitting continuous TC9012 codes (C0 = 1) .......................................... 11-80
Figure 11-38 Code format for transmitting continuous TC9012 codes (C0 = 0) .......................................... 11-81
Figure 11-39 Frame format for transmitting a single SONY code................................................................ 11-81
Figure 11-40 Frame format for transmitting continuous SONY codes by holding the key down................. 11-81
Figure 11-41 Definitions of bit0 and bit1 ..................................................................................................... 11-82
Figure 11-42 Process of initializing the IR module ...................................................................................... 11-83
Figure 11-43 Process of reading the decoded data........................................................................................ 11-84
Figure 12-1 Schematic diagram of the system for debugging of the ARM software......................................12-2

02 (2010-01-19) xv

Hi3520

Table 2-1 I/O type of pins .................................................................................................................................2-1

Table 2-2 Power pins ........................................................................................................................................2-2
Table 2-3 SIO pins ..........................................................................................................................................2-22

Table 2-4 VDAC pins .....................................................................................................................................2-23
Table 2-5 DDRA pins .....................................................................................................................................2-26
Table 2-6 DDRB pins .....................................................................................................................................2-30

Table 2-7 EBI pins ..........................................................................................................................................2-34
Table 2-8 GMAC pins.....................................................................................................................................2-36
Table 2-9 VO pins...........................................................................................................................................2-38

Table 2-10 PCI pins ........................................................................................................................................2-39
Table 2-11 SYS pins .......................................................................................................................................2-43
Table 2-12 I2C pins.........................................................................................................................................2-44

Table 2-13 JTAG pins .....................................................................................................................................2-44
Table 2-14 UART pins ....................................................................................................................................2-45
Table 2-15 USB pins.......................................................................................................................................2-45

Table 2-16 VI pins ..........................................................................................................................................2-46
Table 2-17 Software multiplexing pins of the VI interface.............................................................................2-48
Table 2-18 Software multiplexing signals of the VI interface ........................................................................2-50

Table 2-19 Software multiplexing pins of the VO interface ...........................................................................2-52
Table 2-20 Software multiplexing signals of the VO interface.......................................................................2-53
Table 2-21 Software multiplexing pins of the I2C interface ...........................................................................2-56
Table 2-22 Software multiplexing signals of the I2C interface.......................................................................2-56
Table 2-23 Software multiplexing pins of the SIO interface...........................................................................2-56
Table 2-24 Software multiplexing signals of the SIO interface ......................................................................2-56

Table 2-25 Software multiplexing pins of the EBI interface...........................................................................2-57
Table 2-26 Software multiplexing signals of the EBI interface ......................................................................2-57

02 (2010-01-19) xvii

Hi3520

Table 2-27 Software multiplexing pins of the GMAC interface .....................................................................2-58

Table 2-28 Software multiplexing signals of the GMAC interface.................................................................2-58
Table 2-29 Software multiplexing pins of the PCI interface...........................................................................2-58
Table 2-30 Software multiplexing signals of the PCI interface ......................................................................2-58
Table 2-31 Hardware multiplexing pins of the EBI interface .........................................................................2-59
Table 2-32 Hardware multiplexing signals of the EBI interface.....................................................................2-60
Table 2-33 Hardware multiplexing pins of the PCI interface .........................................................................2-62
Table 2-34 Hardware multiplexing signals of the PCI interface .....................................................................2-62
Table 2-35 Summary of the IO config registers (base address: 0x200F_0000) ..............................................2-63
Table 2-36 DC parameters (DVDD33 = 3.3 V) ............................................................................................2-109
Table 2-37 DC parameters (DVDD18 = 1.8 V) ............................................................................................2-109
Table 2-38 Recommended operating conditions........................................................................................... 2-110
Table 2-39 Clock parameters ........................................................................................................................ 2-113
Table 2-40 Memory device parameters......................................................................................................... 2-113

Table 2-41 Package/Board parameters.......................................................................................................... 2-114
Table 2-42 Timing parameters of the MII interface ...................................................................................... 2-116
Table 2-43 Timing parameters of the RGMII interface................................................................................. 2-117

Table 2-44 Timing parameters of the MDIO interface.................................................................................. 2-118
Table 2-45 Transmit timing parameters of the MDIO interface.................................................................... 2-118
Table 2-46 Timing parameters of the VI interface ........................................................................................ 2-119

Table 2-47 Timing parameters of the VO interface....................................................................................... 2-119
Table 2-48 Timing of the VO concatenated input interface ..........................................................................2-120
Table 2-49 Timing parameters of the PCI interface ......................................................................................2-121
Table 2-50 Timing parameters of the I2C interface .......................................................................................2-122
Table 2-51 Timing parameters of the MMC .................................................................................................2-123
Table 2-52 Timing parameters of the SSP interface......................................................................................2-124
Table 2-53 Timing parameters of the data receive signal URXD of the UART interface.............................2-126
Table 2-54 Timing parameters of the data transmit signal UTXD of the UART interface............................2-126
Table 2-55 Timing parameters of the I2S interface .......................................................................................2-127

Table 2-56 Timing parameters of the PCM interface....................................................................................2-128
Table 2-57 Package parameters.....................................................................................................................2-130
Table 2-58 Statistics on the Hi3520 pins.......................................................................................................2-131

Table 2-59 Pin arrangement ..........................................................................................................................2-136

xviii 02(2010-01-19)

Hi3520

Table 3-1 Types of reset signals ........................................................................................................................3-2

Table 3-2 PLL configuration registers of the Hi3520 .......................................................................................3-5
Table 3-3 Formulas for calculating the frequency of each PLL pin of the Hi3520...........................................3-5
Table 3-4 Configuration parameters related to the APLL of the Hi3520 ..........................................................3-6
Table 3-5 Configuration parameters related to the EPLL of the Hi3520 ..........................................................3-7
Table 3-6 Configuration parameters related to VPLL0 of the Hi3520..............................................................3-8
Table 3-7 Configuration parameters related to VPLL1 of the Hi3520..............................................................3-9
Table 3-8 Frequency configuration of the ARM/SCLK/HCLK/PCLK........................................................... 3-11
Table 3-9 Mapping between the system controller status and clock switching............................................... 3-11
Table 3-10 Clock frequency configuration of the MMC module....................................................................3-12
Table 3-11 Clock frequency configuration of the PCI module .......................................................................3-12
Table 3-12 Clock frequency configuration of the SMI module ......................................................................3-12
Table 3-13 Clock frequency configuration of the VO module........................................................................3-13
Table 3-14 Clock frequency configuration of the VI module .........................................................................3-13

Table 3-15 Clock frequency configuration of the ETH module......................................................................3-14
Table 3-16 Clock frequency configuration of the SIO0/SIO1/SIO2 module ..................................................3-14
Table 3-17 Selection of the boot mode ...........................................................................................................3-17

Table 3-18 Address space list..........................................................................................................................3-26
Table 3-19 Allocation of the PCI address space..............................................................................................3-30
Table 3-20 Interrupt mapping of VIC0 ...........................................................................................................3-32

Table 3-21 Interrupt mapping of VIC1 ...........................................................................................................3-33
Table 3-22 Summary of INT registers ............................................................................................................3-35
Table 3-23 DMAC hardware request signals ..................................................................................................3-43
Table 3-24 Summary of DMAC registers (base address: 0x0x100D_0000)...................................................3-46
Table 3-25 Mapping between the value of DBSize or SBSize and the burst size...........................................3-63
Table 3-26 Mapping between the value of DWidth or SWidth and the transfer bit width ..............................3-63
Table 3-27 Three protection bits of the prot field of DMAC_CX_CONTROL ..............................................3-64
Table 3-28 Flow controller and transfer type corresponding to the flow_cntrl field.......................................3-67
Table 3-29 Summary of CIPHER register (base address: 0x100C_0000) ......................................................3-80

Table 3-30 Summary of timer registers (base addresses: 0x2000_0000, 0x2001_0000, 0x2002_0000, and
0x2003_0000)..................................................................................................................................................3-98
Table 3-31 Watchdog interface signal...........................................................................................................3-108
Table 3-32 Summary of watchdog registers (base address: 0x2004_0000) .................................................. 3-110
Table 3-33 Summary of RTC registers (base address: 0x2006_0000) .......................................................... 3-117

02 (2010-01-19) xix

Hi3520

Table 3-34 Relationship between the status of the system controller and the system clock .........................3-122
Table 3-35 Summary of system controller registers (base address: 0x2005_0000) ......................................3-128
Table 4-1 Signals of the DDRC interface .........................................................................................................4-1
Table 4-2 DDR2 SDRAMs supported by the Hi3520 DDRC...........................................................................4-7
Table 4-3 Command truth table of the DDRC ..................................................................................................4-8
Table 4-4 Address mapping when the DDRC is in 16-bit mode .....................................................................4-10
Table 4-5 Address mapping when the DDRC is in 32bit mode .................................................................... 4-11
Table 4-6 Summary of DDRC registers ..........................................................................................................4-14
Table 4-7 Interface signals of the SMI controller ...........................................................................................4-30
Table 4-8 Configuration of timing parameters of the SMI controller (bus clock fBUSCLK = 200 MHz) .....4-33
Table 4-9 Read/write timing parameters of the SMI controller ......................................................................4-34
Table 4-10 Page read timing parameters of the SMI controller ......................................................................4-35
Table 4-11 Memory address space supported by the SMI controller ..............................................................4-36
Table 4-12 Summary of SMI controller registers (base address: 0x1010_0000) ............................................4-38
Table 4-13 Signals of NANDC interfaces.......................................................................................................4-53
Table 4-14 Boot configuration pins ................................................................................................................4-57
Table 4-15 K9F2G08U0M addresses..............................................................................................................4-58

Table 4-16 K9GAG08X0M addresses ............................................................................................................4-59
Table 4-17 Common commands for operating the NAND flash memories ....................................................4-59
Table 4-18 Summary of NANDC registers (base address: 0x1000_0000) .....................................................4-65

Table 5-1 Signals of external interfaces ............................................................................................................5-2
Table 5-2 Contents of the Ethernet II frame......................................................................................................5-4
Table 5-3 Summary of GMAC registers (base address: 0x1009_0000)............................................................5-7
Table 5-4 Variables in the offset address of GMAC registers ...........................................................................5-7
Table 6-1 Signals of the VI interface ................................................................................................................6-2
Table 6-2 Format of the ITU-R BT.656 YCbCr 4:2:2 line data ........................................................................6-5
Table 6-3 Formats of SAV and EAV .................................................................................................................6-5
Table 6-4 Valid values of SAV and EAV...........................................................................................................6-5
Table 6-5 ITU-R BT.656 error-correcting codes...............................................................................................6-6

Table 6-6 Formats of SAV and EAV with channel IDs .....................................................................................6-9
Table 6-7 Summary of VIU registers (base address: 0x1010_0000) ..............................................................6-24
Table 6-8 Signals of the VOU digital output interface....................................................................................6-77

Table 6-9 Signals of the VOU analog output interface ...................................................................................6-79

xx 02(2010-01-19)

Hi3520

Table 6-10 Summary of VOU registers (base address: 0x2013_0000) ...........................................................6-88

Table 6-11 Variables in the offset addresses of VOU registers .....................................................................6-104
Table 7-1 SIO interface signals.........................................................................................................................7-2
Table 7-2 Pin multiplexing................................................................................................................................7-8
Table 7-3 Summary of SIO registers............................................................................................................... 7-11
Table 8-1 MMC interface signals......................................................................................................................8-2
Table 8-2 Load parameters of signal lines ........................................................................................................8-3
Table 8-3 Reference configuration of MMC_CMD for non-data transfer command ..................................... 8-11
Table 8-4 Reference configuration of MMC_CMD during the process of reading single-block or
multiple-block data..........................................................................................................................................8-12
Table 8-5 Reference configuration of MMC_CMD during the process of writing single-block or
multiple-block data..........................................................................................................................................8-14
Table 8-6 Reference configuration of MMC_CMDARG during a resume operation.....................................8-17
Table 8-7 Summary of MMC registers (base address: 0x1003_0000)............................................................8-18
Table 9-1 PCI interface signals .........................................................................................................................9-2
Table 9-2 PCI interface signals .........................................................................................................................9-9

Table 9-3 Registers at the AHB side (base address: 0xB000_0000) ............................................................... 9-11
Table 9-4 Summary of PCI configuration space registers...............................................................................9-12
Table 10-1 Interface signals of the USB 2.0 host............................................................................................10-3

Table 10-2 Summary of USB registers (base address: 0x100B_0000) ...........................................................10-5
Table 11-1 Signals of the I2C interface ........................................................................................................... 11-2
Table 11-2 Typical values of I2C_SS_SCL_HCNT........................................................................................ 11-4

T
Table 11-3 Typical values of I2C_SS_SCL_LCNT ........................................................................................ 11-4

T
Table 11-4 Typical values of I2C_FS_SCL_HCNT........................................................................................ 11-5

T
Table 11-5 Typical values of I2C_FS_SCL_LCNT ........................................................................................ 11-5

T
Table 11-6 I2C register summary (base address: 0x200D_0000) .................................................................... 11-8
Table 11-7 Signals of the UART0 interface .................................................................................................. 11-31

Table 11-10 Signals of the UART3 interface ................................................................................................ 11-32
Table 11-11 Summary of UART registers..................................................................................................... 11-38

Table 11-12 SPI interface signals.................................................................................................................. 11-53
Table 11-13 Typical configuration of the SPI clock dividers ........................................................................ 11-62
Table 11-14 Summary of SPI registers (base address: 0x200E_0000).......................................................... 11-65

02 (2010-01-19) xxi

Hi3520

Table 11-15 IR interface signals.................................................................................................................... 11-73

Table 11-16 Statistics on the code formats of the infrared receive data (NEC with simple repeat code)...... 11-74
Table 11-17 Statistics on the code formats of the infrared receive data (NEC with full repeat code)........... 11-75
Table 11-18 Statistics on the code formats of the infrared receive data (TC9012 and SONY)..................... 11-76
Table 11-19 Summary of IR registers (base address: 0x2007_0000)............................................................ 11-85
Table 11-20 GPIO interface signals .............................................................................................................. 11-99
Table 11-21 Configuration of pin multiplexing .......................................................................................... 11-103
Table 11-22 Base addresses of the eight sets of GPIO pins ........................................................................ 11-107
Table 11-23 GPIO register summary .......................................................................................................... 11-108
Table 12-1 Operating modes of the Hi3520....................................................................................................12-1
Table 12-2 JTAG interface signals of the Hi3520...........................................................................................12-2
Table 12-3 Connections to the ARM926 and ARM1176 ................................................................................12-3

xxii 02(2010-01-19)

Hi3520

Hi3520

Hi3520 H.264 V100

z
z

02 (2010-01-19) 1

Hi3520

Terminal Display Terminal Display

0 1
RO W0C

WO W1S 1 1 0

2 02 (2010-01-19)

Hi3520

RW W0S 0 1 1
RC 1
OSW
W1C 1 0
1K 1024
RAM 1M 1,048,576
1G 1,073,741,824
1k 1000
1M 1,000,000
1G 1,000,000,000
0x 0xFE040x18 16
0b 0b0000b00 00000000 2 2

2010-01-19 02 2
2.5 reg2reg17
VOUDAT0VOUDAT15

02 (2010-01-19) 3

Hi3520

2009-12-23 01 1
1.1.14 070

2
2-4 RSET
2-32 NFPAGE0 NFPAGE1 00
11 FUNSEL0 FUNSEL1
01 10
2-38 070

3
3.10.5 SC_PERCTRL23 bit[10:9]
00 11
4
512B8KB page size NAND Flash

2009-11-30 00B60 11
GPIO
2009-11-20 00B50 4
4.3.5
bit
SC_PERDIS[nandc_clken]0
SC_PERDIS[nandcclkdis]1
11
11.2..5

SC_PERDIS[uartclkdis]=1
SC_PERDIS[uartclkdis]=0xF
2009-10-30 00B40 4
4.1.4.2 DDR 4-4 4-5 2Gbit

6
VIn_PORT_CFG bit[11:10] bit[7:6]
BT.656 2bit

4 02 (2010-01-19)

Hi3520

2009-08-28 00B30 3
XIN XIN24
CIPHER_CTRL bit[7:6] 3DES

4
4.1.5.3 DDR 4 DDR burst
length 4 8
6
6.1.5.3 0 2 4

9 PCI
PCIAHB_SIZ_NP FF000000
FFC00000PCIAHB_SIZ_PF FF000000
FF800000
2009-07-30 00B20 113

2 B01/B02
1AVDD AVSS AVDD_DAC
AVSS_DAC
2DDR VREFA VREFB
VREF
3D22 DDRA_UDM0
4D11 DDRA_LDM1
5VI VI0DAT0VI0DAT7
VOUDAT8VOUDAT15VI1DAT0~VI1DAT7
VOUDAT0VOUDAT7
6 PinMap
2009-5-30 00B01/00B02 1 2

02 (2010-01-19) 5

Hi3520
1
1.1
1.1.1
Hi3520 1-1
1-1 Hi3520
Ethernet 10/100/1000 Mbit/s ARM Processor PCI

PHY GMAC Java Acc/VFP/MMU
BT.1120 SDIO
Video BT656
Decoder Video In X 4 Graphics Engine Video Codec
(A/D) I2C
De-inerlace/Scaler/OSD H.264/MJPEG
CMOS
SSP/SPI
Sensor
TV CVBS Video Out CVBS 0 Shared memory switch / DMA GPIO
CVBS JTAG
TV Video Out CVBS 1 Pre/Post processing engine
UART4
RGB
VGA Video Out VGA Interrupt Control Timers/WDT
IR
BT.1120
Video
BT656 Security RTC
Encoder Video Out USB2.02
AES/DES/3DES Real-Time Clock
(D/A)
Audio NAND Flash NOR Flash DDR2 SDRAM

I2S 3
Codec Controller Controller ControllerX 2
Hi3520
NAND Flash NOR Flash DDR2 SDRAM

02 (2010-01-19) 1-1

Hi3520
1
1.1.2
Hi3520 ARM1176 ARM926 ARM1176
CPUCentral Processing Unit 600MHzARM1176
ARM926

z ARM1176 CPU
16KB cache 16KB cache
2KB ITCMInstruction Tightly-Coupled Memory
600MHz
z DMACDirect Memory Access Controller

z 32
z 4 Dual-Timer Dual-Timer 2
1.1.3
Hi3520

z De-interlace
z De-interlace 60 60
60 30
z
z clipalpha blendingROPcolorkey Gamma
z 16
z OSDOn Screen Display 4

z
z 2D

1-2 02 (2010-01-19)

Hi3520
1
1.1.4
Hi3520 H.264/MJEPG/JPEG
z H.264 Main Profile @ Level 3
z H.264 BaseLine @ Level 3
z JPEG/MJPEG Baseline
z H.264 8 D1
z H.264 1280%1024@30fps
z H.264
120fps D1 +120fps CIF +120fps D1 @NTSC
100fps D1 +100fps CIF +100fps D1 @PAL
z H.264 MJPEG
z MJPEG/JPEG 300 10f/s
z H.264 CBR/VBR/ABR 16kbit/s20Mbit/s
1.1.5
AESAdvanced Encryption Standard/DESData Encryption
Standard/3DES
z DES/3DES AES FIPS46-3/FIPS 197 DES/3DES AES

FIPS -81/NIST special800-38a
1.1.6

z 2 DDR2Double Data-Rate Controller
400MHz
16bit 32bit
16bit DDR2 SDRAM 256MB
32bit DDR2 SDRAM 512MB
z NOR Flash
8bit
2 32MB
NOR Flash
z NAND Flash
8bit

02 (2010-01-19) 1-3

Hi3520
1
SLCMLC148bit ECC
8GB
NAND Flash
1.1.7
802.3 10/100/1000 Mbit/s ARM1176

z 10/100 Mbit/s 1000Mbit/s
z RGMII MII
z MDIO
z
z MAC
z
z
1.1.8
4 2 6
27/54/108 MHz
z
4 BT.656 YCrCb 4:2:2 8bit27/54/108MHz
2 SMPTE296MBT.1120
Digital Camera 1280%1024@30fps
1600%1200@20fps2048%1536@10fps
z

VGA/YPbPr%1+CVBS%2
VGA%2
1920%1080p@30fps1920%1080i@60fps
BT.656BT.1120LCD
1.1.9
Hi3520 SIOSonic Input/Output 3 I2SInter-IC
Sound Audio codec

z I2S 16 8bit 16bit
z 8/16/32
z 8/16/32/44.1/48 kHz

1-4 02 (2010-01-19)

Hi3520
1
1.1.10 MMC/SD/SDIO
MMCMulti-media Card/SDSecure Digital/SDIOSecure Digital Input/Output
SD/MMC SDIO
Blue ToothWiFi MMC/SD/SDIO

z SD mem-version 2.00
z SDIO-version 1.10
z MMC-version 4.2
1.1.11 PCI
Hi3520 PCIPeripheral Component InterconnectLocal
BusPCI
PCI/miniPCI SATAWiFiPCI-to-PCI Bridge
PCI
z PCI2.3 miniPCI
z Host BridgeSimple Bridge
PCI 5 PCI Device PCI
z PCI 33MHz 66MHz
1.1.12 USB
Hi3520 2 USBUniversal Serial Bus 2.0 Host
z USB 2.0
z OHCI Rev 1.0aEHCI Rev 1.0
z High-speedFull-speedLow-speed
z
z Control TransferBulk TransferIsochronous TransferInterrupt Transfer

z USB Hub 127
1.1.13

z I2C
I2CThe Inter-Integrated Circuit I2C Philips
I2C I2C
z UART
UARTUniversal Asynchronous Receiver Transmitter
UART Hi3520 4 UART

02 (2010-01-19) 1-5

Hi3520
1
3 1 RTSCTS

z SPI
SPISynchronous Peripheral Interface master slave

A Motorola SPISynchronous Peripheral Interface-compatible interface
A Texas Instruments synchronous serial interface
A National Semiconductor Microwire interface
z IR
IRInfrared Remoter NEC with simple
repeat codeNEC with full repeat codeSONY TC9012

z GPIO
Hi3520 8 GPIOGeneral Purpose Input/Output GPIO 8
GPIO

1.1.14
z 1600mW DVR
z
z 90nm 1.0/1.8/3.3 V
z 768 pin FPBGA 0.8mm 27mm27mm
z 20+85
z 20+105
z 40+125
1.2
Hi3520 ARM11
MPEG-4 AVC/H.264 MJPEG

Hi3520
z 16 CIF DVR
z 4 D1 DVR
z 8 D1 DVR

1-6 02 (2010-01-19)

Hi3520
1
16 CIF DVR
Hi3520 16CIF DVRDigital Video Recorder 1-2

z 1280%1024 VGA
z 16 CIF
z 16 QCIF
z 16 CIF
1-2 Hi3520 16CIF DVR
SATA SATA SATA

HDD HDD HDD
TV VGA TV
or
PCI2SATA
CVBS VGA/CVBS PCI

Flash
DDR2
Hi3520
DDR2 USB2.0 Host
PHY GMAC
GMAC VI0
VI0 VI1
VI1 VI2
VI2 VI3
VI3
Router
16 Ch. A/V Dec.
IP Camera
LAN

02 (2010-01-19) 1-7

Hi3520
1
4 D1 DVR
Hi3520 4D1 DVR 1-3
z 12801024 VGA
z 4 D1
z 4 CIF
z 4 D1
1-3 Hi3520 4D1 DVR
SATA SATA SATA

HDD HDD HDD
TV VGA or TV
PCI2SATA
CVBS VGA/CVBS PCI

Flash
DDR2 Hi3520
DDR2 USB2.0 Host
PHY GMAC
GMAC VI0 VI1
VI2 VI2
VI3 VI3
Router
4 Ch. A/V Dec.
IP Camera
LAN

1-8 02 (2010-01-19)

Hi3520
1
8 D1 DVR
Hi3520 8D1 DVR 1-4
z 12801024 VGA
z 8 D1
z 8 CIF
z 8 D1
1-4 Hi3520 8D1 DVR
SATA SATA SATA

HDD HDD HDD
PCI2SATA
TV VGA or TV
CVBS VGA/CVBS PCI PCI

Flash Host Target
DDR2 Hi3520 Hi3520

DDR2 USB2.0 Host
PHY GMAC
GMAC VI2
VI0 VI1 VI3 VI2 VI3
Router
4 Ch. A/V Dec. 4 Ch. A/V Dec.
IP Camera

LAN

02 (2010-01-19) 1-9

Hi3520
2
2.1
I/O 2-1
2-1 I/O
I/O
IPD
IPU
IS
ISPD
ISPU
OOD
I/O /
IPD/O
IPU/O
ISPU/O
IPD/OOD
IPU/OOD
IS/O
IS/OOD
CIN Crystal Oscillator

2-8 02 (2010-01-19)

Hi3520
2
I/O
COUT Crystal Oscillator
2.1.1 POWER
POWER 2-2
2-2 POWER
Pin
mA) V
VDAC
AB8 AVDD33_D - - 3.3 VDAC 3.3V

AC
AE11 AVDD33_D - - 3.3 VDAC 3.3V
AC
AL5 AVDD33_D - - 3.3 VDAC 3.3V
AC
AK3 AVDD33_D - - 3.3 VDAC 3.3V
AC
AK4 AVDD33_D - - 3.3 VDAC 3.3V
AC
AJ3 AVDD33_D - - 3.3 VDAC 3.3V
AC
AH2 AVDD33_D - - 3.3 VDAC 3.3V
AC
AH7 AVDD33_D - - 3.3 VDAC 3.3V
AC
AG3 AVDD33_D - - 3.3 VDAC 3.3V
AC
AD10 DVDD10_D - - 1.0 VDAC 1.0V
AC
AD8 DVDD33_D - - 3.3 VDAC0 3.3V
AC0

02 (2010-01-19) 2-9

Hi3520
2
Pin
mA) V
AE9 DVDD33_D - - 3.3 VDAC1 3.3V

AC1
AM1 AVSS_DAC - - - VDAC
AM5 AVSS_DAC - - - VDAC
AL2 AVSS_DAC - - - VDAC
AK2 AVSS_DAC - - - VDAC
AJ2 AVSS_DAC - - - VDAC
AH1 AVSS_DAC - - - VDAC
AD11 AVSS_DAC - - - VDAC
AB9 AVSS_DAC - - - VDAC
AA12 AVSS_DAC - - - VDAC
AA13 AVSS_DAC - - - VDAC
Y12 AVSS_DAC - - - VDAC
AC9 DVSS10_D - - - VDAC 1.0V

AC
AE8 DVSS33_D - - - VDAC 3.3V
AC
AD9 DVSS33_D - - - VDAC 3.3V
AC
PLL
U28 AVDD33_A - - 3.3 ARM ETH PLL1 3.3V

EPLL

2-10 02 (2010-01-19)

Hi3520
2
Pin
mA) V
T28 AVDD33_V - - 3.3 Video PLL 3.3V

PLL
V24 VDD10_AP - - 1.0 ARM PLL 1.0V
LL
U24 VDD10_EPL - - 1.0 ETH PLL 1.0V
L
T24 VDD10_VP - - 1.0 Video 0 PLL 1.0V
LL0
T25 VDD10_VP - - 1.0 Video 1 PLL 1.0V
LL1
V25 VSS_APLL - - - ARM PLL
V28 VSS_APLL - - - ARM PLL
U25 VSS_EPLL - - - ETH PLL
R25 VSS_VPLL - - - Video PLL
R28 VSS_VPLL - - - Video PLL
USB
K5 USBVDD - - 1.0 USB 2.0 HOST

1.0V
N8 USBVDDA3 - - 3.3 USB 2.0 HOST

3 3.3V
R8 USBVDDA3 - - 3.3 USB 2.0 HOST

3 3.3V
P9 USBVDDA3 - - 3.3 USB 2.0 HOST

3 3.3V
M1 USBVDDA3 - - 3.3 USB 2.0 HOST

3 3.3V

3 3.3V

3 3.3V
L4 USBVDDA3 - - 3.3 USB 2.0 HOST

3 3.3V
L5 USBVSS - - - USB 2.0 HOST

02 (2010-01-19) 2-11

Hi3520
2
Pin
mA) V
P8 USBVSSA3 - - - USB 2.0 HOST

3
R9 USBVSSA3 - - - USB 2.0 HOST
3
N9 USBVSSA3 - - - USB 2.0 HOST
3
L3 USBVSSA3 - - - USB 2.0 HOST
3
K1 USBVSSA3 - - - USB 2.0 HOST
3
3
3
(CORE)
AA14 DVDD10 - - 1.0 1.0V
AA15 DVDD10 - - 1.0 1.0V
AA16 DVDD10 - - 1.0 1.0V
AA17 DVDD10 - - 1.0 1.0V
AA18 DVDD10 - - 1.0 1.0V
AA19 DVDD10 - - 1.0 1.0V
AA20 DVDD10 - - 1.0 1.0V
Y21 DVDD10 - - 1.0 1.0V
W12 DVDD10 - - 1.0 1.0V
W21 DVDD10 - - 1.0 1.0V
V12 DVDD10 - - 1.0 1.0V
V21 DVDD10 - - 1.0 1.0V
U12 DVDD10 - - 1.0 1.0V
U21 DVDD10 - - 1.0 1.0V

2-12 02 (2010-01-19)

Hi3520
2
Pin
mA) V
T12 DVDD10 - - 1.0 1.0V
T21 DVDD10 - - 1.0 1.0V
R12 DVDD10 - - 1.0 1.0V
R21 DVDD10 - - 1.0 1.0V
P12 DVDD10 - - 1.0 1.0V
P21 DVDD10 - - 1.0 1.0V
N12 DVDD10 - - 1.0 1.0V
N21 DVDD10 - - 1.0 1.0V
M13 DVDD10 - - 1.0 1.0V
M14 DVDD10 - - 1.0 1.0V
M15 DVDD10 - - 1.0 1.0V
M16 DVDD10 - - 1.0 1.0V
M17 DVDD10 - - 1.0 1.0V
M18 DVDD10 - - 1.0 1.0V
M19 DVDD10 - - 1.0 1.0V
M20 DVDD10 - - 1.0 1.0V
DDR2
J25 DVDD18 - - 1.8 DDR2 1.8V
H17 DVDD18 - - 1.8 DDR2 1.8V
H16 DVDD18 - - 1.8 DDR2 1.8V
H15 DVDD18 - - 1.8 DDR2 1.8V
H10 DVDD18 - - 1.8 DDR2 1.8V
H9 DVDD18 - - 1.8 DDR2 1.8V
R24 DVDD18 - - 1.8 DDR2 1.8V

02 (2010-01-19) 2-13

Hi3520
2
Pin
mA) V
P24 DVDD18 - - 1.8 DDR2 1.8V
P30 DVDD18 - - 1.8 DDR2 1.8V
P31 DVDD18 - - 1.8 DDR2 1.8V
N24 DVDD18 - - 1.8 DDR2 1.8V
M24 DVDD18 - - 1.8 DDR2 1.8V
M28 DVDD18 - - 1.8 DDR2 1.8V
L24 DVDD18 - - 1.8 DDR2 1.8V
K24 DVDD18 - - 1.8 DDR2 1.8V
K30 DVDD18 - - 1.8 DDR2 1.8V
K31 DVDD18 - - 1.8 DDR2 1.8V
J10 DVDD18 - - 1.8 DDR2 1.8V
J11 DVDD18 - - 1.8 DDR2 1.8V
J12 DVDD18 - - 1.8 DDR2 1.8V
J13 DVDD18 - - 1.8 DDR2 1.8V
J14 DVDD18 - - 1.8 DDR2 1.8V
J15 DVDD18 - - 1.8 DDR2 1.8V
J16 DVDD18 - - 1.8 DDR2 1.8V
J17 DVDD18 - - 1.8 DDR2 1.8V
J18 DVDD18 - - 1.8 DDR2 1.8V
J19 DVDD18 - - 1.8 DDR2 1.8V
J20 DVDD18 - - 1.8 DDR2 1.8V
J21 DVDD18 - - 1.8 DDR2 1.8V
J22 DVDD18 - - 1.8 DDR2 1.8V
J23 DVDD18 - - 1.8 DDR2 1.8V

2-14 02 (2010-01-19)

Hi3520
2
Pin
mA) V
G28 DVDD18 - - 1.8 DDR2 1.8V
E7 DVDD18 - - 1.8 DDR2 1.8V
E8 DVDD18 - - 1.8 DDR2 1.8V
E12 DVDD18 - - 1.8 DDR2 1.8V
E13 DVDD18 - - 1.8 DDR2 1.8V
E16 DVDD18 - - 1.8 DDR2 1.8V
E17 DVDD18 - - 1.8 DDR2 1.8V
E18 DVDD18 - - 1.8 DDR2 1.8V
E22 DVDD18 - - 1.8 DDR2 1.8V
E23 DVDD18 - - 1.8 DDR2 1.8V
E26 DVDD18 - - 1.8 DDR2 1.8V
E27 DVDD18 - - 1.8 DDR2 1.8V
E30 DVDD18 - - 1.8 DDR2 1.8V
E31 DVDD18 - - 1.8 DDR2 1.8V
C12 DVDD18 - - 1.8 DDR2 1.8V
C19 DVDD18 - - 1.8 DDR2 1.8V
C23 DVDD18 - - 1.8 DDR2 1.8V
C30 DVDD18 - - 1.8 DDR2 1.8V
B4 DVDD18 - - 1.8 DDR2 1.8V
B9 DVDD18 - - 1.8 DDR2 1.8V
B12 DVDD18 - - 1.8 DDR2 1.8V
B19 DVDD18 - - 1.8 DDR2 1.8V
B23 DVDD18 - - 1.8 DDR2 1.8V
B27 DVDD18 - - 1.8 DDR2 1.8V

02 (2010-01-19) 2-15

Hi3520
2
Pin
mA) V
A4 DVDD18 - - 1.8 DDR2 1.8V
A9 DVDD18 - - 1.8 DDR2 1.8V
A27 DVDD18 - - 1.8 DDR2 1.8V
H24 VREF - - 0.9 DDRA 0.9V
H22 VREF - - 0.9 DDRA 0.9V
H20 VREF - - 0.9 DDRA 0.9V
H18 VREF - - 0.9 DDRA 0.9V
H14 VREF - - 0.9 DDRA 0.9V
H12 VREF - - 0.9 DDRA 0.9V
K25 VREF - - 0.9 DDRB 0.9V
M25 VREF - - 0.9 DDRB 0.9V
P25 VREF - - 0.9 DDRB 0.9V
IO
K8 DVDD33 - - 3.3 3.3V
L8 DVDD33 - - 3.3 3.3V
M8 DVDD33 - - 3.3 3.3V
T8 DVDD33 - - 3.3 3.3V
U8 DVDD33 - - 3.3 3.3V
Y8 DVDD33 - - 3.3 3.3V
AA8 DVDD33 - - 3.3 3.3V
AE23 DVDD33 - - 3.3 3.3V
AE22 DVDD33 - - 3.3 3.3V
AE19 DVDD33 - - 3.3 3.3V
AE18 DVDD33 - - 3.3 3.3V

2-16 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AE15 DVDD33 - - 3.3 3.3V
AE14 DVDD33 - - 3.3 3.3V
W25 DVDD33 - - 3.3 3.3V
AB25 DVDD33 - - 3.3 3.3V
AC25 DVDD33 - - 3.3 3.3V
AH10 DVDD33 - - 3.3 3.3V
AH11 DVDD33 - - 3.3 3.3V
AH14 DVDD33 - - 3.3 3.3V
AH15 DVDD33 - - 3.3 3.3V
AH18 DVDD33 - - 3.3 3.3V
AH19 DVDD33 - - 3.3 3.3V
AH22 DVDD33 - - 3.3 3.3V
AH23 DVDD33 - - 3.3 3.3V
AH26 DVDD33 - - 3.3 3.3V
AH27 DVDD33 - - 3.3 3.3V
AF5 DVDD33 - - 3.3 3.3V
AF28 DVDD33 - - 3.3 3.3V
AE5 DVDD33 - - 3.3 3.3V
AE28 DVDD33 - - 3.3 3.3V
AD5 DVDD33 - - 3.3 3.3V
AD13 DVDD33 - - 3.3 3.3V
AD14 DVDD33 - - 3.3 3.3V
AD15 DVDD33 - - 3.3 3.3V
AD16 DVDD33 - - 3.3 3.3V

02 (2010-01-19) 2-17

Hi3520
2
Pin
mA) V
AD17 DVDD33 - - 3.3 3.3V
AD18 DVDD33 - - 3.3 3.3V
AD19 DVDD33 - - 3.3 3.3V
AD20 DVDD33 - - 3.3 3.3V
AD21 DVDD33 - - 3.3 3.3V
AD22 DVDD33 - - 3.3 3.3V
AD23 DVDD33 - - 3.3 3.3V
AC24 DVDD33 - - 3.3 3.3V
AB24 DVDD33 - - 3.3 3.3V
AB28 DVDD33 - - 3.3 3.3V
AA5 DVDD33 - - 3.3 3.3V
AA9 DVDD33 - - 3.3 3.3V
AA24 DVDD33 - - 3.3 3.3V
AA28 DVDD33 - - 3.3 3.3V
Y5 DVDD33 - - 3.3 3.3V
Y9 DVDD33 - - 3.3 3.3V
Y24 DVDD33 - - 3.3 3.3V
W9 DVDD33 - - 3.3 3.3V
W24 DVDD33 - - 3.3 3.3V
V9 DVDD33 - - 3.3 3.3V
U5 DVDD33 - - 3.3 3.3V
U9 DVDD33 - - 3.3 3.3V
T5 DVDD33 - - 3.3 3.3V
T9 DVDD33 - - 3.3 3.3V

2-18 02 (2010-01-19)

Hi3520
2
Pin
mA) V
M9 DVDD33 - - 3.3 3.3V
L9 DVDD33 - - 3.3 3.3V
K9 DVDD33 - - 3.3 3.3V
J5 DVDD33 - - 3.3 3.3V
H5 DVDD33 - - 3.3 3.3V
G5 DVDD33 - - 3.3 3.3V
J8 VSS - - -
V8 VSS - - -
W8 VSS - - -
AE24 VSS - - -
AE21 VSS - - -
AE20 VSS - - -
AE17 VSS - - -
AE16 VSS - - -
AE13 VSS - - -
AE12 VSS - - -
L25 VSS - - -
N25 VSS - - -
Y25 VSS - - -
AA25 VSS - - -
AD25 VSS - - -
AE25 VSS - - -
H25 VSS - - -

02 (2010-01-19) 2-19

Hi3520
2
Pin
mA) V
H23 VSS - - -
H21 VSS - - -
H19 VSS - - -
H13 VSS - - -
H11 VSS - - -
H8 VSS - - -
AM8 VSS - - -
AM13 VSS - - -
AM18 VSS - - -
AM23 VSS - - -
AM28 VSS - - -
AM32 VSS - - -
AK8 VSS - - -
AK12 VSS - - -
AK16 VSS - - -
AK20 VSS - - -
AK24 VSS - - -
AK27 VSS - - -
AK30 VSS - - -
AH8 VSS - - -
AH9 VSS - - -
AH12 VSS - - -
AH13 VSS - - -
AH16 VSS - - -

2-20 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AH17 VSS - - -
AH20 VSS - - -
AH21 VSS - - -
AH24 VSS - - -
AH25 VSS - - -
AH28 VSS - - -
AH32 VSS - - -
AG28 VSS - - -
AF1 VSS - - -
AF30 VSS - - -
AE3 VSS - - -
AD12 VSS - - -
AD24 VSS - - -
AD28 VSS - - -
AC1 VSS - - -
AC5 VSS - - -
AC28 VSS - - -
AC32 VSS - - -
AB5 VSS - - -
AA3 VSS - - -
AA21 VSS - - -
AA30 VSS - - -
Y13 VSS - - -
Y14 VSS - - -

02 (2010-01-19) 2-21

Hi3520
2
Pin
mA) V
Y15 VSS - - -
Y16 VSS - - -
Y17 VSS - - -
Y18 VSS - - -
Y19 VSS - - -
Y20 VSS - - -
Y28 VSS - - -
W1 VSS - - -
W5 VSS - - -
W13 VSS - - -
W14 VSS - - -
W15 VSS - - -
W16 VSS - - -
W17 VSS - - -
W18 VSS - - -
W19 VSS - - -
W20 VSS - - -
W28 VSS - - -
V5 VSS - - -
V13 VSS - - -
V14 VSS - - -
V15 VSS - - -
V16 VSS - - -
V17 VSS - - -

2-22 02 (2010-01-19)

Hi3520
2
Pin
mA) V
V18 VSS - - -
V19 VSS - - -
V20 VSS - - -
U3 VSS - - -
U13 VSS - - -
U14 VSS - - -
U15 VSS - - -
U16 VSS - - -
U17 VSS - - -
U18 VSS - - -
U19 VSS - - -
U20 VSS - - -
T13 VSS - - -
T14 VSS - - -
T15 VSS - - -
T16 VSS - - -
T17 VSS - - -
T18 VSS - - -
T19 VSS - - -
T20 VSS - - -
T31 VSS - - -
T32 VSS - - -
R1 VSS - - -
R5 VSS - - -

02 (2010-01-19) 2-23

Hi3520
2
Pin
mA) V
R13 VSS - - -
R14 VSS - - -
R15 VSS - - -
R16 VSS - - -
R17 VSS - - -
R18 VSS - - -
R19 VSS - - -
R20 VSS - - -
P3 VSS - - -
P5 VSS - - -
P13 VSS - - -
P14 VSS - - -
P15 VSS - - -
P16 VSS - - -
P17 VSS - - -
P18 VSS - - -
P19 VSS - - -
P20 VSS - - -
P28 VSS - - -
P29 VSS - - -
P32 VSS - - -
N13 VSS - - -
N14 VSS - - -
N15 VSS - - -

2-24 02 (2010-01-19)

Hi3520
2
Pin
mA) V
N16 VSS - - -
N17 VSS - - -
N18 VSS - - -
N19 VSS - - -
N20 VSS - - -
M12 VSS - - -
M21 VSS - - -
M30 VSS - - -
M31 VSS - - -
K28 VSS - - -
J3 VSS - - -
J9 VSS - - -
J24 VSS - - -
J28 VSS - - -
H1 VSS - - -
H2 VSS - - -
H30 VSS - - -
H31 VSS - - -
F3 VSS - - -
F5 VSS - - -
E1 VSS - - -
E5 VSS - - -
E6 VSS - - -
E9 VSS - - -

02 (2010-01-19) 2-25

Hi3520
2
Pin
mA) V
E10 VSS - - -
E11 VSS - - -
E14 VSS - - -
E15 VSS - - -
E19 VSS - - -
E20 VSS - - -
E21 VSS - - -
E24 VSS - - -
E25 VSS - - -
E28 VSS - - -
D4 VSS - - -
D26 VSS - - -
C3 VSS - - -
C6 VSS - - -
C10 VSS - - -
C16 VSS - - -
C27 VSS - - -
C31 VSS - - -
C32 VSS - - -
B2 VSS - - -
B6 VSS - - -
B10 VSS - - -
B14 VSS - - -
B16 VSS - - -

2-26 02 (2010-01-19)

Hi3520
2
Pin
mA) V
B20 VSS - - -
B25 VSS - - -
B29 VSS - - -
A1 VSS - - -
A14 VSS - - -
A20 VSS - - -
A25 VSS - - -
A29 VSS - - -
A32 VSS - - -
2.1.2 SIO
SIO 2-3
2-3 SIO
Pin
mA) V
P2 ACKOUT ISPU/O 4 - I2S PCM

audio codec

M5 SIO0DI IPU - - SIO0

N2 SIO0DO OT 4 - SIO0
N5 SIO0RCK ISPU/O 4 - I2S/PCM
N3 SIO0RFS ISPU/O 4 - I2S

ADC PCM

N4 SIO0XCK ISPU/O 4 - I2S/PCM
M4 SIO0XFS ISPU/O 4 - I2S

DAC PCM

02 (2010-01-19) 2-27

Hi3520
2
Pin
mA) V
P4 SIO1DI IPU - - SIO1

R3 SIO1RCK ISPU/O 4 - I2S/PCM
P1 SIO1RFS ISPU/O 4 - I2S

ADC PCM

R4 SIO2DI ISPU/O 4 - SIO2

N1 SIO2RCK ISPU/O 4 - I2S/PCM
R2 SIO2RFS ISPU/O 4 - I2S

ADC PCM

2.1.3 VDAC
VDAC 2-4
2-4 VDAC
Pin
mA) V
AG5 COMPDA - - 3.3 DAC0

C0
DAC
3.3V 0.01F
10uF
AH4 COMPDA - - 3.3 DAC1

C1
DAC
3.3V 0.01F
10uF
AJ1 DACVGA0 - - 3.3 DAC0 blue

B
AK1 DACVGA0 - - 3.3 DAC0 green

G CVBS

2-28 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AL1 DACVGA0 - - 3.3 DAC0 red

R CVBS

AM4 DACVGA1 - - 3.3 DAC1 Blue

B
AM3 DACVGA1 - - 3.3 DAC1 green

G
AM2 DACVGA1 - - 3.3 DAC1 red

R
AG4 RSETDAC - - 3.3 DAC0

0 a
DAC0 full-scale

AH5 RSETDAC - - 3.3 DAC1

1 a
DAC1 full-scale

AC8 VREFIND - - 3.3 DAC0

AC0
DAC
0.1F

AE10 VREFIND - - 3.3 DAC1

AC1
DAC
0.1F

a VREFIN(V) VREFDAC0
VREFDAC1 1.183VIOFS
37.5 1.2V 32mA
1.183%40.3/32mA = 1.49K
2.1.4 DDRA
DDRA 2-5

02 (2010-01-19) 2-29

Hi3520
2
2-5 DDRA
Pin
mA) V
A10 DDRA_AD - - 1.8 DDR A

R0
R1
R2
B18 DDRA_AD - - 1.8 DDR A
R3
B11 DDRA_AD - - 1.8 DDR A
R4
D18 DDRA_AD - - 1.8 DDR A
R5
R6
C17 DDRA_AD - - 1.8 DDR A
R7
R8
R9
R10
R11
R12
R13
A16 DDRA_BA - - 1.8 DDR A bank0
0
A17 DDRA_BA - - 1.8 DDR A bank1

1
B17 DDRA_BA - - 1.8 DDR A bank2

2
D13 DDRA_CA - - 1.8 DDR A

SN

2-30 02 (2010-01-19)

Hi3520
2
Pin
mA) V
C15 DDRA_CK - - 1.8 DDR A

E
B15 DDRA_CK - - 1.8 DDR A 0

N0
B13 DDRA_CK - - 1.8 DDR A 1

N1
A15 DDRA_CK - - 1.8 DDR A 0

P0
A13 DDRA_CK - - 1.8 DDR A 1

P1
D15 DDRA_CS - - 1.8 DDR A DDR2

N SDRAM

C24 DDRA_DQ - - 1.8 DDR A

0
D24 DDRA_DQ - - 1.8 DDR A
1
2
A26 DDRA_DQ - - 1.8 DDR A
3
B26 DDRA_DQ - - 1.8 DDR A
4
5
6
7
8
9
10
11

02 (2010-01-19) 2-31

Hi3520
2
Pin
mA) V

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

2-32 02 (2010-01-19)

Hi3520
2
Pin
mA) V

31
SN0
DDRDQ[7:0]

SN1
DDRDQ[15:8]

SN2
DDRDQ[23:16]

SN3
DDRDQ[31:24]

SP0
DDRDQ[7:0]

SP1
DDRDQ[15:8]

SP2
DDRDQ[23:16]

SP3
DDRDQ[31:24]
D25 DDRA_LD - - 1.8 DDR A

M0 DDRDQ[7:0]
D22 DDRA_UD - - 1.8 DDR A

M0 DDRDQ[15:8]
C11 DDRA_OD - - 1.8 DDR A ODT

T
D12 DDRA_RA - - 1.8 DDR A

SN
D11 DDRA_LD - - 1.8 DDR A

M1 DDRDQ[23:16]

02 (2010-01-19) 2-33

Hi3520
2
Pin
mA) V
A2 DDRA_UD - - 1.8 DDR A

M1 DDRDQ[31:24]
C14 DDRA_WE - - 1.8 DDR A

N
2.1.5 DDRB
DDRB 2-6
2-6 DDRB
Pin
mA) V
H28 DDRB_AD - - 1.8 DDR B

R0
N29 DDRB_AD - - 1.8 DDR B
R1
H32 DDRB_AD - - 1.8 DDR B
R2
M32 DDRB_AD - - 1.8 DDR B
R3
G30 DDRB_AD - - 1.8 DDR B
R4
R5
G31 DDRB_AD - - 1.8 DDR B
R6
L32 DDRB_AD - - 1.8 DDR B
R7
J29 DDRB_AD - - 1.8 DDR B
R8
L30 DDRB_AD - - 1.8 DDR B
R9
R10
K29 DDRB_AD - - 1.8 DDR B
R11

2-34 02 (2010-01-19)

Hi3520
2
Pin
mA) V

R12
R13
L31 DDRB_BA - - 1.8 DDR B bank0
0
L28 DDRB_BA - - 1.8 DDR B bank1

1
M29 DDRB_BA - - 1.8 DDR B bank2

2
J30 DDRB_CA - - 1.8 DDR B

SN
L29 DDRB_CK - - 1.8 DDR B

E
J32 DDRB_CK - - 1.8 DDR B 0

N0
J31 DDRB_CK - - 1.8 DDR B 0

P0
G32 DDRB_CS - - 1.8 DDR B DDR2

N SDRAM

E29 DDRB_DQ - - 1.8 DDR B

0
F28 DDRB_DQ - - 1.8 DDR B
1
2
E32 DDRB_DQ - - 1.8 DDR B
3
4
5
D30 DDRB_DQ - - 1.8 DDR B
6
7

02 (2010-01-19) 2-35

Hi3520
2
Pin
mA) V
B31 DDRB_DQ - - 1.8 DDR B

8
C29 DDRB_DQ - - 1.8 DDR B
9
A31 DDRB_DQ - - 1.8 DDR B
10
11
12
13
14
C28 DDRB_DQ - - 1.8 DDR B
15
SN0
DDRDQ[7:0]

SN1
DDRDQ[15:8]

SP0
DDRDQ[7:0]

SP1
DDRDQ[15:8]
G29 DDRB_LD - - 1.8 DDR B

M0 DDRDQ[7:0]
F32 DDRB_OD - - 1.8 DDR B ODT

T
H29 DDRB_RA - - 1.8 DDR B

SN
D27 DDRB_UD - - 1.8 DDR B

M0 DDRDQ[15:8]

2-36 02 (2010-01-19)

Hi3520
2
Pin
mA) V
K32 DDRB_WE - - 1.8 DDR B

N
2.1.6 EBI
EBI 2-7
2-7 EBI
Pin
mA) V
AK29 EBIADR0 O 8 - EBI ADR0
AM30 EBIADR1 O 8 - EBI ADR1
AM31 EBIADR2 O 8 - EBI ADR2
AL31 EBIADR3 O 8 - EBI ADR3
AJ29 EBIADR4 O 8 - EBI ADR4
AL32 EBIADR6 O 8 - EBI ADR6
AH29 EBIADR11 O 8 - EBI ADR11
AG29 EBIADR14 O 8 - EBI ADR14
AG31 EBIADR15 I/O 8 - EBI ADR15

02 (2010-01-19) 2-37

Hi3520
2
Pin
mA) V
AF29 EBIADR18 I/O 8 - EBI ADR18
AE29 EBIADR21 I/O 8 - EBI ADR21
AL27 EBIDQ0 I/O 8 - EBI DAT0
AJ27 EBIDQ2 I/O 8 - EBI DAT2
AK28 EBIDQ3 I/O 8 - EBI DAT3
AJ28 EBIDQ4 I/O 8 - EBI DAT4
AM29 EBIDQ6 I/O 8 - EBI DAT6
AL24 EBIWEN O 8 - EBI
AM26 NFALE O 4 - Nand Flash
AM25 NFCLE O 4 - Nand Flash
AK26 NFCS0N O 4 - Nand Flash 0

AM27 NFCS1N I/O 4 - Nand Flash 1

AK25 NFOEN O 8 - Nand Flash

2-38 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AJ26 NFRB IPU/O 4 - Nand Flash

0
1
Nand Flash
Flash

AJ25 SMICS0N O 4 - SMI 0

AL25 SMICS1N I/O 4 - SMI 1

AJ24 SMIOEN O 8 - SMI

AL26 EBIRDYN ISPU - - SMI Ready

2.1.7 GMAC
GMAC 2-8
2-8 GMAC
Pin
mA) V
D1 GCOL IPU/O 4 - GMAC
G3 GCRS IPU/O 4 - GMAC
F1 GRCLK IPU - - GMAC
H4 GRXD0 IPU - - GMAC DAT0
F2 GRXD1 IPU - - GMAC DAT1
H3 GRXD2 IPU - - GMAC DAT2
J4 GRXD3 IPU - - GMAC DAT3

02 (2010-01-19) 2-39

Hi3520
2
Pin
mA) V
E3 GRXDV IPU - - GMAC
F4 GTCLK IPU - - GMAC
E2 GTCLKOU IPU/O 8 - GMAC

T
D3 GTXD0 O 8 - GAMC DAT0
E4 GTXD1 O 8 - GAMC DAT1
C1 GTXD2 O 8 - GAMC DAT2
D2 GTXD3 O 8 - GAMC DAT3
G4 GTXEN O 8 - GMAC
C2 MDCK O 4 - MDIO
B1 MDIO IPU/O 4 - MDIO /
2.1.8 VO
VO 2-9
2-9 VO
Pin
mA) V
Y29 GPIO3_0 I/O 8 - GPIO

VOBDAT7 VO RGB
blue DAT7
W32 VO0CK I/O 8 -
W30 VO0DAT0 I/O 8 - DAT0
W29 VO0DAT1 I/O 8 - DAT1
V32 VO0DAT2 I/O 8 - DAT2

2-40 02 (2010-01-19)

Hi3520
2
Pin
mA) V
U29 VO0DAT6 I/O 8 - DAT6
U30 VO0DAT7 I/O 8 - DAT7
AA31 VO1CK I/O 8 -
AD29 VO1DAT0 OT 8 - DAT0
AD31 VO1DAT1 OT 8 - DAT1
AD30 VO1DAT2 ISPU/O 8 - DAT2
AD32 VO1DAT3 ISPU/O 8 - DAT3
AC29 VO1DAT4 ISPU/O 8 - DAT4
AC31 VO1DAT5 ISPU/O 8 - DAT5
AB29 VO1DAT6 ISPU/O 8 - DAT6
AC30 VO1DAT7 I/O 8 - DAT7
AB31 VO1DAT8 I/O 8 - DAT8
AB30 VO1DAT9 IPU/O 8 - DAT9
AB32 VO1DAT1 OT 8 -
0 DAT10
AA32 VO1DAT1 IPU/O 8 -

1 DAT11
AA29 VO1DAT1 IPU/O 8 -

2 DAT12
Y31 VO1DAT1 I/O 8 -

3 DAT13
Y32 VO1DAT1 I/O 8 -

4 DAT14
Y30 VO1DAT1 I/O 8 -

5 DAT15
W31 VORGBD I/O 8 - VO RGB

V

02 (2010-01-19) 2-41

Hi3520
2
2.1.9 PCI
PCI 2-10
2-10 PCI
Pin
mA) V
AL21 PCIAD0 I/O - - PCI 0
AM22 PCIAD1 I/O - - PCI 1
AJ20 PCIAD2 I/O - - PCI 2
AK19 PCIAD7 I/O - - PCI 7

2-42 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AK11 PCICBE0 I/O - - PCI

0
AL11 PCICBE1 I/O - - PCI

1
AM15 PCICBE2 I/O - - PCI

2
AL18 PCICBE3 I/O - - PCI

3
AM7 PCICLK I/O - - PCI
AK15 PCIDEVSE I/O - - PCI DEVSEL

LN
AJ9 PCIFRAM I/O - - PCI FRAME

EN
AK21 PCIGRAN I/O - - PCI 0
T0N
AJ21 PCIGRAN I/O - - PCI 1

T1N
AK22 PCIGRAN I/O - - PCI 2

T2N

02 (2010-01-19) 2-43

Hi3520
2
Pin
mA) V
AL22 PCIGRAN I/O - - PCI 3

T3N
AJ22 PCIGRAN I/O - - PCI 4

T4N
AL14 PCIIDSEL IS/O - - PCI IDSEL
AL8 PCIINTAN IS/O - - PCI INTA

AJ14 PCIIRDYN I/O - - PCI IRDY

AM19 PCIPAR I/O - - PCI PAR
AK18 PCIPERRN I/O - - PCI PERR

4.7k
AL19 PCIREQ0N IS/O - - PCI 0

AL23 PCIREQ1N IS/O - - PCI 1

AK23 PCIREQ2N IS/O - - PCI 2

AJ23 PCIREQ3N IS/O - - PCI 3

AM24 PCIREQ4N IS/O - - PCI 4

AJ8 PCIRSTN IS/O - - PCI
AJ18 PCISERRN I/O - - PCI SERR

4.7k
AL15 PCISTOPN I/O - - PCI STOP

AK14 PCITRDY I/O - - PCI TRDY

N

2-44 02 (2010-01-19)

Hi3520
2
2.1.10 SYS
SYS 2-11
2-11 SYS
Pin
mA) V
AJ6 RSTN ISPU - -

T30 TESTMOD ISPD - - ARM debug

E
0ARM
debug
1
AK7 WDGRST OT 4 -
OD
U31 XIN_24 - - - 24MHz

U32 XOUT_24 - - - 24MHz

2.1.11 I2C
I2C 2-12
2-12 I2C
Pin
mA) V
G1 SCL ISPU/O 4 - I2C OD PCB

G2 SDA ISPU/O 4 - I2C /OD

PCB
2.1.12 JTAG
JTAG 2-13

02 (2010-01-19) 2-45

Hi3520
2
2-13 JTAG
Pin
mA) V
R31 TCK ISPD - - JTAG
R29 TDI ISPU - - JTAG
R30 TDO OT 4 - JTAG
R32 TMS ISPU - - JTAG
T29 TRSTN ISPD - - JTAG
2.1.13 UART
UART 2-14
2-14 UART
Pin
mA) V
AM6 UCTSN1 IPU - - UART1
AL6 URTSN1 OT 4 - UART1

AK5 URXD0 IPU - - UART0
AJ7 URXD1 IPU - - UART1
AK6 UTXD0 OT 4 - UART0
AL7 UTXD1 OT 4 - UART1
2.1.14 USB
USB 2-15
2-15 USB
Pin
mA) V
J2 USBDM0 I/O - 3.3 USB 2.0 HOST 0 D-

2-46 02 (2010-01-19)

Hi3520
2
Pin
mA) V
L2 USBDM1 I/O - 3.3 USB 2.0 HOST 1 D-

J1 USBDP0 I/O - 3.3 USB 2.0 HOST 0 D+

L1 USBDP1 I/O - 3.3 USB 2.0 HOST 1 D+

K3 USBREXT I/O - 3.3 USB 2.0 HOST

2.1.15 VI
VI 2-16
2-16 VI
Pin
mA) V
AC2 VI0CK IPU - - VI0
AB2 VI0DAT0 IPU - - VI0 DAT0
AD1 VI0DAT2 IPU - - VI0 DAT2
AC4 VI0DAT4 IPU - - VI0 DAT4
AC3 VI0DAT5 IPU - - VI0 DAT5
AA4 VI0HS IPU/O 4 - VI0

AB1 VI0VS IPU/O 4 - VI0

AE1 VI1CK IPU - - VI1

02 (2010-01-19) 2-47

Hi3520
2
Pin
mA) V
AE2 VI1DAT0 IPU/O 4 - VI1 DAT0
AF2 VI1DAT1 IPU/O 4 - VI1 DAT1
AE4 VI1DAT2 IPU/O 4 - VI1 DAT2
AD4 VI1DAT3 IPU/O 4 - VI1 DAT3
AG1 VI1DAT5 IPU/O 4 - VI1 DAT5
AG2 VI1DAT7 IPU/O 4 - VI1 DAT7
T1 VI2CK IPU - - VI2
T2 VI2DAT0 IPU/O 4 - VI2 DAT0
U4 VI2DAT1 IPU/O 4 - VI2 DAT1
V3 VI2DAT4 IPU/O 4 - VI2 DAT4
T3 VI2HS IPU/O 4 - VI2

T4 VI2VS IPU/O 4 - VI2

W2 VI3CK IPU - - VI3
W3 VI3DAT0 IPU/O 4 - VI3 DAT0
Y1 VI3DAT1 IPU/O 4 - VI3 DAT1
W4 VI3DAT2 IPU/O 4 - VI3 DAT2

2-48 02 (2010-01-19)

Hi3520
2
Pin
mA) V
AA1 VI3DAT3 IPU/O 4 - VI3 DAT3
AA2 VI3DAT7 IPU/O 4 - VI3 DAT7
2.2
CPU
2.2.1 VI
VI 2-17
2-17 VI
Pin Pad 1 2

AA4 VI0HS reg0 URXD2 GPIO1_3
AB1 VI0VS reg1 UTXD2 GPIO1_4
AB2 VI0DAT0 reg2 VOUDAT8 -
AD1 VI0DAT2 reg4 VOUDAT10 -
AC4 VI0DAT4 reg6 VOUDAT12 -
AC3 VI0DAT5 reg7 VOUDAT13 -
AE2 VI1DAT0 reg10 GPIO4_0 VOUDAT0

02 (2010-01-19) 2-49

Hi3520
2
Pin Pad 1 2

AF2 VI1DAT1 reg11 GPIO4_1 VOUDAT1
AE4 VI1DAT2 reg12 GPIO4_2 VOUDAT2
AD4 VI1DAT3 reg13 GPIO4_3 VOUDAT3
AG1 VI1DAT5 reg15 GPIO4_5 VOUDAT5
AG2 VI1DAT7 reg17 GPIO4_7 VOUDAT7
T3 VI2HS reg18 URXD3 GPIO3_4
T4 VI2VS reg19 UTXD3 GPIO3_5
T2 VI2DAT0 reg20 GPIO5_0 -
U4 VI2DAT1 reg21 GPIO5_1 -
V3 VI2DAT4 reg24 GPIO5_4 -
W3 VI3DAT0 reg28 GPIO6_0 -
Y1 VI3DAT1 reg29 GPIO6_1 -
W4 VI3DAT2 reg30 GPIO6_2 -
AA1 VI3DAT3 reg31 GPIO6_3 -

2-50 02 (2010-01-19)

Hi3520
2
Pin Pad 1 2

AA2 VI3DAT7 reg35 GPIO6_7 -
VI 2-18
2-18 VI
GPIO1_3 I/O GPIO
GPIO1_4 I/O GPIO
GPIO3_4 I/O GPIO
GPIO3_5 I/O GPIO
GPIO4_0 I/O GPIO
GPIO4_1 I/O GPIO
GPIO4_2 I/O GPIO
GPIO4_3 I/O GPIO
GPIO4_4 I/O GPIO
GPIO4_5 I/O GPIO
GPIO4_6 I/O GPIO
GPIO4_7 I/O GPIO
GPIO5_0 I/O GPIO
GPIO5_1 I/O GPIO
GPIO5_2 I/O GPIO
GPIO5_3 I/O GPIO
GPIO5_4 I/O GPIO
GPIO5_5 I/O GPIO
GPIO5_6 I/O GPIO
GPIO5_7 I/O GPIO
GPIO6_0 I/O GPIO
GPIO6_1 I/O GPIO

02 (2010-01-19) 2-51

Hi3520
2
GPIO6_2 I/O GPIO
GPIO6_3 I/O GPIO
GPIO6_4 I/O GPIO
GPIO6_5 I/O GPIO
GPIO6_6 I/O GPIO
GPIO6_7 I/O GPIO
URXD2 I UART2
URXD3 I UART3
UTXD2 O UART2
UTXD3 O UART3
VOUDAT0 I 0
VOUDAT1 I 1
VOUDAT10 I 10
VOUDAT11 I 11
VOUDAT12 I 12
VOUDAT13 I 13
VOUDAT14 I 14
VOUDAT15 I 15
VOUDAT2 I 2
VOUDAT3 I 3
VOUDAT4 I 4
VOUDAT5 I 5
VOUDAT6 I 6
VOUDAT7 I 7
VOUDAT8 I 8
VOUDAT9 I 9

2-52 02 (2010-01-19)

Hi3520
2
2.2.2 VO
VO 2-19
2-19 VO
Pin Pad 1 2 3

W32 VO0CK reg36 GPIO1_5 VORDAT0 -
W30 VO0DAT0 reg37 GPIO2_0 VORDAT1 -
W29 VO0DAT1 reg38 GPIO2_1 VORDAT2 -
V32 VO0DAT2 reg39 GPIO2_2 VORDAT3 -
U29 VO0DAT6 reg43 GPIO2_6 VORDAT7 -
U30 VO0DAT7 reg44 GPIO2_7 VOGDAT0 -
AA31 VO1CK reg45 GPIO7_2 SDIOCK -
AD29 VO1DAT0 reg46 VGA1HS - -
AD31 VO1DAT1 reg47 VGA1VS - -
AD30 VO1DAT2 reg48 SDIOCMD VOGDAT1 -
AD32 VO1DAT3 reg49 SDIODAT0 VOGDAT2 -
AC29 VO1DAT4 reg50 SDIODAT1 VOGDAT3 -
AC31 VO1DAT5 reg51 SDIODAT2 VOGDAT4 -
AB29 VO1DAT6 reg52 SDIODAT3 VOGDAT5 -
AC30 VO1DAT7 reg53 GPIO1_6 VOGDAT6 -
AB31 VO1DAT8 reg54 SPICK VOGDAT7 -
AB30 VO1DAT9 reg55 SPIDI VOBDAT0 -
AB32 VO1DAT10 reg56 SPIDO VOBDAT1 -

02 (2010-01-19) 2-53

Hi3520
2
Pin Pad 1 2 3

AA32 VO1DAT11 reg57 SPICSN0 VOBDAT2 -
AA29 VO1DAT12 reg58 SPICSN1 VOBDAT3 -
Y31 VO1DAT13 reg59 GPIO7_4 VOBDAT4 VGA0HS
Y32 VO1DAT14 reg60 GPIO7_5 VOBDAT5 VGA0VS
Y30 VO1DAT15 reg61 GPIO1_7 VOBDAT6 -
Y29 GPIO3_0 reg62 VOBDAT7 - -
W31 VORGBDV reg82 GPIO7_3 - -
VO 2-20
2-20 VO
GPIO1_5 I/O GPIO
GPIO1_6 I/O GPIO
GPIO1_7 I/O GPIO
GPIO2_0 I/O GPIO
GPIO2_1 I/O GPIO
GPIO2_2 I/O GPIO
GPIO2_3 I/O GPIO
GPIO2_4 I/O GPIO
GPIO2_5 I/O GPIO
GPIO2_6 I/O GPIO
GPIO2_7 I/O GPIO
GPIO7_2 I/O GPIO
GPIO7_3 I/O GPIO
GPIO7_4 I/O GPIO
GPIO7_5 I/O GPIO

2-54 02 (2010-01-19)

Hi3520
2
SDIOCK O SDIO/MMC
SDIOCMD I/O SDIO/MMC
SDIODAT0 I/O SDIO/MMC DAT0
SPICK I/O SPI
SPICSN0 I/O SPI 0
SPICSN1 I/O SPI 1
SPIDI I SPI
SPIDO O SPI
VGA0HS O VGA0
VGA0VS O VGA0
VGA1HS O VGA1
VGA1VS O VGA1
VOBDAT0 O VO RGB blue DAT0
VOGDAT0 O VO RGB green DAT0

02 (2010-01-19) 2-55

Hi3520
2
VORDAT0 O VO RGB red DAT0
2.2.3 I2C
I2C 2-21
2-21 I2C
Pin Pad 1
G2 SDA reg63 GPIO0_0
G1 SCL reg64 GPIO0_1
I2C 2-22
2-22 I2C
GPIO0_0 I/O GPIO
GPIO0_1 I/O GPIO
2.2.4 SIO
SIO 2-23

2-56 02 (2010-01-19)

Hi3520
2
2-23 SIO
Pin Pad 1 2

M4 SIO0XFS reg65 GPIO0_2 -
N4 SIO0XCK reg66 GPIO0_3 -
P2 ACKOUT reg67 GPIO0_4 -
R4 SIO2DI reg68 GPIO0_5 SIO1DO
R2 SIO2RFS reg69 GPIO0_6 SIO1XFS
N1 SIO2RCK reg70 GPIO0_7 SIO1XCK
SIO 2-24
2-24 SIO
GPIO0_2 I/O GPIO
GPIO0_3 I/O GPIO
GPIO0_4 I/O GPIO
GPIO0_5 I/O GPIO
GPIO0_6 I/O GPIO
GPIO0_7 I/O GPIO
SIO1DO O SIO 1
SIO1XCK I/O I2S/PCM
SIO1XFS I/O I2S DAC

PCM
2.2.5 EBI
EBI 2-25

02 (2010-01-19) 2-57

Hi3520
2
2-25 EBI
Pin Pad 1
AL25 SMICS1N reg71 GPIO3_2
AL26 EBIRDYN reg74 IRRCV
AM27 NFCS1N reg72 GPIO3_3
AJ26 NFRB reg73 GPIO3_1
EBI 2-26
2-26 EBI
GPIO3_1 I/O GPIO
GPIO3_2 I/O GPIO
GPIO3_3 I/O GPIO
2.2.6 GMAC
GMAC 2-27
2-27 GMAC
Pin Pad 1
E2 GTCLKOUT reg75 GPIO1_0
D1 GCOL reg76 GPIO1_1
G3 GCRS reg77 GPIO1_2
GMAC 2-28
2-28 GMAC
GPIO1_0 I/O GPIO
GPIO1_1 I/O GPIO

2-58 02 (2010-01-19)

Hi3520
2
GPIO1_2 I/O GPIO
IRRCV I
2.2.7 PCI
PCI 2-29
2-29 PCI
Pin Pad 1

AJ23 PCIREQ3N reg78 GPIO3_6
AM24 PCIREQ4N reg79 GPIO3_7
AL22 PCIGRANT3N reg80 GPIO7_0
AJ22 PCIGRANT4N reg81 GPIO7_1
PCI 2-30
2-30 PCI
GPIO3_6 I/O GPIO
GPIO3_7 I/O GPIO
GPIO7_0 I/O GPIO
GPIO7_1 I/O GPIO
2.3
2.3.1 EBI
EBI 2-31

02 (2010-01-19) 2-59

Hi3520
2
2-31 power_on==0b1

2-31 EBI
Pin Pad 1
(power_on==0b1)
AG31 EBIADR15 NFECC0
AG30 EBIADR16 NFECC1
AG32 EBIADR17 NFNUM0
AF29 EBIADR18 NFNUM1
AF32 EBIADR19 NFPAGE0
AF31 EBIADR20 NFPAGE1
AE29 EBIADR21 FUNSEL0
AE31 EBIADR22 FUNSEL1
AE30 EBIADR23 BOOTSEL0
AE32 EBIADR24 BOOTSEL1
EBI 2-32
2-32 EBI
NFECC0 I NFECC1 Nand Flash

boot ECC
{NFECC1, NFECC0}
00
011bit
104bit
118bit

2-60 02 (2010-01-19)

Hi3520
2
NFECC1 I NFECC0 Nand Flash

boot ECC
{NFECC1, NFECC0}
00
011bit
104bit
118bit
NFNUM0 I NFNUM1 Nand

Flash boot
{NFNUM1, NFNUM0}
003
014
105
116
NFNUM1 I NFNUM0 Nand

Flash boot
{NFNUM1, NFNUM0}
003
014
105
116
NFPAGE0 I NFPAGE1 Nand

Flash boot
{NFPAGE1, NFPAGE0}
012KB
104KB

NFPAGE1 I NFPAGE0 Nand

Flash boot
{NFPAGE1, NFPAGE0}
012KB
104KB

02 (2010-01-19) 2-61

Hi3520
2
FUNSEL0 I FUNSEL1 ARM debug

{FUNSEL1,FUNSEL0}
00debug ARM1176
10debug ARM926
01debug ARM1176+ARM926
11
FUNSEL1 I FUNSEL0 ARM debug

{FUNSEL1, FUNSEL0}
00debug ARM1176
10debug ARM926
11
BOOTSEL0 I BOOTSEL1
{BOOTSEL1, BOOTSEL0}
00 Nor Flash
01 Nand Flash
1X DDR
BOOTSEL1 I BOOTSEL0
{BOOTSEL1, BOOTSEL0}
00 Nor Flash
01 Nand Flash
1X DDR
2.3.2 PCI
PCI 2-33
2-33 pcimode==0b1 periphctrl11[pci_mode] 1
2-33 PCI
Pin Pad 1
(pcimode == 0b1)
AL14 PCIIDSEL PCIINTBN

2-62 02 (2010-01-19)

Hi3520
2
Pin Pad 1
(pcimode == 0b0)
AL19 PCIREQ0N PCIGRANT_SLAVEN
AK21 PCIGRANT0N PCIREQ_SLAVEN
PCI 2-34
2-34 PCI
PCIINTBN I PCI INTB
PCIGRANT_SLAVEN I PCI
PCIREQ_SLAVEN O PCI
2.4 IO Config
IO Config 2-35
2-35 IO Config 0x200F_0000
0x0000 reg0 VI0HS 2-67
0x0004 reg1 VI0VS 2-68
0x0008 reg2 VI0DAT0 2-68
0x000C reg3 VI0DAT1 2-69
0x0010 reg4 VI0DAT2 2-69
0x0014 reg5 VI0DAT3 2-70
0x0018 reg6 VI0DAT4 2-70
0x0020 reg8 VI0DAT6 2-71
0x0024 reg9 VI0DAT7 2-72
0x0028 reg10 VI1DAT0 2-72

02 (2010-01-19) 2-63

Hi3520
2
0x0030 reg12 VI1DAT2 2-73
0x0034 reg13 VI1DAT3 2-74
0x0038 reg14 VI1DAT4 2-74
0x0040 reg16 VI1DAT6 2-75
0x0044 reg17 VI1DAT7 2-76
0x0048 reg18 VI2HS 2-76
0x004C reg19 VI2VS 2-77
0x0050 reg20 VI2DAT0 2-77
0x0054 reg21 VI2DAT1 2-78
0x0058 reg22 VI2DAT2 2-78
0x0060 reg24 VI2DAT4 2-79
0x0064 reg25 VI2DAT5 2-80
0x0068 reg26 VI2DAT6 2-80
0x0070 reg28 VI3DAT0 2-81
0x0074 reg29 VI3DAT1 2-82
0x0078 reg30 VI3DAT2 2-82
0x0080 reg32 VI3DAT4 2-83
0x0084 reg33 VI3DAT5 2-84
0x0088 reg34 VI3DAT6 2-84
0x0090 reg36 VO0CK 2-85
0x0094 reg37 VO0DAT0 2-86
0x0098 reg38 VO0DAT1 2-86
0x009C reg39 VO0DAT2 2-87

2-64 02 (2010-01-19)

Hi3520
2
0x00A0 reg40 VO0DAT3 2-87
0x00AC reg43 VO0DAT6 2-89
0x00B0 reg44 VO0DAT7 2-89
0x00B4 reg45 VO1CK 2-90
0x00B8 reg46 VO1DAT0 2-90
0x00BC reg47 VO1DAT1 2-91
0x00C0 reg48 VO1DAT2 2-91
0x00CC reg51 VO1DAT5 2-93
0x00D0 reg52 VO1DAT6 2-93
0x00DC reg55 VO1DAT9 2-95
0x00E0 reg56 VO1DAT10 2-95
0x00E4 reg57 VO1DAT11 2-96
0x00E8 reg58 VO1DAT12 2-96
0x00EC reg59 VO1DAT13 2-97
0x00F0 reg60 VO1DAT14 2-97
0x00F4 reg61 VO1DAT15 2-98
0x00F8 reg62 GPIO3_0 2-98
0x00FC reg63 SDA 2-99
0x0100 reg64 SCL 2-99
0x0104 reg65 SIO0XFS 2-100
0x0108 reg66 SIO0XCK 2-100
0x010C reg67 ACKOUT 2-101
0x0110 reg68 SIO2DI 2-101

02 (2010-01-19) 2-65

Hi3520
2
0x0114 reg69 SIO2RFS 2-102
0x0118 reg70 SIO2RCK 2-102
0x011C reg71 SMICS1N 2-103
0x0120 reg72 NFCS1N 2-103
0x0124 reg73 NFRB 2-104
0x0128 reg74 EBIRDYN 2-104
0x012C reg75 GTCLKOUT 2-105
0x0130 reg76 GCOL 2-105
0x0134 reg77 GCRS 2-106
0x0138 reg78 PCIREQ3N 2-106
0x013C reg79 PCIREQ4N 2-107
0x0140 reg80 PCIGRANT3N 2-107
0x0144 reg81 PCIGRANT4N 2-108
0x0148 reg82 VORGBDV 2-108
2.5
reg0
VI0HS
Offset Address Register Name Total Reset Value

0x0000 reg0 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg0
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access Name Description
VI0HS
[1:0] RW reg0
00VI0HS

2-66 02 (2010-01-19)

Hi3520
2
01URXD2
10GPIO1_3

reg1
VI0VS

0x0004 reg1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg1
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0VS
00VI0VS
[1:0] RW reg1 01UTXD2
10GPIO1_4

reg2
VI0DAT0

0x0008 reg2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg2
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT0
[0] RW reg2
0VI0DAT0

02 (2010-01-19) 2-67

Hi3520
2
1VOUDAT8
reg3
VI0DAT1

0x000C reg3 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg3
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT1
[0] RW reg3 0VI0DAT1
1VOUDAT9
reg4
VI0DAT2

0x0010 reg4 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg4
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT2
1VOUDAT10

2-68 02 (2010-01-19)

Hi3520
2
reg5
VI0DAT3

0x0014 reg5 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg5
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT3
1VOUDAT11
reg6
VI0DAT4

0x0018 reg6 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg6
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT4
1VOUDAT12
reg7
VI0DAT5

02 (2010-01-19) 2-69

Hi3520
2

0x001C reg7 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg7
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT5
1VOUDAT13
reg8
VI0DAT6

0x0020 reg8 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg8
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT6
1VOUDAT14
reg9
VI0DAT7

2-70 02 (2010-01-19)

Hi3520
2

0x0024 reg9 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg9
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI0DAT7
1VOUDAT15
reg10
VI1DAT0

0x0028 reg10 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg10
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT0
00VI1DAT0
[1:0] RW reg10 01GPIO4_0
10VOUDAT0

reg11
VI1DAT1

02 (2010-01-19) 2-71

Hi3520
2

0x002C reg11 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg11
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT1
00VI1DAT1
[1:0] RW reg11 01GPIO4_1
10VOUDAT1

reg12
VI1DAT2

0x0030 reg12 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg12
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT2
00VI1DAT2
[1:0] RW reg12 01GPIO4_2
10VOUDAT2

reg13
VI1DAT3

2-72 02 (2010-01-19)

Hi3520
2

0x0034 reg13 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg13
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT3
00VI1DAT3
[1:0] RW reg13 01GPIO4_3
10VOUDAT3

reg14
VI1DAT4

0x0038 reg14 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg14
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT4
00VI1DAT4
[1:0] RW reg14 01GPIO4_4
10VOUDAT4

reg15
VI1DAT5

02 (2010-01-19) 2-73

Hi3520
2

0x003C reg15 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg15
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT5
00VI1DAT5
[1:0] RW reg15 01GPIO4_5
10VOUDAT5

reg16
VI1DAT6

0x0040 reg16 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg16
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT6
00VI1DAT6
[1:0] RW reg16 01GPIO4_6
10VOUDAT6

reg17
VI1DAT7

2-74 02 (2010-01-19)

Hi3520
2

0x0044 reg17 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg17
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI1DAT7
00VI1DAT7
[1:0] RW reg17 01GPIO4_7
10VOUDAT7

reg18
VI2HS

0x0048 reg18 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg18
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2HS
00VI2HS
[1:0] RW reg18 01URXD3
10GPIO3_4

reg19
VI2VS

02 (2010-01-19) 2-75

Hi3520
2

0x004C reg19 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg19
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2VS
00VI2VS
[1:0] RW reg19 01UTXD3
10GPIO3_5

reg20
VI2DAT0

0x0050 reg20 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg20
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT0
1GPIO5_0
reg21
VI2DAT1

2-76 02 (2010-01-19)

Hi3520
2

0x0054 reg21 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg21
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT1
1GPIO5_1
reg22
VI2DAT2

0x0058 reg22 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg22
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT2
1GPIO5_2
reg23
VI2DAT3

02 (2010-01-19) 2-77

Hi3520
2

0x005C reg23 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg23
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT3
1GPIO5_3
reg24
VI2DAT4

0x0060 reg24 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg24
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT4
1GPIO5_4
reg25
VI2DAT5

2-78 02 (2010-01-19)

Hi3520
2

0x0064 reg25 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg25
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT5
1GPIO5_5
reg26
VI2DAT6

0x0068 reg26 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg26
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT6
1GPIO5_6
reg27
VI2DAT7

02 (2010-01-19) 2-79

Hi3520
2

0x006C reg27 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg27
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI2DAT7
1GPIO5_7
reg28
VI3DAT0

0x0070 reg28 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg28
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT0
1GPIO6_0
reg29
VI3DAT1

2-80 02 (2010-01-19)

Hi3520
2

0x0074 reg29 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg29
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT1
1GPIO6_1
reg30
VI3DAT2

0x0078 reg30 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg30
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT2
1GPIO6_2
reg31
VI3DAT3

02 (2010-01-19) 2-81

Hi3520
2

0x007C reg31 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg31
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT3
1GPIO6_3
reg32
VI3DAT4

0x0080 reg32 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg32
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT4
1GPIO6_4
reg33
VI3DAT5

2-82 02 (2010-01-19)

Hi3520
2

0x0084 reg33 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg33
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT5
1GPIO6_5
reg34
VI3DAT6

0x0088 reg34 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg34
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT6
1GPIO6_6
reg35
VI3DAT7

02 (2010-01-19) 2-83

Hi3520
2

0x008C reg35 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg35
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI3DAT7
1GPIO6_7
reg36
VO0CK

0x0090 reg36 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg36
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0CK
00GPIO1_5
[1:0] RW reg36 01VO0CK
10VORDAT0

reg37
VO0DAT0

2-84 02 (2010-01-19)

Hi3520
2

0x0094 reg37 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg37
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT0
00GPIO2_0
[1:0] RW reg37 01VO0DAT0
10VORDAT1

reg38
VO0DAT1

0x0098 reg38 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg38
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT1
00GPIO2_1
10VORDAT2

reg39
VO0DAT2

02 (2010-01-19) 2-85

Hi3520
2

0x009C reg39 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg39
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT2
00GPIO2_2
10VORDAT3

reg40
VO0DAT3

0x00A0 reg40 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg40
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT3
00GPIO2_3
10VORDAT4

reg41
VO0DAT4

2-86 02 (2010-01-19)

Hi3520
2

0x00A4 reg41 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg41
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT4
00GPIO2_4
10VORDAT5

reg42
VO0DAT5

0x00A8 reg42 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg42
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT5
00GPIO2_5
10VORDAT6

reg43
VO0DAT6

02 (2010-01-19) 2-87

Hi3520
2

0x00AC reg43 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg43
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT6
00GPIO2_6
10VORDAT7

reg44
VO0DAT7

0x00B0 reg44 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg44
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO0DAT7
00GPIO2_7
10VOGDAT0

reg45
VO1CK

2-88 02 (2010-01-19)

Hi3520
2

0x00B4 reg45 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg45
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1CK
00GPIO7_2
[1:0] RW reg45 01VO1CK
10SDIOCK

reg46
VO1DAT0

0x00B8 reg46 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg46
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT0
[0] RW reg46 0VGA1HS
1VO1DAT0
reg47
VO1DAT1

02 (2010-01-19) 2-89

Hi3520
2

0x00BC reg47 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg47
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT1
[0] RW reg47 0VGA1VS
1VO1DAT1
reg48
VO1DAT2

0x00C0 reg48 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg48
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT2
00SDIOCMD
10VOGDAT1

reg49
VO1DAT3

2-90 02 (2010-01-19)

Hi3520
2

0x00C4 reg49 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg49
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT3
00SDIODAT0
10VOGDAT2

reg50
VO1DAT4

0x00C8 reg50 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg50
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT4
00SDIODAT1
10VOGDAT3

reg51
VO1DAT5

02 (2010-01-19) 2-91

Hi3520
2

0x00CC reg51 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg51
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT5
00SDIODAT2
10VOGDAT4

reg52
VO1DAT6

0x00D0 reg52 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg52
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT6
00SDIODAT3
10VOGDAT5

reg53
VO1DAT7

2-92 02 (2010-01-19)

Hi3520
2

0x00D4 reg53 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg53
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT7
00GPIO1_6
10VOGDAT6

reg54
VO1DAT8

0x00D8 reg54 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg54
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT8
00SPICK
10VOGDAT7

reg55
VO1DAT9

02 (2010-01-19) 2-93

Hi3520
2

0x00DC reg55 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg55
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT9
00SPIDI
10VOBDAT0

reg56
VO1DAT10

0x00E0 reg56 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg56
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT10
00SPIDO
10VOBDAT1

reg57
VO1DAT11

2-94 02 (2010-01-19)

Hi3520
2

0x00E4 reg57 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg57
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT11
00SPICSN0
10VOBDAT2

reg58
VO1DAT12

0x00E8 reg58 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg58
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT12
00SPICSN1
10VOBDAT3

reg59
VO1DAT13

02 (2010-01-19) 2-95

Hi3520
2

0x00EC reg59 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg59
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT13
00GPIO7_4
10VOBDAT4
11VGA0HS
reg60
VO1DAT14

0x00F0 reg60 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg60
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT14
00GPIO7_5
10VOBDAT5
11VGA0VS
reg61
VO1DAT15

2-96 02 (2010-01-19)

Hi3520
2

0x00F4 reg61 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg61
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VO1DAT15
00GPIO1_7
10VOBDAT6

reg62
GPIO3_0

0x00F8 reg62 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg62
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO3_0
[0] RW reg62 0GPIO3_0
1VOBDAT7
reg63
SDA

02 (2010-01-19) 2-97

Hi3520
2

0x00FC reg63 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg63
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDA
[0] RW reg63 0SDA
1GPIO0_0
reg64
SCL

0x0100 reg64 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg64
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCL
[0] RW reg64 0SCL
1GPIO0_1
reg65
SIO0XFS

2-98 02 (2010-01-19)

Hi3520
2

0x0104 reg65 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg65
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO0XFS
[0] RW reg65 0SIO0XFS
1GPIO0_2
reg66
SIO0XCK

0x0108 reg66 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg66
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO0XCK
[0] RW reg66 0SIO0XCK
1GPIO0_3
reg67
ACKOUT

02 (2010-01-19) 2-99

Hi3520
2

0x010C reg67 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg67
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ACKOUT
1ACKOUT
reg68
SIO2DI

0x0110 reg68 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg68
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO2DI
00GPIO0_5
[1:0] RW reg68 01SIO2DI
10SIO1DO

reg69
SIO2RFS

2-100 02 (2010-01-19)

Hi3520
2

0x0114 reg69 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg69
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO2RFS
00GPIO0_6
[1:0] RW reg69 01SIO2RFS
10SIO1XFS

reg70
SIO2RCK

0x0118 reg70 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg70
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO2RCK
00GPIO0_7
[1:0] RW reg70 01SIO2RCK
10SIO1XCK

reg71
SMICS1N

02 (2010-01-19) 2-101

Hi3520
2

0x011C reg71 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg71
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SMICS1N
1SMICS1N
reg72
NFCS1N

0x0120 reg72 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg72
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NFCS1N
1NFCS1N
reg73
NFRB

2-102 02 (2010-01-19)

Hi3520
2

0x0124 reg73 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg73
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NFRB
[0] RW reg73 0NFRB
1GPIO3_1
reg74
EBIRDYN

0x0128 reg74 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg74
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EBIRDYN
[0] RW reg74 0EBIRDYN
1IRRCV
reg75
GTCLKOUT

02 (2010-01-19) 2-103

Hi3520
2

0x012C reg75 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg75
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTCLKOUT
1GTCLKOUT
reg76
GCOL

0x0130 reg76 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg76
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GCOL
[0] RW reg76 0GCOL
1GPIO1_1
reg77
GCRS

2-104 02 (2010-01-19)

Hi3520
2

0x0134 reg77 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg77
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GCRS
[0] RW reg77 0GCRS
1GPIO1_2
reg78
PCIREQ3N

0x0138 reg78 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg78
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCIREQ3N
1PCIREQ3N
reg79
PCIREQ4N

02 (2010-01-19) 2-105

Hi3520
2

0x013C reg79 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg79
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCIREQ4N
1PCIREQ4N
reg80
PCIGRANT3N

0x0140 reg80 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg80
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCIGRANT3N
1PCIGRANT3N
reg81
PCIGRANT4N

2-106 02 (2010-01-19)

Hi3520
2

0x0144 reg81 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg81
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCIGRANT4N
1PCIGRANT4N
reg82
VORGBDV

0x0148 reg82 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg82
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VORGBDV
1VORGBDV
2.6

02 (2010-01-19) 2-107

Hi3520
2
2.7
3.4
2.8
2.8.1 DC/AC
DC/AC 2-36 2-37
2-36 DC DVDD33=3.3V
VIH 2.0 - 5.5 V -
VIL 0.3 - 0.8 V -
IL - - !10 A -
IOZ - - !10 A -
VOL - - 0.4 V -
RPU 63 92 142 k -
RPD 57 91 159 k -
2-37 DC DVDD18=1.8V
Vref 0.49DVD 0.50DVD 0.51DVD V -

D18 D18 D18
VIH (dc) Vref+0.125 - DVDD18+ V -
0.3
VIL(dc) 0.3 - Vref0.125 V -
IOH(dc) |13.4| - - mA Voh(dc)

=1.42V
IOL(dc) 13.4 - - mA Vol(dc)=
0.28V
VIH (ac) Vref+0.25 - - V -
VIL(ac) - - Vref-0.25 V -

2-108 02 (2010-01-19)

Hi3520
2
RTT -30% 150 +30% Ohm -

0.5*DVDD18 -30% 75 +30%
ODT -30% 50 +30%
VTT INT -2.0% 0.5*DVDD +2.0% V -
18
ILS -1.0 - 1.0 uA
SSTL

2.8.2
2-38
2-38
TOPT 20 - 85
TS 20 - 105
TJ 40 - 125
DVDD10 Core 0.95 1 1.1 V
DVDD33 I/O 3.135 3.3 3.6 V
DVDD18 DDR I/O 1.7 1.8 1.9 V
VREF DDR 0.85 0.9 0.95 V
AVDD33_PLL PLL 3.135 3.3 3.6 V
DVDD10_PLL PLL 0.95 1 1.1 V
AVDD33_USB USB 3.135 3.3 3.465 V
DVDD10_USB USB 0.95 1 1.05 V
AVDD33_VDAC VDAC 3.135 3.3 3.6 V
DVDD10_DAC VDAC 0.95 1 1.1 V
DVDD33_DAC VDAC 3.0 3.3 3.6 V

02 (2010-01-19) 2-109

Hi3520
2
2.9 PCB
PCB Hi3520
2.10
2.10.1
2-1
2-1
2.10.2 DDR2
2.10.2.1
dqs_out dq_out
dqs_out dq_out tDS tDH DDR2-
800 tDS=0.50nstDH=0.125ns
dqs_out DDR CKP/CKN dq_out 2-2

2-110 02 (2010-01-19)

Hi3520
2
2-2 dqs_out dq_out
CKP
CKN
dqs_out
tDH
tDS
dq_out
dqs_out ck
dqs_out ck tDSS tDSH
tCK%0.2 2-3
2-3 dqs_out ck
CKP
CKN
dqs_out
cmd/addr ck
cmd/addr ck 2-4
2-4 cmd/addr ck
CKP
CKN
tIS tIH
cmd/addr
2.10.2.2
cmd/addr ck
2.10.2.1 cmd/addr ck

02 (2010-01-19) 2-111

Hi3520
2
dqs_in dq_in
DDR2 SDRAM DQS CK tDQSCK
0.35nstDQSQ dq dqs dq
dqs 0.2nstQHS dq dqs
0.3ns
DDR2 SDRAM 2-5
2-5 DDR2 SDRAM
CKP
CKN
tDQSCK
dqs_in
tQHS
tDQSQ
dq_in
2.10.2.3
DDR PHY Hi3520 DDR2-800
2-39 2-41
2-39 Clock Parameters
Memory clock frequency 400.00 MHz

PLL clock jitter 0.200 ns
PLL duty cycle 45.000 %
CLK Skew 0.200 ns
2-40 Memory Device Parameters
Memory Type DDR2-800 -

tDSS: DQS falling edge-CK setup time 0.2 Tck
tDSH: DQS falling edge-CK hold time 0.2 Tck
tDS: DQ/DM-DQS setup time 0.050 ns
tDH: DQ/DM-DQS hold time 0.125 ns

2-112 02 (2010-01-19)

Hi3520
2
DQS-DQ Skew, tDQSQ 0.200 ns

Data hold Skew Factor, tQHS 0.400 ns
Adr/Cmd Setup time, tIS 0.175 ns
Adr/Cmd Hold time, tIH 0.250 ns
tDQSCK: DQS output access time from CKP/CKN (min) -0.350 ns
tDQSCK: DQS output access time from CKP/CKN (max) 0.350 ns
2-41 Package/Board Parameters
Package trace skew (max/min) 0.060 ns

Board trace length mismatch (For Dqs/Dq) 0.050 ns
Board trace length mismatch (For others) 0.100 ns
Board and Package Uncertainty(Output) 0.360 ns
Board and Package Uncertainty(Input) 0.360 ns
ASIC Skew 0.200 ns
2.10.3 GMAC
MII PHYPhysical Layer Etity Sublayer MII

MII
MII 100Mbit/s 2-6
2-6 MII 100Mbit/s
40ns
PHY_RXC
PHY_CRS
PHY_RXDV
Thd
Tsu
PHY_RXD

02 (2010-01-19) 2-113

Hi3520
2
MII 10Mbit/s 2-7
2-7 MII 10Mbit/s
400ns
PHY_RXC
PHY_CRS
PHY_RXDV
Thd
Tsu
PHY_RXD
MII
MII 100Mbit/s 2-8
2-8 MII 100Mbit/s
40ns
PHY_TXC
PHY_TXEN
Tsu Thd
PHY_TXD
PHY_CRS
MII 10Mbit/s 2-9
2-9 MII 10Mbit/s
400 ns
PHY_TXC
PHY_TXEN
Tsu Thd
PHY_TXD
PHY_CRS

2-114 02 (2010-01-19)

Hi3520
2
MII
MII 2-42
2-42 MII
MII TsuRX PHY_RXDV 10 - ns

PHY_RXD[3:0]
MII ThdRX PHY_RXDV 10 - ns

PHY_RXD[3:0]
MII TsuTX PHY_TXEN 6 - ns

PHY_TXD[3:0]
MII ThdTX PHY_TXEN 2 - ns

PHY_TXD[3:0]
RGMII
RGMII 2-10
2-10 RGMII
PHY_GRXC
Thd Thd
Tsu Tsu
PHY_GRXD
RGMII
RGMII 2-11
2-11 RGMII
PHY_TXD/PHY
_TXEN
Thd Thd
Tsu Tsu
PHY_GTXC

02 (2010-01-19) 2-115

Hi3520
2
RGMII
2-43 RGMII
RGMII TsuRX PHY_RXDV 0.8 - ns

PHY_RXD[3:0]
RGMII ThdRX PHY_RXDV 1.2 - ns

PHY_RXD[3:0]
RGMII TsuTX PHY_TXEN -0.7 0.7 ns

PHY_TXD[3:0]
RGMII ThdTX PHY_TXEN -0.7 0.7 ns

PHY_TXD[3:0]
MDIO
MDIO 2-12
2-12 MDIO
ETH_MDCK
ETH_MDIO
(Into Chip)
ETH_MDIO
(Out of Chip)
mdata z 1 0 1 0 0 1 0 1 0
MDIO
MDIO 2-13
2-13 MDIO
ETH_MDCK
ETH_MDIO
(Out of Chip)
mdata z 0 1 0 1 0 1 0 1 0 z
MDIO
MDIO 2-14

2-116 02 (2010-01-19)

Hi3520
2
2-14 MDIO
Tp
ETH_MDCK Tov
ETH_MDIO
(Out of Chip)
Thd
ETH_MDIO Tsu
(Into of Chip)
MDIO 2-44
2-44 MDIO
MDIO Tov MDIO 37 37 ns
MDIO Tp MDC 370 740 370 740 ns
MDIO Tsu MDIO 10 - ns
MDIO Thd MDIO 10 - ns
MDC Tp MDC
MDIO
MDIO 2-15
2-15 MDIO
MDC
Thd
Tsu
MDIO
MAC 1 0
MDIO 2-45
2-45 MDIO

MDC 18MHz

MDC 18MHz

02 (2010-01-19) 2-117

Hi3520
2

MDC 2.5MHz

(MDC 2.5MHz)
2.10.4 VI
VI 2-16
2-16 VI
T
VICLK (nPort)
Tsu Thd
HS/VS (Port0/2)
Tsu Thd
VIDATAn (nPort)
VI 2-46
2-46 VI
VICLK VIU T - - - ns

Tsu 2.93 - - ns
Thd 2 - - ns
2.10.5 VO
VO 2-17

2-118 02 (2010-01-19)

Hi3520
2
2-17 VO
VOCK (n Port)
Tov
VODATAn
VO 2-48
2-47 VO
VOCK T - 37.03 - ns
Tov T/2T T/2 + 1 T/2+1+T ns
T BT.656 T3BT.1120 T0.11T
2-18 VO
T
VI0CLK
Tsu Thd
VODATAn
VO 2-48
2-48 VO
VICLK T - 13.5 - ns
Tsu 3 - - ns
Thd 2 - - ns
2.10.6 PCI
PCI 2-19 2-20

02 (2010-01-19) 2-119

Hi3520
2
2-19 PCI ()
T
PCI CLK
(OUT Port)
Tsu1 Thd1
Input
Tov1
Output
2-20 PCI ()
T
PCI CLK
(IN Port)
Tsu2 Thd2
Input
Tov2
Output
PCI 2-48
2-49 PCI
PCI CLK T 15.15 - - ns
Tos1 5 - - ns

Tos2 4.5 - - ns
Toh1 0 - - ns

Toh2 0 - - ns
Tov1 4 - 6 ns

Tov2 2 - 8 ns
2.10.7 I2C
I2C 2-21

2-120 02 (2010-01-19)

Hi3520
2
2-21 I2C
SDA
t BUF
tf tr t SU;DAT t HD;STA
t LOW
SCL
t SU;STA t SU;STO
t HD;STA t HD;DAT t HIGH P
S Sr
I2C 2-50
2-50 I2C
SCLSerial Clock fSCL 0 100 0 400 KHz

tHD;STA 4.0 - 0.6 - s
SCL tLOW 4.7 - 1.3 - s
SCL tHIGH 4.0 - 0.6 - s
tSU;STA 4.7 - 0.6 - s
tHD;DAT 0 3.45 0 0.9 s
tSU;DAT 250 - 100 - ns
SDASCL tr - 1000 20+0.1Cb 300 ns
SDASCL tf - 300 20+0.1Cb 300 ns
tSU;STO 4.0 - 0.6 - s
tBUF 4.7 - 1.3 - s

Cb - 400 - 400 pF
VnL 0.1VDD - 0.1VDD - V
VnH 0.2VDD - 0.2VDD - V
2.10.8 MMC
MMC 2-22

02 (2010-01-19) 2-121

Hi3520
2
2-22 MMC
MMCCLK T
(OUT Port)
Tsu Thd
Input
Tov
Output
MMC 2-51
2-51 MMC
MMCCLK T 20.8 - - ns
Tsu 5 - - ns
Thd 2.5 - - ns
Tov 6.5 - 14.3 ns
2.10.9 SPI
2-23 2-25
z MSB:Most Significant Bit
z LSB:Least Significant Bit
z SPICK(0):spo=0
z SPICK(1):spo=1
SPI 2-23
2-23 SPICK
2 3
1
SPICK(0)
SPICK(1)
SPI 2-24 2-25

2-122 02 (2010-01-19)

Hi3520
2
2-24 SPI sph=0
SPICSN
10
11
SPICK(0)
SPICK(1)
4 6 5 7
SPIDI
8 9
SPIDO
2-25 SPI sph=1
SPICSN
18 19
SPICK(0)
SPICK(1)
14 15
12 13
SPIDI MSB IN DATA LSB IN
16 17
SPIDO MSB OUT DATA MSB OUT
SPI 2-52
2-52 SPI
No
1 Cycle time, SPICK tc - - - ns

2 Pulse duration, SPICK high (All tw1 - - - ns
Master Modes)
3 Pulse duration. SPICK low (All tw2 - - - ns
Master Modes)
4 Setup time, SPIDI (input) valid tsu1 - - - ns
before SPICK (output)
falling edge
5 Setup time, SPIDI (in put) valid tsu2 - - - ns
before SPICK (output)
rising edge
6 Hold time, SPIDI (input) valid after th1 - - - ns
SPICK (output) falling edge

02 (2010-01-19) 2-123

Hi3520
2
No

SPICK (output) rising edge
8 Delay time, SPICK (output) rising td1 - - - ns
edge to SPIDO (output) transition
9 Delay time, SPICK (output) falling td2 - - - ns
10 Delay time, SPICSN (output) td3 - - - ns
falling edge to first SPICK (output)
rising or falling edge
or falling edge to SPICSN (output)
rising edge
12 Setup time, SPIDI (input) valid tsu3 - - - ns
before SPICK (output) rising edge
13 Setup time, SPIDI (in put) valid tsu4 - - - ns
before SPICK (output) falling edge
SPICK (output) rising edge
SPICK (output) falling edge
16 Delay time, SSP_SPICK (output) td5 - - - ns
falling edge to SSP_SPIDO
(output) transition
18 Delay time, SPICSN (output) td7 - - - ns
falling edge to first SPICK (output)
rising or falling edge
or falling edge to SPICSN (output)
rising edge
2.10.10 UART
UART 2-26

2-124 02 (2010-01-19)

Hi3520
2
2-26 UART
1 2
LSB MSB Stop bit(1-2 bit)
UART_RXD
Start bit 5-8 bit data Parity bit

(Optional)
3 4
LSB MSB Stop bit(1-2 bit)
UART_TXD
Start bit 5-8 bit data Parity bit

(Optional)
UART URXD 2-53
2-53 UART
No
1 Start Bit UART_RXD 0.96U - 1.05U ns
2 Data Bit UART_RXD 0.96U - 1.05U ns
U = UART baud time = 1/baud rate
UART UTXD 2-54
2-54 UART
No
3 Start Bit UART_TXD U-2 - U+2 ns
4 Data Bit UART_TXD U-2 - U+2 ns
U = UART baud time = 1/baud rate
2.10.11 SIO
I2S
I2S 2-27

02 (2010-01-19) 2-125

Hi3520
2
2-27 I2S
RCK
Tsu
Thd
RFS
Tsu Thd
DI
I2S 2-28
2-28 I2S
XCK
XFS Td Td
Td
DO
I2S 2-55
2-55 I2S
Tsu 10 - - ns
Thd 10 - - ns
Td 0 - 8 ns
PCM
PCM 2-29
2-29 PCM
RCK
Tsu Thd
RFS
Tsu Thd
DI

2-126 02 (2010-01-19)

Hi3520
2
PCM 2-30
2-30 PCM
XCK
Td
XFS Td
Td
DO
PCM 2-56
2-56 PCM
Tsu 10 - - ns
Thd 10 - - ns
Td 0 - 8 ns
2.10.12 SMI
SMI 4.2.4
2.11
2.11.1
Hi3520 PBGA 27mm27mm 0.8mm
2-31 2-35 2-57

02 (2010-01-19) 2-127

Hi3520
2
2-31
aaa
E3 E2 E
D3
D2
D
aaa
2-32
e
A
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T E1
R
P
N
M
L
K
J
H
G
F
E
D
C
B
B A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
"B" 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
D1

2-128 02 (2010-01-19)

Hi3520
2
2-33 Detail B
eee M C B A
fff M C
E
D b
C
B
A
DETAIL"B"
2-34
A A2
A1 "A"
C
2-35 Detail A
ddd C
// ccc C
DETAIL"A"
2-57
mm
A - 2.13 2.23

02 (2010-01-19) 2-129

Hi3520
2
mm
A1 0.30 0.40 0.50

A2 1.12 1.17 1.22
b 0.40 0.50 0.60
c 0.51 0.56 0.61
D 26.80 27.00 27.20
D1 - 24.80 -
D2 23.80 24.00 24.20
D3 - 18.00 -
E 26.80 27.00 27.20
E1 - 24.80 -
E2 23.80 24.00 24.20
E3 -- 18.00 -
e - 0.80 -
aaa 0.20
ccc 0.25
ddd 0.15
eee 0.25
fff 0.10
30 TPY
2.11.2
Hi3520 768 2-58
2-58 Hi3520
I/O 334
170
203
I/O 17

2-130 02 (2010-01-19)

Hi3520
2
18
24
768
Hi3520 2-37 2-40
2-37 2-40 2-36
2-36
Power Group net group net group

VSS VSS DAC0/DAC1 SIO
DVDD33 DVDD33 UART CLK & RESET&TEST
DVDD10 DVDD10 DDR2 USB
DVDD18 DVDD18 EBI GMAC
PCI JTAG
VO/VI PLL
I2C

02 (2010-01-19) 2-131

Hi3520
2
2-37 Hi3520 116AT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DDRA_UD DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_AD DDRA_AD DDRA_AD DDRA_CK DDRA_CK DDRA_BA
VSS DVDD18 DVDD18 VSS
A M1 25 SP3 29 23 SP2 R0 R6 R2 P1 P0 0
DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_AD DDRA_CK DDRA_CK

MDIO VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS VSS
B 30 SN3 22 SN2 R4 N1 N0
DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_OD DDRA_AD DDRA_WE DDRA_CK

GTXD2 MDCK VSS VSS VSS DVDD18 VSS
C 28 31 16 18 21 T R8 N E
DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_LD DDRA_RA DDRA_CA DDRA_AD DDRA_CS DDRA_AD
GCOL GTXD3 GTXD0 VSS
D 27 24 26 17 20 19 M1 SN SN R11 N R9
GTCLKOU
VSS GRXDV GTXD1 VSS VSS DVDD18 DVDD18 VSS VSS VSS DVDD18 DVDD18 VSS VSS DVDD18
E T
GRCLK GRXD1 VSS GTCLK VSS

F
SCL SDA GCRS GTXEN DVDD33
G
VSS VSS GRXD2 GRXD0 DVDD33 VSS DVDD18 DVDD18 VSS VREF VSS VREF DVDD18 DVDD18
H
USBDP0 USBDM0 VSS GRXD3 DVDD33 VSS VSS DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18
J
USBVSSA USBVSSA USBVSSA
USBREXT USBVDD DVDD33 DVDD33
K 33 33 33
USBVSSA USBVDDA
USBDP1 USBDM1 USBVSS DVDD33 DVDD33
L 33 33
USBVDDA USBVDDA USBVDDA

SIO0XFS SIO0DI DVDD33 DVDD33 VSS DVDD10 DVDD10 DVDD10 DVDD10
M 33 33 33
USBVDDA USBVSSA
SIO2RCK SIO0DO SIO0RFS SIO0XCK SIO0RCK DVDD10 VSS VSS VSS VSS
N 33 33
USBVSSA USBVDDA
SIO1RFS ACKOUT VSS SIO1DI VSS DVDD10 VSS VSS VSS VSS
P 33 33
USBVDDA USBVSSA
VSS SIO2RFS SIO1RCK SIO2DI VSS DVDD10 VSS VSS VSS VSS
R 33 33
VI2CK VI2DAT0 VI2HS VI2VS DVDD33 DVDD33 DVDD33 DVDD10 VSS VSS VSS VSS
T

2-132 02 (2010-01-19)

Hi3520
2
2-38 Hi3520 1732AT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DDRA_BA DDRA_AD DDRA_AD DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRB_DQ DDRB_DQ DDRB_DQ
VSS VSS DVDD18 VSS VSS
1 R1 R13 SP1 15 7 SP0 3 14 SP1 10
A
DDRA_BA DDRA_AD DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRB_DQ DDRB_DQ DDRB_DQ DDRB_DQ
DVDD18 VSS DVDD18 VSS DVDD18 VSS
2 R3 SN1 10 SN0 4 12 SN1 8 13
B
DDRA_AD DDRA_AD DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRA_DQ DDRB_DQ DDRB_DQ
DVDD18 DVDD18 VSS DVDD18 VSS VSS
R7 R10 9 12 13 0 2 5 15 9
C
DDRA_AD DDRA_AD DDRA_DQ DDRA_DQ DDRA_DQ DDRA_UD DDRA_DQ DDRA_DQ DDRA_LD DDRB_UD DDRB_DQ DDRB_DQ DDRB_DQ DDRB_DQ DDRB_DQ
VSS
R12 R5 14 11 8 M0 6 1 M0 M0 11 7 6 SP0 SN0
D
DDRB_DQ DDRB_DQ
DVDD18 DVDD18 VSS VSS VSS DVDD18 DVDD18 VSS VSS DVDD18 DVDD18 VSS DVDD18 DVDD18
0 3
E
DDRB_DQ DDRB_DQ DDRB_DQ DDRB_DQ DDRB_OD
1 2 4 5 T
F
DDRB_LD DDRB_AD DDRB_AD DDRB_CS
DVDD18
M0 R4 R6 N
G
DDRB_AD DDRB_RA DDRB_AD
DVDD18 VREF VSS VREF VSS VREF VSS VREF VSS VSS VSS
R0 SN R2
H
DDRB_AD DDRB_CA DDRB_CK DDRB_CK
DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 DVDD18 VSS DVDD18 VSS
R8 SN P0 N0
J
DDRB_AD DDRB_WE
DVDD18 VREF VSS DVDD18 DVDD18
R11 N
K
DDRB_BA DDRB_CK DDRB_AD DDRB_BA DDRB_AD
DVDD18 VSS
1 E R9 0 R7
L
DDRB_BA DDRB_AD
DVDD10 DVDD10 DVDD10 DVDD10 VSS DVDD18 VREF DVDD18 VSS VSS
2 R3
M
DDRB_AD DDRB_AD DDRB_AD DDRB_AD DDRB_AD
VSS VSS VSS VSS DVDD10 DVDD18 VSS
R12 R1 R10 R13 R5
N
VSS VSS VSS VSS DVDD10 DVDD18 VREF VSS VSS DVDD18 DVDD18 VSS
P
VSS VSS VSS VSS DVDD10 DVDD18 VSS_VPLL VSS_VPLL TDI TDO TCK TMS
R
VDD10_V VDD10_V AVDD33_ TESTMOD
VSS VSS VSS VSS DVDD10 TRSTN VSS VSS
PLL0 PLL1 VPLL E
T

02 (2010-01-19) 2-133

Hi3520
2
2-39 Hi3520 116UAM
VI2DAT3 VI2DAT2 VSS VI2DAT1 DVDD33 DVDD33 DVDD33 DVDD10 VSS VSS VSS VSS
U
VI2DAT6 VI2DAT5 VI2DAT4 VI2DAT7 VSS VSS DVDD33 DVDD10 VSS VSS VSS VSS
V
VSS VI3CK VI3DAT0 VI3DAT2 VSS VSS DVDD33 DVDD10 VSS VSS VSS VSS
W
AVSS_DA
VI3DAT1 VI3DAT4 VI3DAT5 VI3DAT6 DVDD33 DVDD33 DVDD33 VSS VSS VSS VSS
Y C
AVSS_DA AVSS_DA
VI3DAT3 VI3DAT7 VSS VI0HS DVDD33 DVDD33 DVDD33 DVDD10 DVDD10 DVDD10
AA C C
AVDD33_ AVSS_DA
VI0VS VI0DAT0 VI0DAT1 VI0DAT3 VSS
AB DAC C
VREFINDA DVSS10_
VSS VI0CK VI0DAT5 VI0DAT4 VSS
AC C0 DAC
DVDD33_ DVSS33_ DVDD10_ AVSS_DA

VI0DAT2 VI0DAT6 VI0DAT7 VI1DAT3 DVDD33 VSS DVDD33 DVDD33 DVDD33 DVDD33
AD DAC0 DAC DAC C
DVSS33_ DVDD33_ VREFINDA AVDD33_

VI1CK VI1DAT0 VSS VI1DAT2 DVDD33 VSS VSS DVDD33 DVDD33 VSS
AE DAC DAC1 C1 DAC
VSS VI1DAT1 VI1DAT4 VI1DAT6 DVDD33

AF
AVDD33_ RSETDAC COMPDA
VI1DAT5 VI1DAT7
AG DAC 0 C0
AVSS_DA AVDD33_ AVSS_DA COMPDA RSETDAC AVSS_DA AVDD33_

VSS VSS DVDD33 DVDD33 VSS VSS DVDD33 DVDD33 VSS
AH C DAC C C1 1 C DAC
DACVGA0 AVSS_DA AVDD33_ AVSS_DA AVSS_DA PCIFRAM

RSTN URXD1 PCIRSTN PCIAD28 PCIAD24 PCIAD22 PCIAD19 PCIIRDYN PCIAD15 PCIAD12
AJ B C DAC C C EN
DACVGA0 AVSS_DA AVDD33_ AVDD33_ PCIDEVSE

URXD0 UTXD0 WDGRST VSS PCIAD31 PCIAD27 PCICBE0 VSS PCIAD18 PCITRDYN VSS
AK G C DAC DAC LN
DACVGA0 AVSS_DA AVSS_DA AVSS_DA AVDD33_ PCISTOP

URTSN1 UTXD1 PCIINTAN PCIAD30 PCIAD26 PCICBE1 PCIAD21 PCIAD17 PCIIDSEL PCIAD13
AL R C C C DAC N
AVSS_DA DACVGA1 DACVGA1 DACVGA1 AVSS_DA

UCTSN1 PCICLK VSS PCIAD29 PCIAD25 PCIAD23 PCIAD20 VSS PCIAD16 PCICBE2 PCIAD14
AM C R G B C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

2-134 02 (2010-01-19)

Hi3520
2
2-40 Hi3520 1732UAM
VDD10_E AVDD33_
VSS VSS VSS VSS DVDD10 VSS_EPLL VO0DAT6 VO0DAT7 XIN_24 XOUT_24
PLL AEPLL
U
VDD10_A
VSS VSS VSS VSS DVDD10 VSS_APLL VSS_APLL VO0DAT5 VO0DAT4 VO0DAT3 VO0DAT2
PLL
V
VSS VSS VSS VSS DVDD10 DVDD33 DVDD33 VSS VO0DAT1 VO0DAT0 VORGBDV VO0CK
W
VO1DAT1 VO1DAT1 VO1DAT1
VSS VSS VSS VSS DVDD10 DVDD33 VSS VSS GPIO3_0
5 3 4
Y
VO1DAT1 VO1DAT1
DVDD10 DVDD10 DVDD10 DVDD10 VSS DVDD33 VSS DVDD33 VSS VO1CK
2 1
AA
VO1DAT1
DVDD33 DVDD33 DVDD33 VO1DAT6 VO1DAT9 VO1DAT8
0
AB
DVDD33 DVDD33 VSS VO1DAT4 VO1DAT7 VO1DAT5 VSS
AC
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 VSS VSS VSS VO1DAT0 VO1DAT2 VO1DAT1 VO1DAT3
AD
VSS DVDD33 DVDD33 VSS VSS DVDD33 DVDD33 VSS VSS DVDD33 EBIADR21 EBIADR23 EBIADR22 EBIADR24
AE
DVDD33 EBIADR18 VSS EBIADR20 EBIADR19
AF
VSS EBIADR14 EBIADR16 EBIADR15 EBIADR17
AG
VSS DVDD33 DVDD33 VSS VSS DVDD33 DVDD33 VSS VSS DVDD33 DVDD33 VSS EBIADR11 EBIADR12 EBIADR13 VSS
AH
PCISERR PCIGRAN PCIGRAN PCIREQ3
PCIAD8 PCIAD6 PCIAD2 SMIOEN SMICS0N NFRB EBIDQ2 EBIDQ4 EBIADR4 EBIADR9 EBIADR8 EBIADR10
N T1N T4N N
AJ
PCIPERR PCIGRAN PCIGRAN PCIREQ2
PCIAD9 PCIAD7 VSS VSS NFOEN NFCS0N VSS EBIDQ3 EBIADR0 VSS EBIADR7 EBIADR5
N T0N T2N N
AK
PCIREQ0 PCIGRAN PCIREQ1
PCIAD10 PCICBE3 PCIAD5 PCIAD0 EBIWEN SMICS1N EBIRDYN EBIDQ0 EBIDQ1 EBIDQ5 EBIDQ7 EBIADR3 EBIADR6
N T3N N
AL
PCIREQ4
PCIAD11 VSS PCIPAR PCIAD4 PCIAD3 PCIAD1 VSS NFCLE NFALE NFCS1N VSS EBIDQ6 EBIADR1 EBIADR2 VSS
N
AM
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2.11.3
Hi3520 2-59
2-59
A1 VSS U1 VI2DAT3
A2 DDRA_UDM1 U2 VI2DAT2
A3 DDRA_DQ25 U3 VSS
A4 DVDD18 U4 VI2DAT1
A5 DDRA_DQSP3 U5 DVDD33
A6 DDRA_DQ29 U8 DVDD33

02 (2010-01-19) 2-135

Hi3520
2
A7 DDRA_DQ23 U9 DVDD33
A8 DDRA_DQSP2 U12 DVDD10
A9 DVDD18 U13 VSS
A10 DDRA_ADR0 U14 VSS
A13 DDRA_CKP1 U17 VSS
A14 VSS U18 VSS
A15 DDRA_CKP0 U19 VSS
A16 DDRA_BA0 U20 VSS
A17 DDRA_BA1 U21 DVDD10
A18 DDRA_ADR1 U24 VDD10_EPLL
A19 DDRA_ADR13 U25 VSS_EPLL
A20 VSS U28 AVDD33_AEPLL
A21 DDRA_DQSP1 U29 VO0DAT6
A22 DDRA_DQ15 U30 VO0DAT7
A23 DDRA_DQ7 U31 XIN_24
A24 DDRA_DQSP0 U32 XOUT_24
A25 VSS V1 VI2DAT6
A26 DDRA_DQ3 V2 VI2DAT5
A27 DVDD18 V3 VI2DAT4
A28 DDRB_DQ14 V4 VI2DAT7
A29 VSS V5 VSS
A30 DDRB_DQSP1 V8 VSS
A31 DDRB_DQ10 V9 DVDD33
A32 VSS V12 DVDD10
B1 MDIO V13 VSS
B2 VSS V14 VSS
B3 DDRA_DQ30 V15 VSS
B4 DVDD18 V16 VSS
B5 DDRA_DQSN3 V17 VSS

2-136 02 (2010-01-19)

Hi3520
2
B6 VSS V18 VSS

B7 DDRA_DQ22 V19 VSS
B8 DDRA_DQSN2 V20 VSS
B9 DVDD18 V21 DVDD10
B10 VSS V24 VDD10_APLL
B11 DDRA_ADR4 V25 VSS_APLL
B12 DVDD18 V28 VSS_APLL
B13 DDRA_CKN1 V29 VO0DAT5
B14 VSS V30 VO0DAT4
B15 DDRA_CKN0 V31 VO0DAT3
B16 VSS V32 VO0DAT2
B17 DDRA_BA2 W1 VSS
B18 DDRA_ADR3 W2 VI3CK
B19 DVDD18 W3 VI3DAT0
B20 VSS W4 VI3DAT2
B21 DDRA_DQSN1 W5 VSS
B22 DDRA_DQ10 W8 VSS
B23 DVDD18 W9 DVDD33
B24 DDRA_DQSN0 W12 DVDD10
B25 VSS W13 VSS
B26 DDRA_DQ4 W14 VSS
B27 DVDD18 W15 VSS
B28 DDRB_DQ12 W16 VSS
B29 VSS W17 VSS
B30 DDRB_DQSN1 W18 VSS
C1 GTXD2 W21 DVDD10
C2 MDCK W24 DVDD33
C3 VSS W25 DVDD33
C4 DDRA_DQ28 W28 VSS

02 (2010-01-19) 2-137

Hi3520
2
C5 DDRA_DQ31 W29 VO0DAT1

C6 VSS W30 VO0DAT0
C7 DDRA_DQ16 W31 VORGBDV
C8 DDRA_DQ18 W32 VO0CK
C9 DDRA_DQ21 Y1 VI3DAT1
C10 VSS Y2 VI3DAT4
C11 DDRA_ODT Y3 VI3DAT5
C12 DVDD18 Y4 VI3DAT6
C13 DDRA_ADR8 Y5 DVDD33
C14 DDRA_WEN Y8 DVDD33
C15 DDRA_CKE Y9 DVDD33
C16 VSS Y12 AVSS_DAC
C17 DDRA_ADR7 Y13 VSS
C18 DDRA_ADR10 Y14 VSS
C19 DVDD18 Y15 VSS
C20 DDRA_DQ9 Y16 VSS
C23 DVDD18 Y19 VSS
C25 DDRA_DQ2 Y21 DVDD10
C26 DDRA_DQ5 Y24 DVDD33
C27 VSS Y25 VSS
C28 DDRB_DQ15 Y28 VSS
C29 DDRB_DQ9 Y29 GPIO3_0
C30 DVDD18 Y30 VO1DAT15
C31 VSS Y31 VO1DAT13
C32 VSS Y32 VO1DAT14
D1 GCOL AA1 VI3DAT3
D2 GTXD3 AA2 VI3DAT7
D3 GTXD0 AA3 VSS

2-138 02 (2010-01-19)

Hi3520
2
D4 VSS AA4 VI0HS

D5 DDRA_DQ27 AA5 DVDD33
D8 DDRA_DQ17 AA12 AVSS_DAC
D9 DDRA_DQ20 AA13 AVSS_DAC
D11 DDRA_LDM1 AA15 DVDD10
D12 DDRA_RASN AA16 DVDD10
D13 DDRA_CASN AA17 DVDD10
D14 DDRA_ADR11 AA18 DVDD10
D15 DDRA_CSN AA19 DVDD10
D17 DDRA_ADR12 AA21 VSS
D19 DDRA_DQ14 AA25 VSS
D21 DDRA_DQ8 AA29 VO1DAT12
D22 DDRA_UDM0 AA30 VSS
D23 DDRA_DQ6 AA31 VO1CK
D24 DDRA_DQ1 AA32 VO1DAT11
D25 DDRA_LDM0 AB1 VI0VS
D26 VSS AB2 VI0DAT0
D27 DDRB_UDM0 AB3 VI0DAT1
D28 DDRB_DQ11 AB4 VI0DAT3
D29 DDRB_DQ7 AB5 VSS
D30 DDRB_DQ6 AB8 AVDD33_DAC
D31 DDRB_DQSP0 AB9 AVSS_DAC
D32 DDRB_DQSN0 AB24 DVDD33
E1 VSS AB25 DVDD33
E2 GTCLKOUT AB28 DVDD33

02 (2010-01-19) 2-139

Hi3520
2
E3 GRXDV AB29 VO1DAT6

E4 GTXD1 AB30 VO1DAT9
E5 VSS AB31 VO1DAT8
E6 VSS AB32 VO1DAT10
E7 DVDD18 AC1 VSS
E8 DVDD18 AC2 VI0CK
E9 VSS AC3 VI0DAT5
E10 VSS AC4 VI0DAT4
E11 VSS AC5 VSS
E12 DVDD18 AC8 VREFINDAC0
E13 DVDD18 AC9 DVSS10_DAC
E14 VSS AC24 DVDD33
E15 VSS AC25 DVDD33
E16 DVDD18 AC28 VSS
E17 DVDD18 AC29 VO1DAT4
E18 DVDD18 AC30 VO1DAT7
E19 VSS AC31 VO1DAT5
E20 VSS AC32 VSS
E21 VSS AD1 VI0DAT2
E22 DVDD18 AD2 VI0DAT6
E23 DVDD18 AD3 VI0DAT7
E24 VSS AD4 VI1DAT3
E25 VSS AD5 DVDD33
E26 DVDD18 AD8 DVDD33_DAC0
E27 DVDD18 AD9 DVSS33_DAC
E28 VSS AD10 DVDD10_DAC
E29 DDRB_DQ0 AD11 AVSS_DAC
E30 DVDD18 AD12 VSS
E31 DVDD18 AD13 DVDD33
E32 DDRB_DQ3 AD14 DVDD33
F1 GRCLK AD15 DVDD33

2-140 02 (2010-01-19)

Hi3520
2
F2 GRXD1 AD16 DVDD33

F3 VSS AD17 DVDD33
F4 GTCLK AD18 DVDD33
F5 VSS AD19 DVDD33
F28 DDRB_DQ1 AD20 DVDD33
F32 DDRB_ODT AD24 VSS
G1 SCL AD25 VSS
G2 SDA AD28 VSS
G3 GCRS AD29 VO1DAT0
G4 GTXEN AD30 VO1DAT2
G5 DVDD33 AD31 VO1DAT1
G28 DVDD18 AD32 VO1DAT3
G29 DDRB_LDM0 AE1 VI1CK
G30 DDRB_ADR4 AE2 VI1DAT0
G31 DDRB_ADR6 AE3 VSS
G32 DDRB_CSN AE4 VI1DAT2
H1 VSS AE5 DVDD33
H2 VSS AE8 DVSS33_DAC
H3 GRXD2 AE9 DVDD33_DAC1
H4 GRXD0 AE10 VREFINDAC1
H5 DVDD33 AE11 AVDD33_DAC
H8 VSS AE12 VSS
H9 DVDD18 AE13 VSS
H10 DVDD18 AE14 DVDD33
H11 VSS AE15 DVDD33
H12 VREF AE16 VSS
H13 VSS AE17 VSS
H14 VREF AE18 DVDD33

02 (2010-01-19) 2-141

Hi3520
2
H15 DVDD18 AE19 DVDD33

H16 DVDD18 AE20 VSS
H17 DVDD18 AE21 VSS
H19 VSS AE23 DVDD33
H20 VREF AE24 VSS
H21 VSS AE25 VSS
H23 VSS AE29 EBIADR21
H24 VREF AE30 EBIADR23
H25 VSS AE31 EBIADR22
H28 DDRB_ADR0 AE32 EBIADR24
H29 DDRB_RASN AF1 VSS
H30 VSS AF2 VI1DAT1
H31 VSS AF3 VI1DAT4
H32 DDRB_ADR2 AF4 VI1DAT6
J1 USBDP0 AF5 DVDD33
J2 USBDM0 AF28 DVDD33
J3 VSS AF29 EBIADR18
J4 GRXD3 AF30 VSS
J5 DVDD33 AF31 EBIADR20
J8 VSS AF32 EBIADR19
J9 VSS AG1 VI1DAT5
J10 DVDD18 AG2 VI1DAT7
J11 DVDD18 AG3 AVDD33_DAC
J12 DVDD18 AG4 RSETDAC0
J13 DVDD18 AG5 COMPDAC0
J14 DVDD18 AG28 VSS
J15 DVDD18 AG29 EBIADR14

2-142 02 (2010-01-19)

Hi3520
2

J19 DVDD18 AH1 AVSS_DAC
J20 DVDD18 AH2 AVDD33_DAC
J21 DVDD18 AH3 AVSS_DAC
J22 DVDD18 AH4 COMPDAC1
J23 DVDD18 AH5 RSETDAC1
J24 VSS AH6 AVSS_DAC
J25 DVDD18 AH7 AVDD33_DAC
J28 VSS AH8 VSS
J29 DDRB_ADR8 AH9 VSS
J30 DDRB_CASN AH10 DVDD33
J31 DDRB_CKP0 AH11 DVDD33
J32 DDRB_CKN0 AH12 VSS
K1 USBVSSA33 AH13 VSS
K2 USBVSSA33 AH14 DVDD33
K3 USBREXT AH15 DVDD33
K4 USBVSSA33 AH16 VSS
K5 USBVDD AH17 VSS
K8 DVDD33 AH18 DVDD33
K9 DVDD33 AH19 DVDD33
K24 DVDD18 AH20 VSS
K25 VREF AH21 VSS
K28 VSS AH22 DVDD33
K29 DDRB_ADR11 AH23 DVDD33
K30 DVDD18 AH24 VSS
K31 DVDD18 AH25 VSS
K32 DDRB_WEN AH26 DVDD33
L1 USBDP1 AH27 DVDD33
L2 USBDM1 AH28 VSS
L3 USBVSSA33 AH29 EBIADR11
L4 USBVDDA33 AH30 EBIADR12

02 (2010-01-19) 2-143

Hi3520
2
L5 USBVSS AH31 EBIADR13

L8 DVDD33 AH32 VSS
L9 DVDD33 AJ1 DACVGA0B
L24 DVDD18 AJ2 AVSS_DAC
L25 VSS AJ3 AVDD33_DAC
L28 DDRB_BA1 AJ4 AVSS_DAC
L29 DDRB_CKE AJ5 AVSS_DAC
L30 DDRB_ADR9 AJ6 RSTN
L31 DDRB_BA0 AJ7 URXD1
L32 DDRB_ADR7 AJ8 PCIRSTN
M1 USBVDDA33 AJ9 PCIFRAMEN
M2 USBVDDA33 AJ10 PCIAD28
M3 USBVDDA33 AJ11 PCIAD24
M4 SIO0XFS AJ12 PCIAD22
M5 SIO0DI AJ13 PCIAD19
M8 DVDD33 AJ14 PCIIRDYN
M9 DVDD33 AJ15 PCIAD15
M12 VSS AJ16 PCIAD12
M14 DVDD10 AJ18 PCISERRN
M17 DVDD10 AJ21 PCIGRANT1N
M18 DVDD10 AJ22 PCIGRANT4N
M19 DVDD10 AJ23 PCIREQ3N
M20 DVDD10 AJ24 SMIOEN
M21 VSS AJ25 SMICS0N
M24 DVDD18 AJ26 NFRB
M25 VREF AJ27 EBIDQ2
M28 DVDD18 AJ28 EBIDQ4
M29 DDRB_BA2 AJ29 EBIADR4

2-144 02 (2010-01-19)

Hi3520
2
M30 VSS AJ30 EBIADR9

M31 VSS AJ31 EBIADR8
M32 DDRB_ADR3 AJ32 EBIADR10
N1 SIO2RCK AK1 DACVGA0G
N2 SIO0DO AK2 AVSS_DAC
N3 SIO0RFS AK3 AVDD33_DAC
N4 SIO0XCK AK4 AVDD33_DAC
N5 SIO0RCK AK5 URXD0
N8 USBVDDA33 AK6 UTXD0
N9 USBVSSA33 AK7 WDGRST
N12 DVDD10 AK8 VSS
N13 VSS AK9 PCIAD31
N14 VSS AK10 PCIAD27
N15 VSS AK11 PCICBE0
N16 VSS AK12 VSS
N17 VSS AK13 PCIAD18
N18 VSS AK14 PCITRDYN
N19 VSS AK15 PCIDEVSELN
N20 VSS AK16 VSS
N21 DVDD10 AK17 PCIAD9
N24 DVDD18 AK18 PCIPERRN
N25 VSS AK19 PCIAD7
N28 DDRB_ADR12 AK20 VSS
N29 DDRB_ADR1 AK21 PCIGRANT0N
N30 DDRB_ADR10 AK22 PCIGRANT2N
N31 DDRB_ADR13 AK23 PCIREQ2N
N32 DDRB_ADR5 AK24 VSS
P1 SIO1RFS AK25 NFOEN
P2 ACKOUT AK26 NFCS0N
P3 VSS AK27 VSS
P4 SIO1DI AK28 EBIDQ3

02 (2010-01-19) 2-145

Hi3520
2
P5 VSS AK29 EBIADR0

P8 USBVSSA33 AK30 VSS
P9 USBVDDA33 AK31 EBIADR7
P12 DVDD10 AK32 EBIADR5
P13 VSS AL1 DACVGA0R
P14 VSS AL2 AVSS_DAC
P17 VSS AL5 AVDD33_DAC
P18 VSS AL6 URTSN1
P19 VSS AL7 UTXD1
P20 VSS AL8 PCIINTAN
P21 DVDD10 AL9 PCIAD30
P24 DVDD18 AL10 PCIAD26
P25 VREF AL11 PCICBE1
P28 VSS AL12 PCIAD21
P30 DVDD18 AL14 PCIIDSEL
P31 DVDD18 AL15 PCISTOPN
R1 VSS AL17 PCIAD10
R2 SIO2RFS AL18 PCICBE3
R3 SIO1RCK AL19 PCIREQ0N
R4 SIO2DI AL20 PCIAD5
R5 VSS AL21 PCIAD0
R8 USBVDDA33 AL22 PCIGRANT3N
R9 USBVSSA33 AL23 PCIREQ1N
R12 DVDD10 AL24 EBIWEN
R13 VSS AL25 SMICS1N
R14 VSS AL26 EBIRDYN
R15 VSS AL27 EBIDQ0

2-146 02 (2010-01-19)

Hi3520
2
R16 VSS AL28 EBIDQ1

R17 VSS AL29 EBIDQ5
R18 VSS AL30 EBIDQ7
R19 VSS AL31 EBIADR3
R20 VSS AL32 EBIADR6
R21 DVDD10 AM1 AVSS_DAC
R24 DVDD18 AM2 DACVGA1R
R25 VSS_VPLL AM3 DACVGA1G
R28 VSS_VPLL AM4 DACVGA1B
R29 TDI AM5 AVSS_DAC
R30 TDO AM6 UCTSN1
R31 TCK AM7 PCICLK
R32 TMS AM8 VSS
T1 VI2CK AM9 PCIAD29
T2 VI2DAT0 AM10 PCIAD25
T3 VI2HS AM11 PCIAD23
T4 VI2VS AM12 PCIAD20
T5 DVDD33 AM13 VSS
T8 DVDD33 AM14 PCIAD16
T9 DVDD33 AM15 PCICBE2
T12 DVDD10 AM16 PCIAD14
T13 VSS AM17 PCIAD11
T14 VSS AM18 VSS
T15 VSS AM19 PCIPAR
T16 VSS AM20 PCIAD4
T17 VSS AM21 PCIAD3
T18 VSS AM22 PCIAD1
T19 VSS AM23 VSS
T20 VSS AM24 PCIREQ4N
T21 DVDD10 AM25 NFCLE
T24 VDD10_VPLL0 AM26 NFALE

02 (2010-01-19) 2-147

Hi3520
2
T25 VDD10_VPLL1 AM27 NFCS1N

T28 AVDD33_VPLL AM28 VSS
T29 TRSTN AM29 EBIDQ6
T30 TESTMODE AM30 EBIADR1
T31 VSS AM31 EBIADR2
T32 VSS AM32 VSS

2-148 02 (2010-01-19)

Hi3520
3
3.1
3.1.1

z
z
z
3.1.2
3-1
3-1
System
Controller
sys_rst_req xx_rst_req
RSTN xx_rst_n
ResetCtrl ResetCtrl
Level1 Level2
PCIRSTN sys_rst_n
npor
RSTN RSTN
PCIRSTNPCI PCIRSTN
sys_rst_req
xx_rst_req
xx_rst_nsys_rst_nnpor

02 (2010-01-19) 3-1

Hi3520
3
3-1
npor RSTN

sys_rst_n

xx_rst_n
PCI PCI PCIRSTN Hi3520

PCIRSTN PCI
3.1.3
RSTN Hi3520 IO
z IO
z XIN24
z 12 XIN24

z
z SC_SYSSTAT
SC_SYSSTAT

z 360
z 1
0
z USB 2.0 Host PHY MMCETHVIVO RTC

3-2 02 (2010-01-19)

Hi3520
3
3.2
3.2.1

z
z
z
3.2.2
3-2
3-2
System
Controller
SC_PEREN
SC_PERCTRL0-7 SC_PERCTRL9 SC_PERDIS
arm_clk
PLL ARMCLK
sclk
Freq Ctrl
PLL
PLL Clock
Gating
PLL
IPCLK XXIP_clk
Freq Ctrl
XIN24 VInCK ERXCLK ETXCLK PCICLK
VInCK n 03

z XIN24VI0CKVI1CKVI2CKVI3CK
ERXCLKETXCLK PCICLK
XIN24 PLL USB 2.0 Host PHY
VI0CKVI1CKVI2CKVI3CK
ERXCLKETXCLK ETH

02 (2010-01-19) 3-3

Hi3520
3
PCICLK PCI
z
PLL
IP

z PLL ARM
z ARM ARMCLK Freq Ctrl IPCLK Freq
Ctrl
z Clock Gating
3.2.3
PLL
Hi3520 PLL PLL 3-2
SC_PERCTRL0SC_PERCTRL7
3-2 Hi3520 PLL
PLL
APLL SC_PERCRTL0 APLL ARM

SC_PERCRTL1
EPLL SC_PERCRTL2 EPLL ETH
SC_PERCRTL3
VPLL0 SC_PERCRTL4 VPLL0 VO0
SC_PERCRTL5
VPLL1 SC_PERCRTL6 VPLL1 VO1
SC_PERCRTL7
PLL XIN24 24MHz PLL

3-3
3-3 Hi3520 PLL
PLL Pin
FREF 24MHz Hi3520 24MHz

3-4 02 (2010-01-19)

Hi3520
3
PLL Pin
FOUTVCO FREF % ( fbdiv + frac/2^24) / PLL VCO

refdiv 800MHz 2.4GHz
PLL
frac0
FOUTPOSTDIV FOUTVCO / pstdiv1 % -

pstdiv2
FOUT1ph0 FOUTVCO / (pstdiv1 % 2) -
FOUT2 FOUTVCO / (pstdiv1 % 4) -
Hi3520 PLL APLL EPLL VPLL0 VPLL1

APLL FOUT2FOUT3 FOUT4 600MHz
400MHz 300MHz 3-4 SC_PERCTRL0=0x8900_0000
SC_PERCTRL1=0x006C_1064
3-4 Hi3520 APLL
bit PLL Pin
SC_PERCTRL0[31] dsmpd 0 0b1

1
SC_PERCTRL0 [30] bypass 0no bypass 0b0

1bypass
SC_PERCTRL0[29:27] postdiv2 PLL 0b001
SC_PERCTRL0[26:24] postdiv1 PLL 0b001
SC_PERCTRL0[23:0] frac PLL 0x00_0000
SC_PERCTRL1[22] reset PLL 0b1

0
1
SC_PERCTRL1[21] pd PLL Power Down 0b1

0
1

02 (2010-01-19) 3-5

Hi3520
3
bit PLL Pin
SC_PERCTRL1[20] foutvcopd PLL VCO Power Down 0b0

0
1
SC_PERCTRL1[19] postdivpd PLL POSTDIV Power 0b1

Down
0
1
SC_PERCTRL1[18] fout4phasepd PLL FOUT Power Down 0b1

0
1
SC_PERCTRL1[17:12] refdiv PLL 0x01
SC_PERCTRL1[11:0] fbdiv PLL 0x064
EPLL FOUTPOSTDIVFOUT1ph0FOUT2 FOUT4

500MHz250MHz125MHz 62.5MHz 3-5
SC_PERCTRL6=0x8B00_0000 SC_PERCTRL7=0x006C_207D
3-5 Hi3520 EPLL
bit PLL Pin
SC_PERCTRL6[31] dsmpd 0 0x1

1
SC_PERCTRL6[30] bypass 0no bypass 0x0

1bypass
SC_PERCTRL6[29:27] postdiv2 PLL 0x1
SC_PERCTRL6[26:24] postdiv1 PLL 0x3
SC_PERCTRL6[23:0] frac PLL 0x00_0000
SC_PERCTRL7[22] reset PLL 0x1

0
1
SC_PERCTRL7[21] pd PLL Power Down 0x1

0
1

3-6 02 (2010-01-19)

Hi3520
3
bit PLL Pin
SC_PERCTRL7[20] foutvcopd PLL VCO Power Down 0x0

0
1
SC_PERCTRL7[19] postdivpd PLL POSTDIV Power 0x1

Down
0
1
SC_PERCTRL7[18] vfout4phase PLL FOUT Power Down 0x1

pd
0
1
SC_PERCTRL7[17:12] refdiv PLL 0x2
SC_PERCTRL7[11:0] fbdiv PLL 0x07D
VPLL0 VPLL1 PLL FOUTPOSTDIV

SC_PERCTRL2SC_PERCTRL5 3-6 3-7
3-6 Hi3520 VPLL0
bit PLL Pin
SC_PERCTRL2[31] dsmpd 0
1
SC_PERCTRL2[30] bypass 0no bypass 0b0

1bypass
SC_PERCTRL2[29:27] postdiv2 PLL
SC_PERCTRL2 [23:0] frac PLL

0
1
SC_PERCTRL3 [21] pd PLL Power Down 0b1

0
1

02 (2010-01-19) 3-7

Hi3520
3
bit PLL Pin
SC_PERCTRL3 [20] foutvcopd PLL VCO Power Down 0b0

0
1

Down
0
1
SC_PERCTRL3[18] vfout4phase PLL FOUT Power Down 0b1

pd
0
1
SC_PERCTRL3[17:12] refdiv PLL
SC_PERCTRL3 [11:0] fbdiv PLL
3-7 Hi3520 VPLL1
bit PLL Pin
SC_PERCTRL4[31] dsmpd 0
1
SC_PERCTRL4[30] bypass 0no bypass 0b0

1bypass
SC_PERCTRL4[23:0] frac PLL

0
1
SC_PERCTRL5[21] pd PLL Power Down 0b1

0
1

3-8 02 (2010-01-19)

Hi3520
3
bit PLL Pin
SC_PERCTRL5[20] foutvcopd PLL VCO Power Down 0b0

0
1

Down
0
1
SC_PERCTRL5[18] vfout4phase PLL FOUT Power Down 0b1

pd
0
1
SC_PERCTRL5[17:12] refdiv PLL
SC_PERCTRL5 [11:0] fbdiv PLL
PLL VPLL1
VPLL1 FOUTPOSTDIV VO1 VO1 74.25MHz

z postdiv24postdiv15 FOUTVCO74.25%4%5=1485MHz
z refdiv1 24%(fbdiv + frac/2^24)=1485MHz
fbdiv61frac=14680064
VPLL0 54MHzVPLL1 108MHz
z SC_PERCTRL2=0xB400_0000
z SC_PERCTRL3=0x006C_1036
z SC_PERCTRL4=0x9C00_0000
z SC_PERCTRL5=0x006C_1036
ARM/SCLK/HCLK/PCLK
ARM/SCLK/HCLK/PCLK 3-8
3-8 ARM/SCLK/HCLK/PCLK
sysmode[3:0] ARM
0xB SC_CTRL [2:0]

02 (2010-01-19) 3-9

Hi3520
3
sleep_mode SCLK/IR /CRGClock Reset Generation

SC_CTRL bit[2:0]]

arm0freq_sel ARM1196 SC_PERCRTL9 bit[1:0]

3-9
3-9
45kHz 24MHz ARMPLL

NORMAL ARM
PLL
SLOW ARM
24MHz

DOZE ARM
24MHz
45KHz

SLEEP
45KHz

MMC 3-10
3-10 MMC
mmcclk_sel MMC SC_PERCRTL9

bit[21:20]
MMC
mmcsap_sel
SC_PERCRTL bit[22]

3-10 02 (2010-01-19)

Hi3520
3
PCI 3-11
3-11 PCI
pciclk_sel[3:0] PCI SC_PERCRTL9

bit[24:23]
SMI 3-12
3-12 SMI
ssmcclk_sel SMI AHB 1 2

SC_PERCRTL9 bit[3]
VO 3-13
3-13 VO
vo0out_sel VO0 BT656 VO0

SC_PERCRTL9 bit[18]
vo1out_sel VO1 BT1120 VO1

SC_PERCRTL9 bit[19]
VO_SD DATE VO
vosd_sel
SC_PERCRTL9 bit[15:14]
VO_HD DATE VO
vohd_sel
VI 3-14
3-14 VI
vi3div_sel[1:0] VI3 VI3 1/2/4



02 (2010-01-19) 3-11

Hi3520
3


vi3_vi2_sel VI3 SC_PERCRTL9 bit[5]

vi1_vi0_sel VI1 SC_PERCRTL9 bit[4]

ETH 3-15
3-15 ETH
ethmac_mode[2:0] GMAC SC_PERCRTL9 [28:26]

ethtclk_sel ETH txclk SC_PERCRTL9 [29]

ethtioclk_sel ETH txioclk SC_PERCRTL9 [30]

SIO0/SIO1/SIO2 3-16
3-16 SIO0/SIO1/SIO2
sio0clk_sel[23:0] SIO0 SIO_MCLK

sio0_bclk_sel[3:0] SIO0 SIO_XCKBCLK

sio0_lrclk_sel[3:0] SIO0
SIO_RFS/SIO_XFSFSCLK
sio12clk_sel[23:0] SIO1/SIO2 SIO_MCLK



3-12 02 (2010-01-19)

Hi3520
3

sio0_blk_edge SIO0 SC_PERCRTL16 bit[8]



ACKOUT SC_PERCRTL9 bit[25]

aclkout_sel

FSCLK BCLK MCLK

FSCLK
ARMPLL 540MHz SIO

FSCLK=48kHzMCLK=256FSCLK=12.288MHzBCLK=16FSCLK=384KHz

ARMPLL MCLK N=12.288/540 sioclk_sel[23:0]= N 2

27
z
3054199 sioclk_sel=0x002E_9A77
MCLK
z BCLK MCLK BCLK/MCLK=16/256=1/16
siobclk_sel[2:0]=0b100 16 BCLK

z FSCLK BCLK 1/16
siolrclk_sel=0b011 16 FSCLK
SC_PEREN

z ARM XIN24

02 (2010-01-19) 3-13

Hi3520
3
z PLL 0.1ms PLL

SLOW
z PLL PLL
3.3
3.3.1
Hi3520 ARM1176ZJF-SARM0 ARM926EJ-SARM1
ARM1176ZJF-S
z 32bit ARM v5TEJ8 32bit ARM16bit Thumb
z DSP
z Java
z VFPVector Floating-Point
z
z 16KB Cache16KB CacheCache 4 4-
WayCache Line 32byteCache Index
Cache Write-back Write-through Core Cache 64bit

z Cache Non-blocking HUMHit-Under-Miss
z MMUMemory Management Unit VxWorksLinuxWindowCE
PalmOS
z ARMv6
z 64bit ARM1176
1:11:2 1:3
z little endian
z FIQ IRQ
z JTAG
z
z 2KB ITCMInstruction TCM
z 600MHz
ARM926EJ-S
z 32bit ARM v5TEJ5 32bit ARM16bit Thumb
z DSP
z Java
z 16KB Cache16kB Cache4 CacheCache Line
32byte Cache write-back write-through
z Cache round-robin

3-14 02 (2010-01-19)

Hi3520
3
z ARM926EJ-S 1:1
1:2
z MMU VxWorksLinuxWindowCEPalmOS
z 2KB ITCMInstruction TCM
z little endian
z FIQFast Interrupt Request IRQInterrupt
Request
z JTAG
z
3.3.2
3.3.2.1 ARM1176
Hi3520 32bit 4GBHi3520
3
z NOR Flash
z NAND Flash
z DDR
3 ARM1176
EBIADR23 EBIADR24 3-17

3-17
EBIADR23 EBIADR24
NOR Flash
DDR
NAND Flash
DDR
NOR Flash
3-17 NOR Flash
NOR FlashHi3520 8bit NOR Flash
NOR Flash 3-3

02 (2010-01-19) 3-15

Hi3520
3
3-3 NOR Flash
0xFFFF_FFFF 0x201C_FFFF
DDR1 0x201C_0000 GPIO7
0xE000_0000
0x201B_0000 GPIO6
DDR0 GPIO5
0xC000_0000 0x201A_0000
0x2008_FFFF
0x2019_0000 GPIO4
PCI IPCM
0xB000_0000 GPIO3 0x2008_0000
0x2018_0000 IR
GPIO2 0x2007_0000
0x2017_0000 RTC
0x8800_0000 0x2006_0000
0x2016_0000 GPIO1

GPIO0 0x2005_0000
0x8600_0000 0x2015_0000 WDG
TDE 0x2004_0000
SMI1 0x2014_0000 Timer3
0x8400_0000 0x2003_0000
0x2013_0000 VOU
Timer2
DDRC1 0x2002_0000
0x8200_0000 0x2012_0000 Timer1
DDRC0 0x2001_0000
SMI0 0x2011_0000 Timer0
0x8000_0000 0x2000_0000
0x2010_0000
IO config 0x1011_0000
0x7400_0000 0x200F_0000 VIU
SPI 0x1010_0000
Nand Flash 0x200E_0000 VDEU1
0x100F_0000
0x7000_0000 0x200D_0000 I2C
0x100E_0000 VDEU0
UART3
0x201D_0000 0x200C_0000 DMAC
0x100D_0000
0x200B_0000 UART2
0x100C_0000 CIPHER
0x200A_0000 UART1
USB 2.0 HOST
0x2009_0000 UART0 0x100B_0000 EHCI
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000

VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
SIO0
0x1004_0000
MMC
0x1000_0000 0x1003_0000

0x1002_0000
0x0400_0000 SMI
0x1001_0000
SMI0
0x0000_0000 NANDC
0x1000_0000

3-16 02 (2010-01-19)

Hi3520
3
NOR Flash 3-4
z 2KB ITCM ITCM

2KB
z ITCM ARM CP15
ITCM ITCM MCR C9
0xD
3-4 NOR Flash

02 (2010-01-19) 3-17

Hi3520
3
0x201C_FFFF
0x201C_0000 GPIO7
0x201B_0000 GPIO6
0xFFFF_FFFF 0x201A_0000 GPIO5

DDR1 0x2008_FFFF
0x2019_0000 GPIO4
0xE000_0000 IPCM
GPIO3 0x2008_0000
DDR0 0x2018_0000 IR
0xC000_0000 GPIO2 0x2007_0000
0x2017_0000 RTC
PCI GPIO1 0x2006_0000
0x2016_0000
0xB000_0000 0x2005_0000
0x2015_0000 GPIO0
WDG
TDE 0x2004_0000
0x8800_0000 0x2014_0000 Timer3
VOU 0x2003_0000
0x2013_0000 Timer2
0x8600_0000 DDRC1 0x2002_0000
0x2012_0000 Timer1
SMI1 DDRC0 0x2001_0000
0x8400_0000 0x2011_0000 Timer0
0x2000_0000
0x2010_0000
0x8200_0000 IO config 0x1011_0000
0x200F_0000 VIU
SMI0 SPI 0x1010_0000
0x8000_0000 0x200E_0000 VDEU1
0x100F_0000
0x200D_0000 I2C
0x100E_0000 VDEU0
0x7400_0000 0x200C_0000 UART3
0x100D_0000 DMAC
Nand Flash UART2
0x200B_0000 CIPHER
0x7000_0000 0x100C_0000
0x200A_0000 UART1
USB 2.0 HOST

0x201D_0000 UART0 0x100B_0000 EHCI
0x2009_0000
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000
VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
0x1000_0000 SIO0
0x1004_0000
MMC
0x0400_0000 0x1003_0000

0x1002_0000
0x0000_0800 SMI
ITCM 0x1001_0000
0x0000_0000 NANDC
0x1000_0000
NAND Flash
3-17 NAND Flash
NAND FlashHi3520 8bit NAND Flash

3-18 02 (2010-01-19)

Hi3520
3
NAND Flash 3-5
3-5 NAND Flash
0x201C_FFFF
0x201C_0000 GPIO7
0x201B_0000 GPIO6
0xFFFF_FFFF
DDR1 0x201A_0000 GPIO5
0xE000_0000 0x2008_FFFF
0x2019_0000 GPIO4
IPCM
DDR0 GPIO3 0x2008_0000
0xC000_0000 0x2018_0000 IR
GPIO2 0x2007_0000
PCI 0x2017_0000 RTC
0xB000_0000 GPIO1 0x2006_0000
0x2016_0000
GPIO0 0x2005_0000
0x2015_0000 WDG
0x8800_0000 TDE 0x2004_0000
0x2014_0000 Timer3
0x2003_0000
0x8600_0000 0x2013_0000 VOU
Timer2
DDRC1 0x2002_0000
SMI1 0x2012_0000 Timer1
0x8400_0000 0x2001_0000
0x2011_0000 DDRC0
Timer0
0x2000_0000
0x8200_0000 0x2010_0000
SMI0 0x200F_0000 VIU
0x8000_0000 SPI 0x1010_0000
0x200E_0000 VDEU1
0x100F_0000
0x200D_0000 I2C
0x7400_0000 0x100E_0000 VDEU0
Nand Flash 0x200C_0000 UART3
0x100D_0000 DMAC
0x7000_0000 UART2
0x200B_0000 CIPHER
0x100C_0000
0x200A_0000 UART1
0x201D_0000 USB 2.0 HOST
0x2009_0000 UART0 0x100B_0000 EHCI
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000
VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
0x1000_0000 SIO0
0x1004_0000
MMC
0x0400_0000 0x1003_0000
Nand Flash
0x0000_0000 0x1002_0000
SMI
0x1001_0000
NANDC
0x1000_0000

02 (2010-01-19) 3-19

Hi3520
3
NAND Flash 3-6
3-6 NAND Flash
0x201C_FFFF
0x201C_0000 GPIO7
0x201B_0000 GPIO6

DDR1 0x2008_FFFF
0x2019_0000 GPIO4
0xE000_0000 IPCM
GPIO3 0x2008_0000
DDR0 0x2018_0000 IR
0xC000_0000 GPIO2 0x2007_0000
0x2017_0000 RTC
PCI GPIO1 0x2006_0000
0x2016_0000
0xB000_0000 0x2005_0000
0x2015_0000 GPIO0
WDG
TDE 0x2004_0000
0x8800_0000 0x2014_0000 Timer3
VOU 0x2003_0000
0x2013_0000 Timer2
0x8600_0000 DDRC1 0x2002_0000
0x2012_0000 Timer1
SMI1 DDRC0 0x2001_0000
0x8400_0000 0x2011_0000 Timer0
0x2000_0000
0x2010_0000
0x8200_0000 IO config 0x1011_0000
0x200F_0000 VIU
SMI0 SPI 0x1010_0000
0x8000_0000 0x200E_0000 VDEU1
0x100F_0000
0x200D_0000 I2C
0x100E_0000 VDEU0
0x7400_0000 0x200C_0000 UART3
0x100D_0000 DMAC
Nand Flash UART2
0x200B_0000 CIPHER
0x7000_0000 0x100C_0000
0x200A_0000 UART1
USB 2.0 HOST

0x201D_0000 UART0 0x100B_0000 EHCI
0x2009_0000
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000
VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
0x1000_0000 SIO0
0x1004_0000
MMC
0x0400_0000 0x1003_0000

0x1002_0000
0x0000_0800 SMI
ITCM 0x1001_0000
0x0000_0000 NANDC
0x1000_0000
DDR
3-17 DDR

1 ARM1176ZJF-S

3-20 02 (2010-01-19)

Hi3520
3
2 PCI 0x0000_0000( DDR )
3 PCI ARM1176ZJF-S
4 DDR
----
DDR 3-7
3-7 DDR
0x201C_FFFF
0x201C_0000 GPIO7
0x201B_0000 GPIO6
0xFFFF_FFFF
DDR1 0x201A_0000 GPIO5
0xE000_0000 0x2008_FFFF
0x2019_0000 GPIO4
IPCM
DDR0 GPIO3 0x2008_0000
0xC000_0000 0x2018_0000 IR
GPIO2 0x2007_0000
PCI 0x2017_0000 RTC
0xB000_0000 GPIO1 0x2006_0000
0x2016_0000
GPIO0 0x2005_0000
0x2015_0000 WDG
0x8800_0000 0x2004_0000
0x2014_0000 TDE
Timer3
0x8600_0000 VOU 0x2003_0000
0x2013_0000 Timer2
DDRC1 0x2002_0000
SMI1 0x2012_0000
0x8400_0000 Timer1
DDRC0 0x2001_0000
0x2011_0000 Timer0
0x2000_0000
0x8200_0000 0x2010_0000
SMI0 0x200F_0000 VIU
0x8000_0000 SPI 0x1010_0000
0x200E_0000 VDEU1
0x100F_0000
0x200D_0000 I2C
0x7400_0000 VDEU0
0x100E_0000
Nand Flash 0x200C_0000 UART3
DMAC
0x7000_0000 UART2
0x100D_0000
0x200B_0000 CIPHER
0x100C_0000
0x201D_0000 0x200A_0000 UART1
USB 2.0 HOST
0x2009_0000 UART0 0x100B_0000 EHCI
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000
VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
0x1000_0000 SIO0
0x1004_0000
MMC
0x0400_0000 0x1003_0000
DDR0
0x0000_0000 0x1002_0000
SMI
0x1001_0000
NANDC
0x1000_0000

02 (2010-01-19) 3-21

Hi3520
3
DDR 3-8
3-8 DDR
0x201C_FFFF
0x201C_0000 GPIO7
0x201B_0000 GPIO6

DDR1 0x2008_FFFF
0x2019_0000 GPIO4
0xE000_0000 IPCM
GPIO3 0x2008_0000
DDR0 0x2018_0000 IR
0xC000_0000 GPIO2 0x2007_0000
0x2017_0000 RTC
PCI GPIO1 0x2006_0000
0x2016_0000
0xB000_0000 0x2005_0000
0x2015_0000 GPIO0
WDG
TDE 0x2004_0000
0x8800_0000 0x2014_0000 Timer3
VOU 0x2003_0000
0x2013_0000 Timer2
0x8600_0000 DDRC1 0x2002_0000
0x2012_0000 Timer1
SMI1 DDRC0 0x2001_0000
0x8400_0000 0x2011_0000 Timer0
0x2000_0000
0x2010_0000
0x8200_0000 IO config 0x1011_0000
0x200F_0000 VIU
SMI0 SPI 0x1010_0000
0x8000_0000 0x200E_0000 VDEU1
0x100F_0000
0x200D_0000 I2C
0x100E_0000 VDEU0
0x7400_0000 0x200C_0000 UART3
0x100D_0000 DMAC
Nand Flash UART2
0x200B_0000 CIPHER
0x7000_0000 0x100C_0000
0x200A_0000 UART1
USB 2.0 HOST

0x201D_0000 UART0 0x100B_0000 EHCI
0x2009_0000
USB 2.0 HOST
0x100A_0000 OHCI
GMAC
0x1009_0000
VIC1
0x1008_0000
VIC0
0x1007_0000
SIO2
0x1006_0000
SIO1
0x1005_0000
0x1000_0000 SIO0
0x1004_0000
MMC
0x0400_0000 0x1003_0000

0x1002_0000
0x0000_0800 SMI
ITCM 0x1001_0000
0x0000_0000 NANDC
0x1000_0000
3.3.2.2 ARM926
ARM926 0x00xx_xxxx
0xAAxx_xxxxAA SC_PERIPHCTRL17 bit[7:0]
ARM1176

3-22 02 (2010-01-19)

Hi3520
3
ARM926 Hi3520 ARM1176

ARM926
1 SC_PERIPHCTRL17 bit[7:0] 0xC8
2 0xC800_0000 ARM926
3 SC_PERIPHCTRL8 bit[1] 1 ARM926
4 ARM926 0xC800_0000 boot
----
3.3.2.3
Hi3520 3-18
3-18 Hi3520
0xE000_0000 0xFFFF_FFFF DDR1 512MB

0xC000_0000 0xDFFF_FFFF DDR0 512MB

0xB000_0000 0xBFFF_FFFF PCI 256MB

3-19
0x8800_0000 0xAFFF_FFF 640MB -
0x8600_0000 0x87FF_FFFF 32MB -
0x8400_0000 0x85FF_FFFF SSMC 1 32MB -
0x8200_0000 0x83FF_FFFF 32MB -
0x8000_0000 0x81FF_FFFF SSMC 0 32MB -
0x7400_0000 0x7FFF_FFFF 64MB -
0x7000_0000 0x73FF_FFFF NAND Flash 64MB -

0x201D_0000 0x6FFF_FFFF 1278M -

B
0x201C_0000 0x201C_FFFF GPIO7 64KB -

02 (2010-01-19) 3-23

Hi3520
3
0x201B_0000 0x201B_FFFF GPIO6 64KB -
0x201A_0000 0x201A_FFFF GPIO5 64KB -
0x2019_0000 0x2019_FFFF GPIO4 64KB -
0x2018_0000 0x2018_FFFF GPIO3 64KB -
0x2017_0000 0x2017_FFFF GPIO2 64KB -
0x2016_0000 0x2016_FFFF GPIO1 64KB -
0x2015_0000 0x2015_FFFF GPIO0 64KB -
0x2014_0000 0x2014_FFFF TDE 64KB -
0x2013_0000 0x2013_FFFF VOU 64KB -
0x2012_0000 0x2012_FFFF DDRC1 64KB -
0x2011_0000 0x2011_FFFF DDRC0 64KB -
0x2010_0000 0x2010_FFFF 64KB -
0x200F_0000 0x200F_FFFF IO config 64KB -
0x200E_0000 0x200E_FFFF SPI 64KB -
0x200D_0000 0x200D_FFFF I2C 64KB -
0x200C_0000 0x200C_FFFF UART3 64KB -
0x200B_0000 0x200B_FFFF UART2 64KB -
0x200A_0000 0x200A_FFFF UART1 64KB -
0x2009_0000 0x2009_FFFF UART0 64KB -
0x2008_0000 0x2008_FFFF IPCM 64KB -

0x2007_0000 0x2007_FFFF IR 64KB -
0x2006_0000 0x2006_FFFF RTC 64KB -
0x2005_0000 0x2005_FFFF 64KB -
0x2004_0000 0x2004_FFFF WDG 64KB -
0x2003_0000 0x2003_FFFF Timer3 64KB -
0x2002_0000 0x2002_FFFF Timer2 64KB -
0x2001_0000 0x2001_FFFF Timer1 64KB -
0x2000_0000 0x2000_FFFF Timer0 64KB -
0x1011_0000 0x1FFF_FFFF 255MB -

3-24 02 (2010-01-19)

Hi3520
3
0x1010_0000 0x1010_FFFF VIU 64KB -
0x100F_0000 0x100F_FFFF VEDU1 64KB -
0x100E_0000 0x100E_FFFF VEDU0 64KB -
0x100D_0000 0x100D_FFFF DMAC 64KB -
0x100C_0000 0x100C_FFFF CIPHER 64KB -
0x100B_0000 0x100B_FFFF USB 2.0 HOST 64KB -

EHCI
0x100A_0000 0x100A_FFFF USB 2.0 HOST 64KB -

OHCI
0x1009_0000 0x1009_FFFF GMAC 64KB -
0x1008_0000 0x1008_FFFF VIC1 64KB -
0x1007_0000 0x1007_FFFF VIC0 64KB -
0x1006_0000 0x1006_FFFF SIO2 64KB -
0x1005_0000 0x1005_FFFF SIO1 64KB -
0x1004_0000 0x1004_FFFF SIO0 64KB -
0x1003_0000 0x1003_FFFF SDIO 64KB -
0x1002_0000 0x1002_FFFF 64KB -
0x1001_0000 0x1001_FFFF SSMC 64KB -
0x1000_0000 0x1000_FFFF NANDC 64KB -
0x0400_0000 0x0FFF_FFFF 192MB -
0x0000_0000 0x03FF_FFFF 64MB 3-17

EBIADR23
EBIADR24

ITCM
ITCM
2KB

0x0000_0000
0x0000_0800

02 (2010-01-19) 3-25

Hi3520
3
PCI 3-19
3-19 PCI
0xB000_0000 0xB000_03FF PCI 1KB -
0xB000_0400 0xB000_FFFF 63KB -
0xB001_0000 0xB001_FFFF IO 64KB PCI

0xB002_0000 0xB7FF_FFFF NP 127MB -
0xB800_0000 0xBFFF_FFFF FP 128MB -
3.4 INT
3.4.1
INTInterrupt SystermHi3520 INT VIC0
VIC1
3.4.2
INT
z 32
z INT
z IRQInterrupt Request FIQ
Fast Interrupt Request
z
z
z CPU
INT
3.4.3
INT 3-9

3-26 02 (2010-01-19)

Hi3520
3
3-9 INT
nFIQ
CPU
nIRQ
internal rawinterrupt intenable[31:0] intselect[31:0]

interrupt
sources[31:0]
softint[31:0]
fiqstatus[31:0]
INT irqstatus[31:0]
CPU INT
z INT_INTENABLE
z INT_INTSELECT
FIQ
z INT_SOFTINT INT_SOFTINTCLEAR

z INT_IRQSTATUS INT_FIQSTATUS
z INT_RAWINTR
1 ARM IRQ FIQ
3 System
4 INT_IRQSTATUS INT_FIQSTATUS

02 (2010-01-19) 3-27

Hi3520
3
5 ISR(Interrupt Service Routine)

INT_INTENABLE
INT_INTENABLE
6 ISR
7 INT_SOFTINTCLEAR
8 ARM CPSR IRQ FIQ
----
VIC0 VIC1 3-20
3-20 VIC0
0 WatchDog
2 COMMRX
3 COMMTX
4 Dual-Timer01
5 Dual-Timer23
6 GPIO0
7 GPIO1
8 GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7
9 IR
10 RTC
11 SPI
12 UART0 UART1
13 UART2 UART3
14 GMAC
15 DMAC
16 I2C
17 VIU

3-28 02 (2010-01-19)

Hi3520
3
18 TDE
19 VOU
20 VEDU0
21 VEDU1
22 USB 2.0 HOST OHCI
23 USB 2.0 HOST EHCI
24 SDIO
25 SIO0
26 SIO1
27 SIO2
28 CIPHER
29 PCI
30 NANDC
31 IPCM
COMMRXCOMMTX CPU
3-21 VIC1
0 WatchDog
2 COMMRX
3 COMMTX
4 Dual-Timer45
5 Dual-Timer67
6 GPIO0
7 GPIO1
8 GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7
9 IR

02 (2010-01-19) 3-29

Hi3520
3
10 RTC
11 SPI
12 UART0 UART1
13 UART2 UART3
14 GMAC
15 DMAC
16 I2C
17 VIU
18 TDE
19 VOU
20 VEDU0
21 VEDU1
22 USB 2.0 HOST OHCI
23 USB 2.0 HOST EHCI
24 SDIO
25 SIO0
26 SIO1
27 SIO2
28 CIPHER
29 PCI
30 NANDC
31 IPCM
COMMRXCOMMTX CPU
3.4.4
VIC0 VIC1
0x1007_0000 0x1008_0000 3-22

3-30 02 (2010-01-19)

Hi3520
3
3-22 INT
0x000 INT_IRQSTATUS IRQ 3-31
0x004 INT_FIQSTATUS FIQ 3-31
0x008 INT_RAWINTR 3-32
0x00C INT_INTSELECT 3-32
0x010 INT_INTENABLE 3-33
0x014 INT_INTENCLEAR 3-33
0x018 INT_SOFTINT 3-34
0x01C INT_SOFTINTCLEAR 3-34
0x020 INT_PROTECTION 3-35
3.4.5
INT_IRQSTATUS
INT_IRQSTATUS IRQ 32bit 32
3-20

0x000 INT_IRQSTATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name irqstatus
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IRQ
[31:0] RO irqstatus 0
1 IRQ
INT_FIQSTATUS
INT_FIQSTATUS FIQ 32bit 32

02 (2010-01-19) 3-31

Hi3520
3

0x004 INT_FIQSTATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name fiqstatus
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FIQ
[31:0] RO fiqstatus 0
1 FIQ
INT_RAWINTR
INT_RAWINTR
INT_SOFTINT 32bit 32

0x008 INT_RAWINTR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rawinterrupt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:0] RO rawinterrupt 0
1
INT_INTSELECT
INT_INTSELECT IRQ
FIQ 32bit 32

3-32 02 (2010-01-19)

Hi3520
3

0x00C INT_INTSELECT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name intselect
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:0] RW intselect 0IRQ
1FIQ
INT_INTENABLE
INT_INTENABLE
INT_INTENABLE 0x0000_000032bit 32


0x010 INT_INTENABLE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name intenable
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0
1
[31:0] RW intenable

0
1 1
INT_INTENCLEAR
INT_INTENCLEAR INT_INTENABLE

02 (2010-01-19) 3-33

Hi3520
3

0x014 INT_INTENCLEAR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name intenableclear
Reset
INT_INTENABLE
[31:0] WO intenableclear 0INT_INTENABLE
1INT_INTENABLE 0
INT_SOFTINT
INT_SOFTINT
INT_SOFTINTCLEAR


0x018 INT_SOFTINT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name softint
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:0] RW softint 0
1 1
INT_SOFTINTCLEAR
INT_SOFTINTCLEAR INT_SOFTINT

3-34 02 (2010-01-19)

Hi3520
3

0x01C INT_SOFTINTCLEAR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name softintclear
Reset
INT_SOFTINT
[31:0] WO softintclear 0INT_SOFTINT
1INT_SOFTINT 0
INT_PROTECTION
INT_PROTECTION
z 0user modeprivileged mode

INT
z CPU HPROT
INT

0x020 INT_PROTECTION 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
protection
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved

0CPU
[0] RW protection INT
1CPU INT

02 (2010-01-19) 3-35

Hi3520
3
3.5
3.5.1
DMA I/O
DMAC
DMA
Directory Memory AccessDMACDirectory
Memory Access Controller DMA CPU

CPU
3.5.2
DMAC
z 8bit16bit32bit
z 8 DMA
z DMA 07 2
DMA
z DMAC 0 5 1 4%32bit FIFODMAC 6 7
1 16%32bit FIFOFirst In First Out
z 2 32bit Master
z singleburst2 DMA
z 16 DMA
z DMA
z DMA burst
z DMA
z 4

z DMA
z DMAC
z 2 / ARM DMA DMA

z DMAC DMAC
3.5.3
3.5.3.1
DMAC 3-10

3-36 02 (2010-01-19)

Hi3520
3
3-10 DMAC
DMA
Req&Resp
AHB Bus AHB Slave Interface DMA Request and
and global config registers Response Interface
Transfer control logic and FIFOs

for Channel 07
AHB Master 0 AHB Master 1

DMAC
AHB Bus
DMAC FIFO

2 FIFO
3 FIFO
----
3.5.3.2
DMAC
1 DMAC DMA
// Master
DMAC
DMA
2 DMAC DMA DMAC DMA

3 DMAC DMA FIFO
4 DMAC DMA DMAC DMA

02 (2010-01-19) 3-37

Hi3520
3
5 DMAC DMA FIFO

6 23 45
DMAC DMA
DMA FIFO DMA FIFO

DMAC DMA
FIFO
DMAC 25

DMAC_CX_LLI 0
DMAC_CX_SRC_ADDRDMAC_CX_DEST_ADDRDMAC_CX_LLI
DMAC_CX_CONTROL 3-11 2
DMAC_CX_LLI 0 DMA

----
LLI 3-11
3-11 LLI
Channel Registers Linked Li st Item
DMAC_CX_SRC_ADDR DMAC_CX_SRC_ADDR
DMAC_CX_DEST_ADDR DMAC_CX_DEST_ADDR
DMAC_CX_LLI DMAC_CX_LLI
DMAC_CX_CONTROL DMAC_CX_CONTROL
DMAC_CX_CONFIG
3.5.3.3 DMA
DMA DMAC
DMA
DMAC 2 DMA
z DMACBREQ

3-38 02 (2010-01-19)

Hi3520
3
burst burst burst

z DMACSREQ
DMAC

DMAC DMACLR
DMAC DMA DMA
DMAC
DMAC 3-23
3-23 DMAC
DMAC
0 SIO0
1 SIO0
2 SIO1
3 SIO1
4 SIO2
5 SIO2
6 SPI
7 SPI
8 SDIO Read
9 SDIO Write
10 UART0 RX DMA
11 UART0 TX DMA
12 UART1 RX DMA
13 UART1 TX DMA
14 UART2 RX DMA
15 UART2 TX DMA

02 (2010-01-19) 3-39

Hi3520
3
DMA DMA 2 SIO1

3 SIO1 DMA 2
3
DMA DMA DMAC DMA

DMAC 67
IDLE Master
67
3.5.4
DMAC
1 DMAC_CONFIG DMAC Master1Master2 Endianness

DMAC_CONFIG[e] 1 DMAC
2 DMAC_INT_TC_CLR DMAC_INT_ERR_CLR 1

3 DMAC_SYNC 0 DMA
4 DMAC_CX_CONFIG[e] 0
----
DMAC DMA DMAC

1 DMAC_ENBLD_CHNS

2 DMAC_INT_TC_CLR DMAC_INT_ERR_CLR 1

1. DMAC_CX_SRC_ADDR
2. DMAC_CX_DEST_ADDR
3. DMAC_CX_LLI 0
4. DMAC_CX_LLI

5. DMAC_CX_CONTROL/ Master
/burst size transfer size
6. DMAC_CX_CONFIG DMA
DMAC_CX_CONFIG[e] 0
7. DMAC_CX_CONFIG
Channel Enable 1

3-40 02 (2010-01-19)

Hi3520
3
----
DMA
ARM
1 DMAC_INT_STAT ARM
DMAC_INT_STAT1

2 DMAC_INT_TC_STAT ARM
DMAC_INT_STAT1 1
4 3
3 DMAC_INT_ERR_STAT ARM
DMAC_INT_STAT1 1
5
4 3
1. DMAC_INT_TC_CLR 1
2. buffer
buffer
3.
5 3
1. DMAC_INT_ERR_CLR 1

2.
3.
----
3.5.5
DMAC 3-24
3-24 DMAC 0x100D_0000
0x000 DMAC_INT_STAT DMAC 3-44
0x004 DMAC_INT_TC_STAT DMAC 3-45

0x008 DMAC_INT_TC_CLR DMAC 3-45

02 (2010-01-19) 3-41

Hi3520
3
0x00C DMAC_INT_ERR_STAT DMAC 3-46
0x010 DMAC_INT_ERR_CLR DMAC 3-46
0x014 DMAC_RAW_INT_TC_STAT DMAC 3-47

0x018 DMAC_RAW_INT_ERR_STAT DMAC 3-47

0x01C DMAC_ENBLD_CHNS DMAC 3-48
0x020 DMAC_SOFT_BREQ burst DMA 3-49
0x024 DMAC_SOFT_SREQ Single DMA 3-49
0x028 DMAC_SOFT_LBREQ Last burst DMA 3-50

0x02C DMAC_SOFT_LSREQ Last Single DMA 3-51

0x030 DMAC_CONFIG DMAC 3-51
0x034 DMAC_SYNC DMAC 3-52
0x040 DMAC_INT_STAT1 DMAC 1 3-52
0x044 DMAC_INT_TC_STAT1 DMAC Terminal Count 3-53

1
0x048 DMAC_INT_ERROR_STAT1 DMAC 1 3-53
0x100 DMAC_C0_SRC_ADDR 0 3-52
0x104 DMAC_C0_DEST_ADDR 0 3-55
0x108 DMAC_C0_LLI 0 3-56
0x10C DMAC_C0_CONTROL 0 3-57
0x110 DMAC_C0_CONFIG 0 3-60
0x128 DMAC_C1_LLI 1 3-56

3-42 02 (2010-01-19)

Hi3520
3
0x148 DMAC_C2_LLI 2 3-56
0x168 DMAC_C3_LLI 3 3-56
0x188 DMAC_C4_LLI 4 3-56
0x1A0 DMAC_C5_SRC_ADDR 5 3-52
0x1A4 DMAC_C5_DEST_ADDR 5 3-55
0x1A8 DMAC_C5_LLI 5 3-56
0x1AC DMAC_C5_CONTROL 5 3-57
0x1B0 DMAC_C5_CONFIG 5 3-60
0x1C0 DMAC_C6_SRC_ADDR 6 3-52
0x1C4 DMAC_C6_DEST_ADDR 6 3-55
0x1C8 DMAC_C6_LLI 6 3-56
0x1CC DMAC_C6_CONTROL 6 3-57
0x1D0 DMAC_C6_CONFIG 6 3-60
0x1E0 DMAC_C7_SRC_ADDR 7 3-52
0x1E4 DMAC_C7_DEST_ADDR 7 3-55
0x1E8 DMAC_C7_LLI 7 3-56
0x1EC DMAC_C7_CONTROL 7 3-57
0x1F0 DMAC_C7_CONFIG 7 3-60

02 (2010-01-19) 3-43

Hi3520
3
3.5.6
DMAC_INT_STAT
DMAC_INT_STAT ARM
DMAC_INT_TC_STAT DMAC_INT_ERR_STAT
1 DMAC 1

3-44 02 (2010-01-19)

Hi3520
3

0x000 DMAC_INT_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
DMA bit[7:0] 7
0
[7:0] RO int_stat 0
1

DMAC_INT_TC_STAT
DMAC_INT_TC_STAT
ARM DMAC_CX_CONFIG[itc] X
07 DMAC_INT_STAT

0x004 DMAC_INT_TC_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_tc_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7
0
[7:0] RO int_tc_stat
0
1
DMAC_INT_TC_CLR
DMAC_INT_TC_CLR bit
1 DMAC_INT_TC_STAT DMAC_INT_TC_STAT1

02 (2010-01-19) 3-45

Hi3520
3

0x008 DMAC_INT_TC_CLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_tc_clr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7 0
[7:0] WO int_tc_clr 0
1
DMAC_INT_ERR_STAT
DMAC_INT_ERR_STAT
ARM DMAC_CX_CONFIG[ie]
DMAC_INT_STAT

0x00C DMAC_INT_ERR_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_err_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7
0
[7:0] RO int_err_stat
0
1
DMAC_INT_ERR_CLR
DMAC_INT_ERR_CLR bit 1
DMAC_INT_ERR_STAT DMAC_INT_ERR_STAT1

3-46 02 (2010-01-19)

Hi3520
3

0x010 DMAC_INT_ERR_CLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_err_clr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7 0
[7:0] WO int_err_clr 0
1
DMAC_RAW_INT_TC_STAT
DMAC_RAW_INT_TC_STAT


0x014 DMAC_RAW_INT_TC_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved raw_int_tc_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7 0
[7:0] RO raw_int_tc_stat 0
1
DMAC_RAW_INT_ERR_STAT
DMAC_RAW_INT_ERR_STAT

02 (2010-01-19) 3-47

Hi3520
3

0x018 DMAC_RAW_INT_ERR_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved raw_int_err_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7
0
[7:0] RO raw_int_err_stat
0
1
DMAC_ENBLD_CHNS
DMAC_ENBLD_CHNS
DMAC_ENBLD_CHNS 1
DMAC_CX_CONFIG DMA

DMAC_ENBLD_CHNS 0

0x01C DMAC_ENBLD_CHNS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved enabled_channels
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7 0
[7:0] RO enabled_channels 0
1

3-48 02 (2010-01-19)

Hi3520
3
DMAC_SOFT_BREQ
DMAC_SOFT_BREQ burst DMA burst

DMA burst
1 DMA
DMA DMA

0x020 DMAC_SOFT_BREQ 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved soft_breq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
DMA burst
3-23

0
1 DMA burst
[15:0] RW soft_breq 0

0 DMACBREQ[15:0] DMA burst

1 DMACBREQ[15:0] DMA
burst
DMAC_SOFT_SREQ
DMAC_SOFT_SREQ Single DMA

DMA DMAC 16
DMA 1 DMA
DMA DMA

02 (2010-01-19) 3-49

Hi3520
3

0x024 DMAC_SOFT_SREQ 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved soft_sreq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
DMA single
3-23

0
1 DMA single
[15:0] RW soft_sreq 0

signal
signal
DMAC_SOFT_LBREQ
DMAC_SOFT_LBREQ burst DMA
last burst

0x028 DMAC_SOFT_LBREQ 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved soft_lbreq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
last burst 3-23

0
[15:0] WO soft_lbreq
1 DMA last burst
0

3-50 02 (2010-01-19)

Hi3520
3
DMAC_SOFT_LSREQ
DMAC_SOFT_LSREQ single DMA
last single

0x02C DMAC_SOFT_LSREQ 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved soft_lsreq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
last single 3-
23
[15:0] WO soft_lsreq 0
1 DMA last single
0
DMAC_CONFIG
DMAC_CONFIG DMAC m1
bit[1] m2bit[2] DMAC 2 Master endianness
DMAC 2 Master little endian
2 Master little endian

0x030 DMAC_CONFIG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved m2 m1 e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:3] - reserved
Master2 endianness
[2] RW m2 0little endian
1big endian

02 (2010-01-19) 3-51

Hi3520
3
Master1 endianness
[1] RW m1 0little endian
1big endian
DMAC
[0] RW e 0 DMAC
1 DMAC
DMAC_SYNC
DMAC_SYNC DMA

0x034 DMAC_SYNC 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved dmac_sync
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved

3-23
[15:0] RW dmac_sync
0 DMA
1 DMA
DMAC_INT_STAT1
DMAC_INT_STAT1 ARM
DMAC_INT_STAT1 DMAC_INT_ERR_STAT1
1 DMAC 1

0x040 DMAC_INT_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

3-52 02 (2010-01-19)

Hi3520
3
[31:8] - reserved
DMA bit[7:0] 7
0
[7:0] RO int_stat 0
1

DMAC_INT_TC_STAT1
DMAC_INT_TC_STAT1
ARM DMAC_CX_CONFIG[itc] X
07 DMAC_INT_STAT1

0x044 DMAC_INT_TC_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_tc_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7
0
[7:0] RO int_tc_stat
0
1
DMAC_INT_ERR_STAT1
DMAC_INT_ERR_STAT1
ARM DMAC_CX_CONFIG[ie]
DMAC_INT_STAT1

02 (2010-01-19) 3-53

Hi3520
3

0x048 DMAC_INT_ERR_STAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved int_err_stat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
bit[7:0] 7
0
[7:0] RO int_err_stat
0
1
DMAC_CX_SRC_ADDR
DMAC_CX_SRC_ADDR

0x100+X%0x20 X 07 DMA 0
7

z
z

DMAC

0x100+X % 0x20 DMAC_CX_SRC_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name src_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW src_addr DMA

3-54 02 (2010-01-19)

Hi3520
3
z DMAC 8 5
z DMAC_CX_SRC_ADDR
z DMAC_CX_DEST_ADDR
z DMAC_CX_LLI
z DMAC_CX_CONTROL
z DMAC_CX_CONFIG
DMA 4 DMAC
DMA DMAC

DMAC_CX_DEST_ADDR
DMAC_CX_DEST_ADDR 0x104+X%0x20X
07 DMA 0 7
DMAC_CX_DEST_ADDR

z
z

DMAC

0x104+X % 0x20 DMAC_CX_DEST_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dest_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW dest_addr DMA

02 (2010-01-19) 3-55

Hi3520
3
DMAC_CX_LLI
DMAC_CX_LLI 0x108+X0x20X 0
7 DMA 0 7
DMAC
z DMAC_CX_SRC_ADDR
z DMAC_CX_DEST_ADDR
z DMAC_CX_LLI
z DMAC_CX_CONTROL/ Master/
burst size transfer size
DMAC 3-12
3-12 DMAC
SRC_ADDR SRC_ADDR SRC_ADDR SRC_ADDR
DEST_ADDR DEST_ADDR DEST_ADDR DEST_ADDR
LLI LLI LLI LLI
CONTROL CONTROL CONTROL CONTROL
LLI 1 0xFFFF_FFF0 1 4 burst

0x0000_0000

LLI 0


0x108+X%0x20 DMAC_CXLLI 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name lli lm
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

3-56 02 (2010-01-19)

Hi3520
3
Linked list item[31:2][1:0]

[31:2] RW lli
0 4
[1] RW reserved 0
Master
[0] RW lm 0Master1
1Master2
DMAC_CX_CONTROL
DMAC_CX_CONTROL 0x10C+X0x20X
07 DMA 0 7
DMA burst

0x10C+X% 0x20 DMAC_CX_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name i prot di si d s dwidth swidth dbsize sbsize transfersize
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31] RW i
0
1
Master HPROT[2:0]
[30:28] RW prot
3-27

0
[27] RW di 1

[26] RW si

02 (2010-01-19) 3-57

Hi3520
3
0
1

Master
[25] RW d 0SIO0SIO1UART0SDIOSPI Master1
1NORFlashDDR Master2
Master
[24] RW s 0SIO0SIO1UART0SDIOSPI Master1
1NORFlashDDR Master2

Master
[23:21] RW dwidth
pack unpack
DWidth 3-26

Master
[20:18] RW swidth
pack unpack
SWidth 3-26
burst
1 burst
DMACCxBREQ
[17:15] RW dbsize
burst

DBSize 3-25
burst
1 burst
DMACCxBREQ
[14:12] RW sbsize
burst

SBSize 3-25
DMA DMAC
transfer size
[11:0] RW transfersize

3-58 02 (2010-01-19)

Hi3520
3
DMAC_CX_CONTROL DBSize SBSize burst 3-

25
3-25 DBSize SBSize burst
DBSize SBSize burst
000 1
001 4
010 8
011 16
100 32
101 64
110 128
111 256
DMAC_CX_CONTROL DWidth SWidth 3-26

3-26 DWidth SWidth
SWidth DWidth
000 Byte8bit
001 Halfword16bit
010 Word32bit
DMAC_CX_CONTROL
z transfer size
FIFO
z SWidth DWidth
z transfer size 0 DMAC DMAC
DMA
z DMAC_CX_CONTROL / transfer
size

02 (2010-01-19) 3-59

Hi3520
3
DMAC

z transfer size FIFO
FIFO DMAC FIFO DMAC
FIFO
Master
DMAC_CX_CONTROL[prot]
DMAC_CX_CONFIG[Lock] 3-27 prot 3
3-27 DMAC_CX_CONTROL Prot
[2] Cacheable or Cache Cache

nonCacheable
0 Cache
1 Cache
HPROT[3]
[1] bufferable or
nonbufferable
0
1
HPROT[2]
[0] privileged or user

0
1
HPROT[1]
DMAC_CX_CONFIG
DMAC_CX_CONFIG 0x110+X%0x20X
07 DMA 0 7

3-60 02 (2010-01-19)

Hi3520
3

0x110+X%0x20 DMAC_CX_CONFIG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
itc
Name reserved h a l ie flow_cntrl dest_peripheral src_peripheral e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:21] - reserved
0

[20] ITC1 R/W 0 ARM
1 ARM

[19] IE1 R/W 0 ARM
1 ARM
Active
0 FIFO
[17] RO a 1 FIFO
Halt Channel Enable
DMA
Lock
[16] RW l 0 lock
1 lock

[15] RW itc 0 ARM
1 ARM

[14] RW ie 0 ARM
1 ARM

[13:11] RW flow_cntrl DMAC

3-28

02 (2010-01-19) 3-61

Hi3520
3

[10] - reserved
0

[9:6] RW dest_peripheral DMA
DMA

[5] - reserved
0

[4:1] RW src_peripheral DMA
DMA

DMACEnbldChns
0
1
0 0
FIFO
LLI
[0] RW e 0
FIFO Halt 1
DMA active
0 FIFO enable

1
1

Channel Enable DMAC_ENBLD_CHNS bit 0
Channel Enable 1 Channel Enable 0
burst
3-28 DMAC_CX_CONFIG flow_cntrl
3-28
000 DMAC
001 DMAC
010 DMAC
011 DMAC

3-62 02 (2010-01-19)

Hi3520
3
3.6 CIPHER
3.6.1
CIPHER DESData Encryption Standard/3DES AESAdvanced
Encryption StandardDES/3DES AES FIPS46-
3/FIPS 197 DES/3DES AES FIPS -81/NIST special800-38a

CIPHER

3.6.2
CIPHER
z AES 128192256
z DES 64
z 3DES 3 2
z AES ECBElectronic CodeBook
CBCCipher Block Chaining1/8/128-
CFBCipher FeedBack128-OFBOutput FeedBack CTRCounter
NIST special800-38a
z DES/3DES ECBCBC1/8/64-CFB1/8/64-OFB
FIPS-81
z ECBCBCCFBOFB

z AES CTR
z
z
z

3.6.3
DES/3DESAES FIPS-81 NIST special800-
38a DES/3DES AES ECBCBC CFB OFB
CTR AES
3DES
3DES 3 2 2 3
2 key3key1
3 2 3DES 3-13

02 (2010-01-19) 3-63

Hi3520
3
3-13 3 2 3DES
3DES 3DES
key1 key1
DES DES
key2 key2
DES DES
key3 key1
DES DES
3 2
3 2 3DES 3-14
3-14 3 2 3DES
3DES 3DES
key3 key1
DES DES
key2 key2
DES DES
key1 key1
DES DES
3 2
ECB
ECBElectronic CodeBook

AES/DES 3DES ECB 3-15 3-16

3-64 02 (2010-01-19)

Hi3520
3
3-15 AES/DES ECB
Pi Ci
key key
AES/DES AES/DES
Ci Pi
ECB ECB
3-16 3DES ECB
3DES 3DES
key1 key3
DES DES
key2 key2
DES DES
key3 key1
DES DES
ECB ECB
CBC
CBCCipher Block Chaining IV
Intialization Vector
CBC

AES/DES 3DES CBC 3-17 3-18

02 (2010-01-19) 3-65

Hi3520
3
3-17 AES/DES CBC
IV P1 P2 Pn
key key key

AES/DES AES/DES AES/DES
C1 C2 Cn
CBC
C1 C2 Cn
key key key

IV P1 P2 Pn
CBC

3-66 02 (2010-01-19)

Hi3520
3
3-18 3DES CBC
IV
3DES 3DES
key3
DES DES
3DES 3DES
3DES
key1
DES DES key2
DES DES
key2 DES
DES key1
DES DES
key3
DES DES
IV
CBC CBC
CFB
CFBCipher FeedBack
CFB s s 2

z DES/3DESs 1 8 64
z AESs 1 8 128
AES/DES s CFB 3DES s CFB

3-19 3-20

02 (2010-01-19) 3-67

Hi3520
3
3-19 AES/DES s CFB
IV (128-s) s (128-s) s
key key key


s (128-s) s (128-s) s (128-s)
s s s
P1 P2 Pn
s s s
C1 C2 Cn
CFB
IV (128-s) s (128-s) s
key key key


s (128-s) s (128-s) s (128-s)
s s s
C1 C2 Cn
s s s
P1 P2 Pn
CFB

3-68 02 (2010-01-19)

Hi3520
3
3-20 3DES s CFB

s s
IV IV s
(64-s) s (64-s)
3DES 3DES
key1 DES key1
DES
DES key2 key2

DES
key3 key3
DES DES
s s
(64-s) (64-s)

s s
(s) (s)
OFB
OFBOutput FeedBack IV
IV s
2
z DES/3DESs 1 8 64
z AESs 128

02 (2010-01-19) 3-69

Hi3520
3
AES OFB 3-21
3-21 AES OFB
IV1
key key key

AES AES AES

P1 P2 Pn

C1 C2 Cn
OFB
IV1
key key key

AES AES AES

C1 C2 Cn

P1 P2 Pn
OFB
DES s 3-22

3-70 02 (2010-01-19)

Hi3520
3
3-22 DES s OFB
IV (64-s) s (64-s) s
key key key

DES DES DES

s (64-s) s (64-s) s (64-s)
s s s
P1 P2 Pn
s s s
C1 C2 Cn
OFB
IV (64-s) s (64-s) s
key key key

DES DES DES

s (64-s) s (64-s) s (64-s)
s s s
C1 C2 Cn
s s s
P1 P2 Pn
OFB
3DES s 3-23

02 (2010-01-19) 3-71

Hi3520
3
3-23 3DES s OFB

s s
IV IV
(64-s) s (64-s) s
3DES 3DES
key1 DES key1
DES
DES key2 key2

DES
key3 key3
DES DES
s s
(64-s) (64-s)

s s
(s) (s)
CTR
CTRCounter AES
CTRn

CTRn
AES CTR 3-24

3-72 02 (2010-01-19)

Hi3520
3
3-24 AES CTR
CTR1 CTR2 CTRn
key key key

AES AES AES
P1 P2 Pn
C1 C2 Cn
CTR
CTR1 CTR2 CTRn
key key key

AES AES AES
C1 C2 Cn
P1 P2 Pn
CTR
3.6.4
CIPHER
CIPHER
1 CIPHER_BUSY 0 2
2 CIPHER_CTRL
3 CIPHER_DINCIPHER_IVIN CIPHER_KEY
4 CIPHER_ST 0x1
5 2
z 6
z CIPHER_BUSY 0
6
6 CIPHER_DOUTCIPHER_IVOUT
----

02 (2010-01-19) 3-73

Hi3520
3

z CIPHER_KEY

z CBCCFB OFB
CIPHER_IVOUT CIPHER_IVIN
2
CIPHER_CTRL[ivin_sel] 0 CIPHER_DIN
CIPHER_CTRL[ivin_sel] 1 CIPHER_CTRL
z CBCCFB OFB CIPHER_IVIN
CIPHER_IVOUT
CIPHER_IVIN CIPHER_CTRL[ivin_sel] 1
CIPHER
CIPHER
1 CIPHER_BUSY 0 2

2 CIPHER_CTRL
3 SRC_START_ADDRDEST_START_ADDR
MEM_LENGTH
4 CIPHER_IVIN CIPHER_KEY
5 CIPHER_ST 0x1
6
z 7
z CIPHER_BUSY 0
7
7 CIPHER_IVOUT
----
AES CTR

CPU CPU
CIPHER_ST
CPU

3-74 02 (2010-01-19)

Hi3520
3

z CIPHER_KEY
z
z CBCCFB OFB
2
CIPHER_BUSY[cipher_busy]=0b0
CIPHER
z SC_PERDIS[cipherclkdis] 1 CIPHER
z SC_PEREN[cipherclken] 1 CIPHER

z SC_PERCTRL8[cipher_srst] 1 CIPHER
z SC_PERCTRL8[cipher_srst] 0 CIPHER

3.6.5
3-29 CIPHER 0x100C_0000
0x0000x004 CIPHER_DIN CIPHER 128 3-76

0x0080x00C
0x0100x014 CIPHER_IVIN CIPHER 3-77

0x0180x01C ECB
0x0200x024 CIPHER_KEY CIPHER 3-78

0x0280x02C
0x0300x034
0x0380x03C
0x0400x044 CIPHER_DOUT CIPHER 128 3-79

0x0480x04C

02 (2010-01-19) 3-75

Hi3520
3
0x0500x054 CIPHER_IVOUT CIPHER 3-80

0x0580x05C ECBCTR

0x060 CIPHER_CTRL CIPHER 3-81
0x064 INT_CIPHER CIPHER 3-84
0x068 CIPHER_BUSY CIPHER 3-85
0x06C CIPHER_ST CIPHER / 3-85

0x070 SRC_START_A memory 3-86

DDR
0x074 MEM_LENGTH 32 3-86

0x078 DEST_START_ memory 3-88

ADDR
0x07C INT_MASK CIPHER 3-88
0x080 INT_CIPHER_S CIPHER 3-89

TATUS
3.6.6
CIPHER_DIN
CIPHER_DIN CIPHER 128
CIPHER_CTRL[cipher_mode]=0b0

z AES CIPHER_CTRL[alg_sel]=0b10
1-CFB CIPHER_CTRL bit[5:1]=0b10010 1
CIPHER_DIN bit[0]
CIPHER_DIN bit[7:0]
128-CFB CIPHER_CTRL bit[5:1]=0b00010 0b11010128

128
z DES 3DES CIPHER_CTRL[alg_sel]0b000b01
0b11

3-76 02 (2010-01-19)

Hi3520
3
1-CFB/1-OFB CIPHER_CTRL bit[5:1]=0b10010 0b10011

1 CIPHER_DIN bit[0]
8-CFB/8-OFB CIPHER_CTRL bit[5:1]=0b01010 0b01011

8 CIPHER_DIN bit[7:0]
64-CFB/64-OFB CIPHER_CTRL bit[5:1]=0b000100b11010
0b00011 0b11011 64 CIPHER_DIN bit[63:0]
64 CIPHER_DIN bit[63:0]



0x0000x00C CIPHER_DIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cipher_din
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CIPHER 128 32

CIPHER_DIN[31:0]0x000
[31:0] RW cipher_din
CIPHER_DIN[127:96]0x00C
CIPHER_IVIN
CIPHER_IVIN CIPHER

z CIPHER_CTRL bit[cipher_mode]=0b0
ECB CIPHER_CTRL[mode]=0b0010b0100b011 0b100
CIPHER_CTRL[ivin_sel]=0b0

AES CIPHER_CTRL
[alg_sel]=0b10CIPHER_IVIN bit[127:0] DES
3DES CIPHER_CTRL[alg_sel]0b000b01 0b11 64
CIPHER_IVIN bit[63:0]
z CIPHER_CTRL[cipher_mode]=0b1
ECB CIPHER_CTRL[mode]=0b0010b010 0b011

02 (2010-01-19) 3-77

Hi3520
3


0x0100x01C CIPHER_IVIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cipher_ivin
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CIPHER 128 IV Counter

32
CIPHER_IVIN[31:0]0x010
[31:0] RW cipher_ivin
CIPHER_IVIN[127:96]0x01C
CIPHER_KEY
CIPHER_KEY CIPHER

z DES CIPHER_CTRL[alg_sel]=0b00 0b11 64
CIPHER_KEY[63:0]
z 3DES CIPHER_CTRL[alg_sel]=0b01

3 CIPHER_CTRL[key_length]=0b000b01 0b10 192

CIPHER_KEY bit[63:0]
2 CIPHER_CTRL[key_length]=0b11 128

128 CIPHER_CTRL[key_length]=0b00 0b11
128 CIPHER_KEY bit[127:0]

3-78 02 (2010-01-19)

Hi3520
3
192 CIPHER_CTRL[key_length]=0b01 192

256 CIPHER_CTRL[key_length]=0b10256

0x0200x03C CIPHER_KEY 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cipher_key
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CIPHER 1 32

CIPHER_KEY[31:0]0x020
[31:0] RW cipher_key
CIPHER_KEY[127:96]0x02C
CIPHER_KEY[255:224]0x03C
CIPHER_DOUT
CIPHER_DOUT CIPHER 128
AES DES 3DES
1-CFB CIPHER_CTRL bit[5:1]=0b10010
CIPHER_DOUT bit[0]
CIPHER_DOUT bit[7:0]
128-CFB CIPHER_CTRL bit[5:1]=0b00010 0b11010128

128
z DES 3DES CIPHER_CTRL[alg_sel]=0b000b01 0b11

02 (2010-01-19) 3-79

Hi3520
3
1-CFB 1-OFB CIPHER_CTRL bit[5:1]=0b10010

0b10011 1 CIPHER_DOUT bit[0]
0b01011 8 CIPHER_DOUT bit[7:0]
0b000110b11010 0b11011 64 CIPHER_DOUT bit[63:0]

64 CIPHER_DOUT bit[63:0]


0x0400x04C CIPHER_DOUT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cipher_dout
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CIPHER 128 1 32

CIPHER_DOUT[31:0]0x040
[31:0] RO cipher_dout
CIPHER_DOUT[127:96]0x04C
CIPHER_IVOUT
CIPHER_IVOUT CIPHER

z ECB CTR CIPHER_CTRL[mode]=0b0000b100
0b1010b110 0b111


AES CIPHER_CTRL[alg_sel]=0b10128

DES 3DES CIPHER_CTRL[cipher_mode]=0b000b01
0b11 64 CIPHER_IVOUT bit[63:0]
z CIPHER_CTRL[ivin_sel]=0b1

3-80 02 (2010-01-19)

Hi3520
3
AES CIPHER_CTRL[cipher_mode]=0b10
128

DES 3DES CIPHER_CTRL[cipher_mode]0b00
0b01 0b11 64 CIPHER_IVOUT bit[63:0]

0x0500x05C CIPHER_IVOUT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cipher_ivout
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CIPHER IV ECBCTR
1 32
CIPHER_IVOUT[31:0]0x050
[31:0] RO cipher_ivout
CIPHER_IVOUT[127:96]0x05C
CIPHER_CTRL
CIPHER_CTRL CIPHER

z
z AES CTR AES CTR
CIPHER_CTRL[cipher_mode] 1
z AES CFB CIPHER_CTRL[width] 01
10
z DES/3DES CFB OFB
CIPHER_CTRL[width] 01 10
z CIPHER_CTRL[byte_seq_reg] CIPHER_CTRL[byte_seq_ram]
/
DES
7654321 0x3736_3534_3332_3120

0x0 0x3435_3637
0x4 0x2031_3233
0x0 byte_seq_ram
byte_seq_reg 1

02 (2010-01-19) 3-81

Hi3520
3

0x060 CIPHER_CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
byte_seq_ram
dest_addr_set
byte_seq_reg
cipher_mode
key_length
ivin_sel
decrypt
alg_sel
width
mode
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:15] - reserved
memory
[14] RW byte_seq_ram 0
1

0
[13] RW byte_seq_reg 1
CIPHER_KEYCIPHER_IVIN
CIPHER_DIN
CIPHER_IVOUTCIPHER_DOUT
memory

0
SRC_START_ADDR
[12] RW dest_addr_set
DEST_START_ADDR
1
SRC_START_ADDR
DEST_START_ADDR
CIPHER
[11] RW cipher_mode 0
1
CIPHER_IVIN
[10] RW ivin_sel 0CIPHER_IVIN
1CIPHER_IVIN

3-82 02 (2010-01-19)

Hi3520
3

00DES
[9:8] RW alg_sel 013DES
10AES
11DES

AES
00128
01192
10256
[7:6] RW key_length 11128
3DES
00192 3
01192 3
10192 3
11128 2

DES/3DES
0064
018
101
[5:4] RW width 1164
AES
00128
018
101
11128

02 (2010-01-19) 3-83

Hi3520
3

AES
000ECB
001CBC
010CFB
011OFB
100CTR
[3:1] RW mode
ECB
DES
000ECB
001CBC
010CFB
011OFB
ECB

[0] RW decrypt 0
1
INT_CIPHER
INT_CIPHER INT_CIPHER_STATUS
INT_MASK

0x064 INT_CIPHER 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
int_error
int_done
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
CIPHER word

[1] RO int_error
0
1

3-84 02 (2010-01-19)

Hi3520
3
CIPHER
[0] RO int_done 0
1
CIPHER_BUSY
CIPHER_BUSY

0x068 CIPHER_BUSY 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cipher_busy
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
CIPHER
[0] RO cipher_busy 0 CIPHER
1 CIPHER
CIPHER_ST
CIPHER_ST CIPHER /

z CIPHER_ST 0x0000_0001 CIPHER
z CIPHER_ST 0x0000_0000 CIPHER
z CIPHER_CTRL bit[11]=0b1

02 (2010-01-19) 3-85

Hi3520
3

0x06C CIPHER_ST 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cipher_st
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
CIPHER /
[0] RW cipher_st 0 CIPHER
1 CIPHER
SRC_START_ADDR
SRC_START_ADDR memory
CIPHER

0x070 SRC_START_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name src_start_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW src_start_addr memory
MEM_LENGTH
MEM_LENGTH 32

CIPHER
z AES

3-86 02 (2010-01-19)

Hi3520
3
ECBCBCOFB CTR CIPHER_CTRL[mode]=0b000

0b0010b0110b1000b1010b110 0b111 mem_length
4
128-CFB CIPHER_CTRL[mode]=0b010 CIPHER_CTRL
[width]=0b00 0b11 mem_length 4
8-CFB CIPHER_CTRL[mode]=0b010 CIPHER_CTRL
[width]=0b01 mem_length
mem_length=0x0000_0001
data[31:0]
data[7:0]
data[15:0]
16

1-CFB CIPHER_CTRL[mode]=0b010
CIPHER_CTRL[width]=0b10 mem_length

data[31:0] data[0]

data[1:0] 2

z DES/3DES
ECB CBC CIPHER_CTRL[mode]=0b0000b0010b100
0b1010b110 0b111
mem_length
64-CFB 64-OFB CIPHER_CTRL[mode]=0b010 0b011
CIPHER_CTRL[width]=0b00 0b11
mem_length
mem_length
=0x0000_0001 data[31:0]
data[7:0]

data[15:0] 16


data[31:0] data[0]

data[1:0] 2

02 (2010-01-19) 3-87

Hi3520
3

0x074 MEM_LENGTH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name mem_length
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW mem_length 32
DEST_START_ADDR
DEST_START_ADDR memory

z
CIPHER_CTRL[dest_addr_set]=0b0
z
CIPHER_CTRL[dest_addr_set]=0b1
0x078 DEST_START_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dest_start_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW dest_start_addr memory
INT_MASK
INT_MASK
INT_MASK
z INT_MASK 0x0000_0003 CIPHER
INT_CIPHER_STATUS INT_CIPHER
bit[1:0]=0b00
z INT_MASK 0x0000_0001 CIPHER
INT_CIPHER_STATUS int_done_status
INT_CIPHER[int_done]=0b0

3-88 02 (2010-01-19)

Hi3520
3
z INT_CIPHER_STATUS 0x0000_0002 CIPHER

INT_CIPHER_STATUS int_error_status
INT_CIPHER[int_error]=0b0
0x07C INT_MASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
int_done_mask
int_error_mask
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
int_error
[1] RW int_error_mask 0
1
int_done
[0] RW int_done_mask 0
1
INT_CIPHER_STATUS
INT_CIPHER_STATUS 1 0
INT_CIPHER_STATUS
INT_CIPHER_STATUS 0
INT_DONE_STATUS
int_error_status

02 (2010-01-19) 3-89

Hi3520
3

0x080 INT_CIPHER_STATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
int_error_status
int_done_status
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
CIPHER Master AHB

word slave
[1] WC int_error_status
0
1
CIPHER
[0] WC int_done_status 0
1
3.7 Timer
3.7.1
Timer
Timer 4 Dual-Timer Dual-Timer0Dual-
Timer1Dual-Timer2 Dual-Timer34 Dual-Timer

z Dual-Timer0 Timer0Timer1
Dual-Timer Timer
Dual-Timer0Dual-Timer1 ARM1176Dual-Timer2Dual-Timer3
ARM926

3-90 02 (2010-01-19)

Hi3520
3
3.7.2
Dual-Timer
z 2 8 32bit/16bit /
z APB 3MHz

z 3
z 2 TIMERx_LOAD TIMERx_BGLOAD

z
z 0
3.7.3
Hi3520 Timer Hi3520 4 Dual-Timer

Timer 32bit/16bit
1Timer
Timer 3
z
0
32bit 0xFFFF_FFFF 16bit
0xFFFF
0
z
0 TIMERx_BGLOAD

z
0

Timer prescaler
Timer
1 16 256

z TIMERx_LOAD
TIMERx_LOAD

02 (2010-01-19) 3-91

Hi3520
3
z TIMERx_BGLOAD
0
TIMERx_BGLOAD
3.7.4
Timer TimerXTimerX X 0
123456 7
1 TIMERx_LOAD Timer
2 Timer Timer
TIMERx_BGLOAD Timer
3 SC_CTRL Timer
4 TIMERx_CONTROL Timer
Timer
----
Timer Timer

1 TIMERx_INTCLR Timer
----
4 Timer1 2 Timer0
APB
1 SC_CTRL[timeren0ov]=1
2 Timer
----
3MHz
1 SC_CTRL[timeren0sel]=0
2 Timer

3-92 02 (2010-01-19)

Hi3520
3
----
3.7.5
Timer 8
z Timer0Timer1 0x2000_0000
TIMERx x 01234567
3-30 Timer 0x2000_00000x2001_00000x2002_0000

0x2003_0000
Timer0/2/4/6 Timer1/3/5/7

0x000 0x020 TIMERx_LOAD 3-93
0x004 0x024 TIMERx_VALUE 3-94
0x008 0x028 TIMERx_CONTROL 3-95
0x00C 0x02C TIMERx_INTCLR 3-98
0x010 0x030 TIMERx_RIS 3-98
0x014 0x034 TIMERx_MIS 3-99
0x018 0x038 TIMERx_BGLOAD 3-100

3.7.6
z TIMER0_XXXXTIMER2_XXXXTIMER4_XXXX TIMER6_XXXX
4 TIMER0_XXXX
z TIMER1_XXXXTIMER3_XXXXTIMER5_XXXX TIMER7_XXXX
3 TIMER1_XXXX
3.7.6.1 TIMERx_LOAD
TIMERx_LOAD Timer07 1

0 TIMERx_LOAD
TIMERx_LOAD TIMCLKENx
TIMCLK

02 (2010-01-19) 3-93

Hi3520
3
z TIMERx_LOAD 1
z TIMERx_LOAD 0 Dual-Timer 1
TIMERx_BGLOAD TIMERx_LOAD

TIMCLKENx TIMCLK TIMERx_BGLOAD

TIMERx_LOAD TIMCLKENx TIMCLK
TIMERx_LOAD
0 TIMERx_BGLOAD TIMERx_LOAD

TIMERx_BGLOAD TIMERx_LOAD 2
TIMERx_LOAD TIMERx_BGLOAD
TIMER0_LOAD
0x000 TIMER0_LOAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer0_load
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW timer0_load Timer0
TIMER1_LOAD
0x020 TIMER1_LOAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer1_load
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW timer1_load Timer1
3.7.6.2 TIMERx_VALUE
TIMERx_VALUE
Timer07 1

3-94 02 (2010-01-19)

Hi3520
3
TIMERx_LOAD TIMERx_VALUE PCLK

TIMCLKENx TIMCLK

16bit 32 TIMERx_VALUE 16 0
32bit 16bit TIMERx_LOAD
TIMERx_VALUE 16
TIMER0_VALUE
0x004 TIMER0_VALUE 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer0_value
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:0] RO timer0_value Timer0
TIMER1_VALUE
0x024 TIMER1_VALUE 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer1_value
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:0] RO timer1_value Timer1
3.7.6.3 TIMERx_CONTROL
TIMERx_CONTROL Timer07 1
TIMERx_CONTROL[timermode] 1
TIMERx_CONTROL[oneshot] 0

02 (2010-01-19) 3-95

Hi3520
3
TIMER0_CONTROL
0x008 TIMER0_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timermode
intenable
timersize
reserved
timerpre
oneshot
timeren
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved

[7] RW timeren 0
1

[6] RW timermode 0
1

[5] RW intenable 0
1
[4] - reserved
Timer
00 1
014 Timer 16
[3:2] RW timerpre
108 Timer 256
11 8 Timer
256
16bit/32bit
[1] RW timersize 016bit
132bit

[0] RW oneshot 0
1

3-96 02 (2010-01-19)

Hi3520
3
TIMER1_CONTROL
0x028 TIMER1_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timermode
intenable
timersize
reserved
timerpre
oneshot
timeren
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved

[7] RW timeren 0
1

[6] RW timermode 0
1

[5] RW intenable 0
1
[4] - reserved
Timer
00 1
[3:2] RW timerpre 014 Timer 16
108 Timer 256
11 10
16bit/32bit
[1] RW timersize 016bit
132bit

[0] RW oneshot 0
1

02 (2010-01-19) 3-97

Hi3520
3
3.7.6.4 TIMERx_INTCLR
TIMERx_INTCLR
Timer07 1
Timer

TIMER0_INTCLR
0x00C TIMER0_INTCLR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer0_intclr
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[31:0] WO timer0_intclr Timer0
TIMER1_INTCLR
0x02C TIMER1_INTCLR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timerx1_intclr
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[31:0] WO timer1_intclr Timer1
3.7.6.5 TIMERx_RIS
TIMERx_RIS Timer07 1

3-98 02 (2010-01-19)

Hi3520
3
TIMER0_RIS
0x010 TIMER0_RIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timer0ris
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved 0
Timer0
[0] RO timer0ris 0
1
TIMER1_RIS
0x030 TIMER1_RIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timer1ris
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved 0
Timer1
[0] RO timer1ris 0
1
3.7.6.6 TIMERx_MIS
TIMERx_MIS Timer07 1

02 (2010-01-19) 3-99

Hi3520
3
TIMER0_MIS
0x014 TIMER0_MIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timer0mis
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Timer0
[0] RO timer0mis 0
1
TIMER1_MIS
0x034 TIMER1_MIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timer1mis
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Timer1
[0] RO timer1mis 0
1
3.7.6.7 TIMERx_BGLOAD
TIMERx_BGLOAD Timer07 1

TIMERx_BGLOAD
0

3-100 02 (2010-01-19)

Hi3520
3
TIMERx_LOAD
TIMERx_BGLOAD
TIMER0_BGLOAD
0x018 TIMER0_BGLOAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer0bgload
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Timer0
[31:0] RW timer0bgload TIMERX_LOAD
TIMERx_LOAD
TIMER1_BGLOAD
0x038 TIMER1_BGLOAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name timer1bgload
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Timer1
[31:0] RW timer1bgload TIMERX_LOAD
TIMERx_LOAD
3.8
3.8.1
WatchDog
3.8.2
WatchDog

02 (2010-01-19) 3-101

Hi3520
3
z 32bit
z
z
z
z
z
3.8.3
3-31 WatchDog
WDG_RST O WatchDog WDGRST

WDGRST ODOpen-Drain
3.8.4
WatchDog 3-25
3-25 WatchDog
3MHz WDG_RST
0 clk
APB WatchDog
1
SC_CTRL[wdogenov]

3-102 02 (2010-01-19)

Hi3520
3
WatchDog 1 32bit WDG_LOAD

WatchDog 1
0WatchDog
WDG_LOAD
0 CPU WatchDog WatchDog

WDG_RST
WDG_CONTROL WatchDog

z
z WatchDog WDG_LOAD

WatchDog 3MHz APB

WDG_LOCK WatchDog
z WDG_LOCK 0x1ACC_E551 WatchDog
z WDG_LOCK WatchDog
WDG_LOCK
WatchDog
WatchDog
WatchDog
SLEEP WatchDog3.8.5
WatchDog
debug WatchDog debug

3.8.5
2 WatchDog 3MHz APB

SC_CTRL[wdogenov]
WatchDog
TWDG = Value WDG_LOAD (1 f clk )

02 (2010-01-19) 3-103

Hi3520
3
TWDG WatchDog Value WDG_LOAD WatchDog f clk

WatchDog
WatchDog
z 3MHz 3MHz 01432s
z APB 100MHz 043s
WatchDog
WatchDog WatchDog
1 WDG_LOAD
2 WDG_CONTROL WatchDog
3 WDG_LOCK WatchDog WatchDog
----
WatchDog
WatchDog
1 WDG_LOCK 0x1ACC_E551 WatchDog
2 WDG_INTCLR WatchDog WatchDog

3 WDG_LOCK 0x1ACC_E551 WatchDog
----
WatchDog
SLEEP WatchDog WDG_CONTROL[inten]
0 WatchDog 1 WatchDog
3.8.6
3-32 WatchDog 0x2004_0000
0x000 WDG_LOAD 3-105
0x004 WDG_VALUE 3-105
0x008 WDG_CONTROL 3-106

3-104 02 (2010-01-19)

Hi3520
3
0x00C WDG_INTCLR 3-106
0x010 WDG_RIS 3-107
0x014 WDG_MIS 3-107
0x018 RESERVED -
0xBFC
0xC00 WDG_LOCK LOCK 3-108
3.8.7
WDG_LOAD
WatchDog

0x000 WDG_LOAD 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdg_load
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:0] RW wdg_load
WDG_VALUE
WatchDog

0x004 WDG_VALUE 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdogvalue
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:0] RO wdogvalue WatchDog

02 (2010-01-19) 3-105

Hi3520
3
WDG_CONTROL
WatchDog /

0x008 WDG_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
resen
inten
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
WatchDog
[1] RW resen 0
1
WatchDog
0WatchDog

[0] RW inten
1WatchDog
inten
WDG_LOAD
WDG_INTCLR
WatchDog WatchDog
WatchDog


0x00C WDG_INTCLR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdg_intclr
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
WatchDog
[31:0] WO wdg_intclr
WatchDog WDG_LOAD

3-106 02 (2010-01-19)

Hi3520
3
WDG_RIS
WatchDog

0x010 WDG_RIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wdogris
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
WatchDog 0
1
[0] RO wdogris
0
1
WDG_MIS
WatchDog

02 (2010-01-19) 3-107

Hi3520
3

0x014 WDG_MIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wdogmis
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
[0] RO wdogmis WatchDog

0
1
WDG_LOCK
LOCK WatchDog

0xC00 WDG_LOCK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdg_lock
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1ACC_E551

[31:0] RW wdg_lock
0x0000_0000
0x0000_0001
3.9
3.9.1
RTCReal Time Clock

3-108 02 (2010-01-19)

Hi3520
3
3.9.2
RTC
z 1 32bit
z 1Hz
z
z
z
z
3.9.3
RTC 1 32bit RTC_LR
1 RTC_LR RTC_MR
RTC

RTC 10
RTC_IMSC RTC

z RTC
RTC_MIS RTC_RIS
z RTC RTC_LR
RTC_MR RTC
RTC 1Hz

3.9.4
RTC 1Hz
TRTC = (2 32 1) (1 f rtcclk ) = 4294967295() 49710()
TRTC RTC 2 32 - 1 RTC f rtcclk RTC

1Hz
SC_PERCTRL8[rtc_srst] RTC
RTC

02 (2010-01-19) 3-109

Hi3520
3
1 SC_PERCTRL8[rtc_srst] 1 RTC
2 SC_PERCTRL8[rtc_srst] 0 RTC
----
RTC RTC
RTC
1 RTC_CR[rtc_start]=0b1 RTC
2 RTC_IMSC[rtc_imsc]=0b0 RTC
3 RTC_MR RTC
4 RTC_LR RTC
5 RTC 1Hz RTC_LR RTC_MR

RTC_IMSC
----
RTC
RTC RTC
1 RTC_ICR[rtc_icr]=0b1 RTC
2 RTC_MR
----
RTC
RTC_CR RTC RTC RTC
RTC RTC 0
3.9.5
3-33 RTC 0x2006_0000
0x000 RTC_DR 3-111
0x004 RTC_MR RTC 3-111
0x008 RTC_LR RTC 3-112

3-110 02 (2010-01-19)

Hi3520
3
0x00C RTC_CR RTC 3-112
0x010 RTC_IMSC 3-112
0x014 RTC_RIS 3-113
0x018 RTC_MIS 3-113
0x01C RTC_ICR 3-114
3.9.6
RTC_DR
RTC_DR RTC

0x000 RTC_DR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rtc_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO rtc_data RTC
RTC_MR
RTC_MR RTC RTC

0x004 RTC_MR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rtc_match
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW rtc_match RTC

02 (2010-01-19) 3-111

Hi3520
3
RTC_LR
RTC_LR RTC RTC

0x008 RTC_LR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rtc_load
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW rtc_load RTC
RTC_CR
RTC_CR RTC


0x00C RTC_CR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rtc_start
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
RTC
[0] RW rtc_start 0
1
RTC_IMSC
RTC_IMSC RTC

3-112 02 (2010-01-19)

Hi3520
3

0x010 RTC_IMSC 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rtc_imsc
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
RTC
[0] RW rtc_imsc 0
1
RTC_RIS
RTC_RIS RTC

0x014 RTC_RIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rtc_ris
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
RTC
[0] RO rtc_ris 0
1
RTC_MIS
RTC_MIS RTC RTC

02 (2010-01-19) 3-113

Hi3520
3

0x018 RTC_MIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rtc_mis
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
RTC
[0] RO rtc_mis 0
1
RTC_ICR
RTC_ICR RTC RTC

0x01C RTC_ICR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rtc_icr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
RTC
[0] WO rtc_icr 0
1

3-114 02 (2010-01-19)

Hi3520
3
3.10
3.10.1

3.10.2

z
z
z
z
z
z
z
z
z
3.10.3
4
z NORMAL
NORMAL ARMPLL

z SLOW
SLOW
TimerSMI
DDRCUSB 2.0 HOST CRG AMBA-PCI
SIO0SIO1SIO2MMC
z DOZE
DOZE 46.8kHz
CPU
Timer
z SLEEP
SLEEP CPU
IR 46.8kHz
AMBA-PCI AHB

02 (2010-01-19) 3-115

Hi3520
3
SC_CTRL[modectrl]

z 000 SLEEP
z 001 DOZE
z 01X SLOW
z 1XX NORMAL
X 0 1

SC_CTRL[modestatus]
4 NORMALSLOWDOZESLEEP 4
SW from PLLSW to PLLPLLCTLSW from XTALSW to XTAL
XTALCTL
NORMALSLOWDOZESLEEP 4
NORMAL SC_CTRL[modectrl]001 DOZE
SW from PLLSLOWSW from XTAL
SLOW
VIC
SC_CTRL[modectrl]
3-34
3-34
24MHz PLL

NORMAL ARM PLL

SLOW ARM 24MHz

DOZE ARM
46.8kHz
SLEEP
46.8kHz

3-116 02 (2010-01-19)

Hi3520
3
3-26
3-26
NORMAL
Clock Switch Done

NORMAL
SW to PLL
PLLTIMEOUT
SW from PLL
PLLCTL Clock Switch Done

Power On Reset
NORMAL
SLOW
Clock Switch Done

SLOW& NORMAL
SW to XTAL
SW from
XTALTIMEOUT XTAL
XTALCTL Clock Switch Done
SLOW| NORMAL
DOZE
DOZE &
IRQ|FIQ SLOW &
NORMAL&
STANDBYWFI
SLEEP

z SLEEP
SLEEP IR 46.8kHz
FIQ IRQ
DOZE SC_CTRL[modectrl] SLEEP DOZE
SLEEP DOZE SLEEP

IRQ FIQ GPIO
DOZE GPIO
z DOZE

02 (2010-01-19) 3-117

Hi3520
3
DOZE 46.8kHz

SC_CTRL[modectrl] SLOW NORMAL
SC_XTALCTL 24MHz
SW to XTAL 46.8kHz 24MHz
SLOW
SC_CTRL[modectrl] SLEEP ARM926EJ-S Wait-for-
interrupt SLEEP
z SC_XTALCTRL bit[18:3] 24MHz

z ARM1176 CP15(Wait-for-interrupt)

z SLOW
SLOW ARM 24MHz
SC_CTRL[modectrl] NORMAL PLL
SC_PLLCTL PLL PLL SW to PLL
PLL NORMAL
SC_PLLCTRL bit[27:3] PLL PLL

SC_PLLCTRL23 bit[0] PLL
SC_CTRL[modectrl] SLOW DOZE SLEEP
SW from XTAL 46.8kHz
DOZE
z NORMAL
NORMAL ARM PLL
SC_CTRL[modectrl] NORMAL SW from PLL
24MHz SLOW
PLL
PLL PLL 3-
34
PLL
4 PLL PLL
SC_PERCTRL0SC_PERCTRL1SC_PERCTRL2SC_PERCTRL3
SC_PERCTRL4SC_PERCTRL5SC_PERCTRL6 SC_PERCTRL7

3-118 02 (2010-01-19)

Hi3520
3
z
z FIQ IRQ
z
DOZE NORMAL
NORMAL SLOW

z SC_SYSSTAT

z

UART0
SC_PERCTRL8[uart0_srst] 1 0
z SC_SYSSTAT

z SC_PERCTRL8 SC_PERCTRL10

boot 0
Hi3520 3 boot
z NOR Flash
z NAND Flash
z DDR
EBIADR23 EBIADR24 3-17

3-35
EBIADR23 EBIADR24 Boot
NOR Flash
DDR
NAND Flash
DDR

02 (2010-01-19) 3-119

Hi3520
3
0 SMINAND Flash MDDRC

0x0000_00000x0000_0FFF CPU 2KB ITCM
WatchDog Timer

z WatchDog Timer

z WatchDog Timer
Debug WatchDog
z Timer
128bits interconnect interconnect

interconnect timeout

z SC_CTRL
z SC_SYSSTAT
z ARMPLL SC_PERCTRL0SC_PERCTRL1
SC_PERLOCK
SC_PERLOCK

SC_PERLOCK
ID SC_SYSID
32bit 4 8bit SC_SYSID3
SC_SYSID2SC_SYSID1SC_SYSID0 4
32bit 0x3520_0100 3-27

3-120 02 (2010-01-19)

Hi3520
3
3-27 ID
31 24 23 16 15 8 7 0
7 07 07 07 0
SC_SYSID3 SC_SYSID2 SC_SYSID1 SC_SYSID0
3.10.4
3-36
3-36 0x2005_0000
0x0000 SC_CTRL 3-122
0x0004 SC_SYSSTAT 3-125
0x0008 SC_IMCTRL 3-126
0x000C SC_IMSTAT 3-127
0x0010 SC_XTALCTRL 3-128
0x0014 SC_PLLCTRL PLL 3-128
0x001C SC_PERCTRL0 ARM PLL 1 3-129
0x0020 SC_PERCTRL1 ARM PLL 2 3-130
0x0024 SC_PEREN 3-131
0x0028 SC_PERDIS 3-134
0x002C SC_PERCLKEN 3-138
0x0034 SC_PERCTRL2 VIDEO PLL0 1 3-141
0x003C SC_PERCTRL4 VIDEO PLL1 1 3-142
0x0044 SC_PERLOCK 3-144
0x0048 SC_PERCTRL6 GMAC PLL 1 3-145
0x004C SC_PERCTRL7 GMAC PLL 2 3-146
0x0050 SC_PERCTRL8 1 3-147

02 (2010-01-19) 3-121

Hi3520
3
0x0054 SC_PERCTRL9 1 3-150
0x0058 SC_PERCTRL10 2 3-152
0x005C SC_PERCTRL11 1 3-153
0x0060 SC_PERCTRL12 2 3-155
0x0064 SC_PERCTRL13 2 3-158
0x0068 SC_PERCTRL14 3 3-159
0x0070 SC_PERCTRL16 4 3-160
0x0074 SC_PERCTRL17 ARM926EJ-S 3-162
0x0078 SC_PERCTRL18 1 3-162
0x007C SC_PERCTRL19 2 3-163
0x0088 SC_PERCTRL22 5 3-163
0x008C SC_PERCTRL23 PLL 3-164
0xEE0 SC_SYSID0 ID 0 3-166
0xEEC SC_SYSID3 ID 3 3-167
3.10.5
SC_CTRL
SC_CTRL
SC_PERLOCK

3-122 02 (2010-01-19)

Hi3520
3

0x0000 SC_CTRL 0x0000_0212
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
timeren7sel
timeren6sel
timeren5sel
timeren4sel
timeren3sel
timeren2sel
timeren1sel
timeren0sel
timeren7ov
timeren6ov
timeren5ov
timeren4ov
timeren3ov
timeren2ov
timeren1ov
timeren0ov
remapclear
wdogenov
remapstat
modectrl
reserved
Name reserved modestatus
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
Timer7
0
[31] RW timeren7ov
timeren7sel
1
Timer7 0
[30] RW timeren7sel 0 3MHz
1
Timer6
0
[29] RW timeren6ov
timeren6sel
1
Timer6 0
1
Timer5
0
[27] RW timeren5ov
timeren5sel
1
Timer5 0
1
Timer4
0
[25] RW timeren4ov
timeren4sel
1

02 (2010-01-19) 3-123

Hi3520
3
Timer4 0
1
WDG
[23] RW wdogenov 0WDG 3MHz
1WDG
Timer3
0
[22] RW timeren3ov
timeren3sel
1
Timer3 0
1
Timer2
0
[20] RW timeren2ov
timeren2sel
1
Timer2 0
1
Timer1
0
[18] RW timeren1ov
timeren1sel
1
Timer1 0
1
Timer0
0
[16] RW timeren0ov
timeren0sel
1
Timer0 0
1
[14:10] - reserved 0

3-124 02 (2010-01-19)

Hi3520
3

0
[9] RO remapstat 1EBICS0N
Remap 0DDRCSN
Remap 0

0 Remap
[8] RW remapclear 1 Remap
Clear Remap 3.3 3.3

[7] - reserved 0

4
0x0SLEEP
0x1DOZE
0x2SLOW
0x3XTAL CTL
[6:3] RW modestatus 0x4NORMAL
0x6PLL CTL
0x9SW from XTAL
0xASW from PLL
0xBSW to XTAL
0xESW to PLL

3
000SLEEP
[2:0] RW modectrl
001DOZE
01XSLOW
1XXNORMAL
SC_SYSSTAT
SC_SYSSTAT

02 (2010-01-19) 3-125

Hi3520
3
SC_PERLOCK


0x0004 SC_SYSSTAT 0x0000_0002
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name softresreq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
[31:0] WO softresreq
SC_IMCTRL
SC_IMCTRL

0x0008 SC_IMCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
inmdtype
reserved
itmdctrl
itmden
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved 0

[7] RW inmdtype 0 FIQ
1FIQ IRQ
[6:4] - reserved

3-126 02 (2010-01-19)

Hi3520
3

SC_CTRL[modectrl]

[3:1] RW itmdctrl 000SLEEP

001DOZE
01XSLOW
1XXNORMAL

[0] RW itmden 0
1
SC_IMSTAT
SC_IMSTAT


0x000C SC_IMSTAT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
itmdstat
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved 0

02 (2010-01-19) 3-127

Hi3520
3

0
[0] RW itmdstat 1

0
1
SC_XTALCTRL
SC_XTALCTRL
XTAL CTL SW to XTAL

0x0010 SC_XTALCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name reserved xtaltime
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

XTAL CTL
[18:3] RW xtaltime SW to XTAL
T46.8K 46.8KHz 65536
xtaltimeT46.8K
[2] - reserved 0
[1:0] - reserved
SC_PLLCTRL
SC_PLLCTRL PLL ARM ARMPLL

ARMPLL

3-128 02 (2010-01-19)

Hi3520
3
SC_PERLOCK

ARMPLL
NORMAL ARMPLL
ARMPLL SC_PERCTRL0/SC_PERCTRL1
PLL 0.5ms
plltime

0x0014 SC_PLLCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
pllover
Name reserved plltime
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ARMPLL
PLL PLL
[27:3] RW plltime PLL CTL SW to
PLL TXIN
33554432-plltimeTXIN
[2] - reserved 0
[1] - reserved
0
[0] RW pllover
ARMPLL
SC_PERCTRL0
SC_PERCTRL0 ARM PLL 1

02 (2010-01-19) 3-129

Hi3520
3

0x001C SC_PERCTRL0 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
apll_postdiv2 8 7 6 5 4 3 2 1 0
apll_postdiv1
apll_bypass
apll_dsmpd
Name apll_frac
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
APLL
[31] RW apll_dsmpd 0
1
APLL bypass
[30] RW apll_bypass 0
1
[29:27] RW apll_postdiv2 APLL
[26:24] RW apll_postdiv1 APLL
[23:0] RW apll_frac APLL
SC_PERCTRL1
SC_PERCTRL1 ARM PLL 2

0x0020 SC_PERCTRL1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
apll_fout4phasepd
apll_foutvcopd
apll_postdivpd
apll_reset
apll_pd
Name reserved apll_refdiv apll_fbdiv
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:23] - reserved

3-130 02 (2010-01-19)

Hi3520
3
APLL
[22] RW apll_reset 0
1
APLL Power Down

[21] RW apll_pd 0
1
APLL VCO Power Down

[20] RW apll_foutvcopd 0
1
APLL POSTDIV Power Down

[19] RW apll_postdivpd 0
1
APLL FOUT Power Down

[18] RW apll_fout4phasepd 0
1
[17:12] RW apll_refdiv APLL
[11:0] RW apll_fbdiv APLL
SC_PEREN
SC_PEREN
1 0


0x0024 SC_PEREN 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cipherclken
vdac1clken
vdac0clken
nandcclken
vobusclken
vibusclken
arm9clken
uart3clken
uart2clken
uart1clken
uart0clken
vohdclken
mmcclken
ipcmclken
voadclken
vosdclken
sio2clken
sio1clken
sio0clken
smiclken
usbclken
sspclken
vi3clken
vi2clken
vi1clken
vi0clken
tdeclken
ethclken
pciclken
reserved
irclken
Name
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VIDEO DAC1
[31] WO vdac1clken 0
1

02 (2010-01-19) 3-131

Hi3520
3
VIDEO DAC0
[30] WO vdac0clken 0
1
SSP
[29] WO sspclken 0
1
ARM926
[28] WO arm9clken 0
1
NANDC
[27] WO nandcclken 0
1
VO AD
[26] WO voadclken 0
1
VO HD
[25] WO vohdclken 0
1
VO SD
[24] WO vosdclken 0
1
VO
[23] WO vobusclken 0
1
USB
[22] WO usbclken 0
1
GMAC
[21] WO ethclken 0
1
VI3
[20] WO vi3clken 0
1

3-132 02 (2010-01-19)

Hi3520
3
VI2
[19] WO vi2clken 0
1
VI1
[18] WO vi1clken 0
1
VI0
[17] WO vi0clken 0
1
VI
[16] WO vibusclken 0
1
TDE
[15] WO tdeclken 0
1
MMC
[14] WO mmcclken 0
1
PCI
[13] WO pciclken 0
1
IPCM
[12] WO ipcmclken 0
1
IR
[11] WO irclken 0
1
SIO2
[10] WO sio2clken 0
1
SIO1
[9] WO sio1clken 0
1

02 (2010-01-19) 3-133

Hi3520
3
SIO0
[8] WO sio0clken 0
1
UART3
[7] WO uart3clken 0
1
UART2
[6] WO uart2clken 0
1
UART1
[5] WO uart1clken 0
1
UART0
[4] WO uart0clken 0
1
SMI
[3] WO smiclken 0
1
CIPHER
[2] WO cipherclken 0
1
[1:0] - reserved
SC_PERDIS
SC_PERDIS
1 0

SC_PEREN SC_PERDIS
SMI SC_PERDIS
0x0000_0004 SMI SMI
SC_PEREN 0x0000_0001
SC_PERCLKEN SMI
SC_PERCLKEN[3] 1

3-134 02 (2010-01-19)

Hi3520
3

0x0028 SC_PERDIS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cipherclkdis
vdac1clkdis
vdac0clkdis
nandcclkdis
vobusclkdis
vibusclkdis
arm9clkdis
uart3clkdis
uart2clkdis
uart1clkdis
uart0clkdis
ipcmclkdis
vohdclkdis
mmcclkdis
voadclkdis
vosdclkdis
sio2clkdis
sio1clkdis
sio0clkdis
smiclkdis
usbclkdis
sspclkdis
vi3clkdis
vi2clkdis
vi1clkdis
vi0clkdis
ethclkdis
tdeclkdis
pciclkdis
reserved
irclkdis
Name
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VIDEO DAC1
[31] WO vdac1clkdis 0
1
VIDEO DAC0
[30] WO vdac0clkdis 0
1
SSP
[29] WO sspclkdis 0
1
ARM926
[28] WO arm9clkdis 0
1
NANDC
[27] WO nandcclkdis 0
1
VO AD
[26] WO voadclkdis 0
1
VO HD
[25] WO vohdclkdis 0
1
VO SD
[24] WO vosdclkdis 0
1

02 (2010-01-19) 3-135

Hi3520
3
VO
[23] WO vobusclkdis 0
1
USB
[22] WO usbclkdis 0
1
GMAC
[21] WO ethclkdis 0
1
VI3
[20] WO vi3clkdis 0
1
VI2
[19] WO vi2clkdis 0
1
VI1
[18] WO vi1clkdis 0
1
VI0
[17] WO vi0clkdis 0
1
VI
[16] WO vibusclkdis 0
1
TDE
[15] WO tdeclkdis 0
1
MMC
[14] WO mmcclkdis 0
1
PCI
[13] WO pciclkdis 0
1

3-136 02 (2010-01-19)

Hi3520
3
IPCM
[12] WO ipcmclkdis 0
1
IR
[11] WO irclkdis 0
1
SIO2
[10] WO sio2clkdis 0
1
SIO1
[9] WO sio1clkdis 0
1
SIO0
[8] WO sio0clkdis 0
1
UART3
[7] WO uart3clkdis 0
1
UART2
1
UART1
1
UART0
1
SMI
[3] WO smiclkdis 0
1
CIPHER
[2] WO cipherclkdis 0
1
[1:0] - reserved

02 (2010-01-19) 3-137

Hi3520
3
SC_PERCLKEN
SC_PERCLKEN
SC_PEREN SC_PERDIS
0 1

0x002C SC_PERCLKEN 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cipherclkstat
vdac1clkstat
vdac0clkstat
nandcclkstat
vobusclkstat
vibusclkstat
arm9clkstat
uart3clkstat
uart2clkstat
uart1clkstat
uart0clkstat
ipcmclkstat
vohdclkstat
mmcclkstat
voadclkstat
vosdclkstat
sio2clkstat
sio1clkstat
sio0clkstat
smiclkstat
usbclkstat
sspclkstat
vi3clkstat
vi2clkstat
vi1clkstat
vi0clkstat
tdeclkstat
pciclkstat
ethclkstat
reserved
irclkstat
Name
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VIDEO DAC1
[31] RO vdac1clkstat 0
1
VIDEO DAC0
[30] RO vdac0clkstat 0
1
SSP
[29] RO sspclkstat 0
1
ARM926
[28] RO arm9clkstat 0
1
NANDC
[27] RO nandcclkstat 0
1
VO AD
[26] RO voadclkstat 0
1

3-138 02 (2010-01-19)

Hi3520
3
VO HD
[25] RO vohdclkstat 0
1
VO SD
[24] RO vosdclkstat 0
1
VO
[23] RO vobusclkstat 0
1
USB
[22] RO usbclkstat 0
1
GMAC
[21] RO ethclkstat 0
1
VI3
[20] RO vi3clkstat 0
1
VI2
1
VI1
1
VI0
1
VI
[16] RO vibusclkstat 0
1
TDE
[15] RO tdeclkstat 0
1

02 (2010-01-19) 3-139

Hi3520
3
MMC
[14] RO mmcclkstat 0
1
PCI
[13] RO pciclkstat 0
1
IPCM
[12] RO ipcmclkstat 0
1
IR
[11] RO irclkstat 0
1
SIO2
[10] RO sio2clkstat 0
1
SIO1
1
SIO0
1
UART3
[7] RO uart3clkstat 0
1
UART2
1
UART1
1
UART0
1

3-140 02 (2010-01-19)

Hi3520
3
SMI
[3] RO smiclkstat 0
1
CIPHER
[2] RO cipherclkstat 0
1
[1:0] - reserved
SC_PERCTRL2
SC_PERCTRL2 VIDEO PLL0 1

0x0034 SC_PERCTRL2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vpll0_postdiv2
vpll0_postdiv1
vpll0_bypass
vpll0_dsmpd
Name vpll0_frac
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VPLL0
[31] RW vpll0_dsmpd 0
1
VPLL0 bypass
[30] RW vpll0_bypass 0no bypass
1bypass
[29:27] RW vpll0_postdiv2 VPLL0
[23:0] RW vpll0_frac VPLL0
SC_PERCTRL3

02 (2010-01-19) 3-141

Hi3520
3

0x0038 SC_PERCTRL3 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vpll0_fout4phasepd
vpll0_foutvcopd
vpll0_postdivpd
vpll0_reset
vpll0_pd
Name reserved vpll0_refdiv vpll0_fbdiv
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:23] - reserved
VPLL0
[22] RW vpll0_reset 0
1
VPLL0 Power Down

[21] RW vpll0_pd 0
1
VPLL0 VCO Power Down

[20] RW vpll0_foutvcopd 0
1
VPLL0 POSTDIV Power Down

[19] RW vpll0_postdivpd 0
1
VPLL0 FOUT Power Down

[18] RW vpll0_fout4phasepd 0
1
[17:12] RW vpll0_refdiv VPLL0
[11:0] RW vpll0_fbdiv VPLL0
SC_PERCTRL4

3-142 02 (2010-01-19)

Hi3520
3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
vpll1_postdiv2 8 7 6 5 4 3 2 1 0
vpll1_postdiv1
vpll1_bypass
vpll1_dsmpd
Name vpll1_frac
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VPLL1
[31] RW vpll1_dsmpd 0
1
VPLL1 bypass
[30] RW vpll1_bypass 0no bypass
1bypass
[23:0] RW vpll1_frac VPLL1
SC_PERCTRL5

0x0040 SC_PERCTRL5 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vpll1_fout4phasepd
vpll1_foutvcopd
vpll1_postdivpd
vpll1_reset
vpll1_pd
Name reserved vpll1_refdiv vpll1_fbdiv
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:23] - reserved

02 (2010-01-19) 3-143

Hi3520
3
VPLL1
[22] RW vpll1_reset 0
1
VPLL1 Power Down

[21] RW vpll1_pd 0
1
VPLL1 VCO Power Down

[20] RW vpll1_foutvcopd 0
1
VPLL1 POSTDIV Power Down

[19] RW vpll1_postdivpd 0
1
VPLL1 FOUT Power Down

[18] RW vpll1_fout4phasepd 0
1
[17:12] RW vpll1_refdiv VPLL1
[11:0] RW vpll1_fbdiv VPLL1
SC_PERLOCK
SC_PERLOCK

3-144 02 (2010-01-19)

Hi3520
3

0x0044 SC_PERLOCK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name scper_lockl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SC_CTRLSC_SYSSTATSC_PLLCTRL
SC_PERCTRL0SC_PERCTRL1
0x1ACC_E551
[31:0] RW scper_lockl

0x0000_0000
0x0000_0001
SC_PERCTRL6
SC_PERCTRL6 GMAC PLL 1

0x0048 SC_PERCTRL6 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
epll_postdiv2
epll_postdiv1
epll_bypass
epll_dsmpd
Name epll_frac
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPLL
[31] RW epll_dsmpd 0
1
EPLL bypass
[30] RW epll_bypass 0no bypass
1bypass
[29:27] RW epll_postdiv2 EPLL
[26:24] RW epll_postdiv1 EPLL

02 (2010-01-19) 3-145

Hi3520
3
[23:0] RW epll_frac EPLL
SC_PERCTRL7
SC_PERCTRL7 GMAC PLL 2

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
epll_fout4phasepd
epll_foutvcopd
epll_postdivpd
epll_reset
epll_pd
Name reserved epll_refdiv epll_fbdiv
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:23] - reserved
EPLL
[22] RW epll_reset 0
1
EPLL Power Down

[21] RW epll_pd 0
1
EPLL VCO Power Down

[20] RW epll_foutvcopd 0
1
EPLL POSTDIV Power Down

[19] RW epll_postdivpd 0
1
EPLL FOUT Power Down

[18] RW epll_fout4phasepd 0
1
[17:12] RW epll_refdiv EPLL
[11:0] RW epll_fbdiv EPLL

3-146 02 (2010-01-19)

Hi3520
3
SC_PERCTRL8
SC_PERCTRL8 1

0x0050 SC_PERCTRL8 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
arm11_srst
cipher_srst
gmac_srst
mdio_srst
uart3_srst
uart2_srst
uart1_srst
uart0_srst
arm9_srst
mmc_srst
vohd_srst
ssmc_srst
voad_srst
vosd_srst
sio2_srst
sio1_srst
sio0_srst
usb_hrst
reserved
usb_srst
vi3_srst
vi2_srst
vi1_srst
vi0_srst
eth_srst
pci_srst
i2c_srst
rtc_srst
vo_srst
vi_srst
ir_srst
Name
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
USB
[31] RW usb_srst 0
1
USB
[30] RW usb_hrst 0
1
VO HD
[29] RW vohd_srst 0
1
VO SD
[28] RW vosd_srst 0
1
VO AD
[27] RW voad_srst 0
1
VO
[26] RW vo_srst 0
1
VI3
[25] RW vi3_srst 0
1
VI2
[24] RW vi2_srst 0
1

02 (2010-01-19) 3-147

Hi3520
3
VI1
[23] RW vi1_srst 0
1
VI0
[22] RW vi0_srst 0
1
VI
[21] RW vi_srst 0
1
GMAC
[20] RW gmac_srst 0
1
GMAC MDIO
[19] RW mdio_srst 0
1
GMAC
[18] RW eth_srst 0
1
SIO2
[17] RW sio2_srst 0
1
SIO1
[16] RW sio1_srst 0
1
SIO0
[15] RW sio0_srst 0
1
MMC
[14] RW mmc_srst 0
1
PCI
[13] RW pci_srst 0
1

3-148 02 (2010-01-19)

Hi3520
3
I2C
[12] RW i2c_srst 0
1
RTC
[11] RW rtc_srst 0
1
IR
[10] RW ir_srst 0
1
UART3
[9] RW uart3_srst 0
1
UART2
[8] RW uart2_srst 0
1
UART1
[7] RW uart1_srst 0
1
UART0
[6] RW uart0_srst 0
1
CIPHER
[5] RW cipher_srst 0
1
SSMC
[4] RW ssmc_srst 0
1
[3:2] - reserved
ARM926
[1] RW arm9_srst 0
1
ARM1176
[0] RW arm11_srst 0
1

02 (2010-01-19) 3-149

Hi3520
3
SC_PERCTRL9
SC_PERCTRL9 1

0x0054 SC_PERCTRL9 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ethmac_mode
arm1freq_sel
arm0freq_sel
mmcsap_sel
mmcclk_sel
ssmcclk_sel
vi3_vi2_sel
vi1_vi0_sel
aclkout_sel
vo1out_sel
vo0out_sel
ethtclk_sel
vi3div_sel
vi2div_sel
vi1div_sel
vi0div_sel
pciclk_sel
vohd_sel
vosd_sel
reserved
Name
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
txclk
[29] RW ethtclk_sel 0txclk PHY
1txclk PHY
GMAC
000MII 10M
001MII 100M
010GMII
[28:26] RW ethmac_mode
011RGMII 10M
100RGMII 100M
101RGMII 1000M

ACKOUT
[25] RW aclkout_sel 0 SIO0
1 SIO1
PCI
0062.5MHz
[24:23] RW pciclk_sel 0131.25MHz
1050MHz
1141.5MHz

3-150 02 (2010-01-19)

Hi3520
3
MMC
[22] RW mmcsap_sel 0
1
MMC
0025MHz
[21:20] RW mmcclk_sel 0150MHz
10
1119.23MHz
VO1
[19] RW vo1out_sel 0VO1
1VO1
VO0
[18] RW vo0out_sel 0VO0
1VO0
VO_HD DATE VO
00DATE : VO 1:1
[17:16] RW vohd_sel 01DATE : VO 2:1
10DATE : VO 4:1
11
VO_SD/AD DATE VO
00DATE : VO 1:1
[15:14] RW vosd_sel 01DATE : VO 2:1
10DATE : VO 4:1
11
VI3
00VI3 2
[13:12] RW vi3div_sel 01VI3 4
10VI3
11
VI2
00VI2 2
10VI2
11

02 (2010-01-19) 3-151

Hi3520
3
VI1
00VI1 2
10VI1
11
VI0
00VI0 2
10VI0
11
VI3
[5] RW vi3_vi2_sel 0VI3
1VI2
VI1
[4] RW vi1_vi0_sel 0VI1
1VI0
SSMC
[3] RW ssmcclk_sel 0SSMC:HCLK=1:1
1SSMC:HCLK=1:2
ARM926
[2] RW arm1freq_sel 0ARM9:HCLK=2:1
1ARM9:HCLK=1:1
ARM1176
00ARM11:HCLK=2:1
[1:0] RW arm0freq_sel 01ARM11:HCLK=3:1
10ARM11:HCLK=1:1
11ARM11:HCLK=1:1
SC_PERCTRL10
SC_PERCTRL10 2

3-152 02 (2010-01-19)

Hi3520
3

0x0058 SC_PERCTRL10 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ddrphy_srst
ipcm_srst
nadc_srst
dma_srst
tde_srst
spi_srst
tde_rst
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:7] - reserved
DMA
[6] RW dma_srst 0
1
DDRPHY
[5] RW ddrphy_srst 0
1
SPI
[4] RW spi_srst 0
1
IPCM
[3] RW ipcm_srst 0
1
NANDC
[2] RW nadc_srst 0
1
TDE
[1] RW tde_rst 0
1
TDE
[0] RW tde_srst 0
1
SC_PERCTRL11
SC_PERCTRL11 1

02 (2010-01-19) 3-153

Hi3520
3

0x005C SC_PERCTRL11 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ebi_mormal_mode
i2c_delay_bypass
smi_canclewait
uart1_rtsmode
ebi_arb_delay
pci_clkmode
pci_sim_fast
pci_mode
pci_type
spi_port
Name ebinandc_time_out ebismi_time_out
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
UART1 RTS
[31] RW uart1_rtsmode 0
1
SPI
[30] RW spi_port 0SPI_CS0
1SPI_CS1
SMI
[29] RW smi_canclewait 0
1 SMI
NANDC EBI
[28:19] RW ebinandc_time_out
0x020
SMI EBI
[18:9] RW ebismi_time_out
0x020
EBI SMI NANDC

00
[8:7] RW ebi_arb_delay 01 1
10 2
11 3
EBI
[6] RW ebi_mormal_mode 0
1 Idle

3-154 02 (2010-01-19)

Hi3520
3
I2C SDA SCL

[5] RW i2c_delay_bypass 0
1 300ns
[4] RW pci_sim_fast PCI 0x0
PCI 00
[3:2] RW pci_type 00 PCI

PCI
[1] RW pci_clkmode 0
1
PCI
[0] RW pci_mode 0
1
SC_PERCTRL12
SC_PERCTRL12 2

0x0060 SC_PERCTRL12 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dac1_powredown
dac0_powredown
usb_susp_lgcy
usb_start_clk
vou_test_en
sio2_master
sio1_master
sio0_master
ddrck2_dis
ddrck1_dis
ddrck0_dis
ddr_clksel
usb_tune1
usb_tune0
sio1_xck
sio0_xck
sio1_xfs
sio0_xfs
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:20] - reserved
OHCI OHCI
1 OHCI 12MHz 48MHz 12MHz
48MHz suspend
0
[19] RW usb_start_clk
0OHCI suspend 12MHz 48MHz

1OHCI suspend 12MHz 48MHz

02 (2010-01-19) 3-155

Hi3520
3
OHCI strap
0 USB OHCI utmi_suspend_o_n
0 OHCI USB suspend
OHCI global suspend utmi_suspend_o_n
[18] RW usb_susp_lgcy
1 OHCI USB
OHCI global suspend
1 USB OHCI utmi_suspend_o_n
suspend
DDRB CKP0/CKN0
[17] RW ddrck2_dis 0
1
DDRA CKP1/CKN1
1
DDRA CKP0/CKN0
1
DDR
[14] RW ddr_clksel 0
1
USB 1 transmitter high-speed

high-speed
00 4.5%
01
[13:12] RW usb_tune1
10 4.5%
11 9%
PHY POR

USB 0 transmitter high-speed

high-speed
00 4.5%
01
[11:10] RW usb_tune0
10 4.5%
11 9%
PHY POR

3-156 02 (2010-01-19)

Hi3520
3
DAC1
[9] RW dac1_powredown 0
1
DAC0
[8] RW dac0_powredown 0
1

[7] RW vou_test_en 0
1
SIO2
[6] RW sio2_master 0
1
SIO1
0SIO1 SIO1XFS
[5] RW sio1_xfs
1SIO1 SIO1RFS
SIO1XFS
SIO1
0SIO1 SIO1XCK
[4] RW sio1_xck
1SIO1 SIO1RCK
SIO1XCK
SIO1
1
SIO0
0SIO0 SIO0XFS
[2] RW sio0_xfs
1SIO0 SIO0RFS
SIO0XFS
SIO0
0SIO0 SIO0XCK
[1] RW sio0_xck
1SIO0 SIO0RCK
SIO0XCK
SIO0
1

02 (2010-01-19) 3-157

Hi3520
3
SC_PERCTRL13
SC_PERCTRL13 2

0x0064 SC_PERCTRL13 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name sio0_lrclk_sel sio0_bclk_sel sio0clk_sel
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO0 SIO0 248

16324864128256
0x02
0x14
0x28
0x316
[31:28] RW sio0_lrclk_sel
0x432
0x548
0x664
0x7128
0x8256

SIO0 SIO0 123

4681216244864128
0x01
0x13
0x22
0x34
0x46
[27:24] RW sio0_bclk_sel 0x58
0x612
0x716
0x824
0x948
0x1064
0x11128

3-158 02 (2010-01-19)

Hi3520
3
SIO0 EPLL (500MHz)

[23:0] RW sio0clk_sel
Fsio= (sio0clk_selFepll)/2^27
SC_PERCTRL14
SC_PERCTRL14 3

0x0068 SC_PERCTRL14 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name sio1_lrclk_sel sio1_bclk_sel sio12clk_sel
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIO1 SIO1 248

16324864128256
0x02
0x14
0x28
0x316
0x432
0x548
0x664
0x7128
0x8256

02 (2010-01-19) 3-159

Hi3520
3
SIO1 SIO1 123

4681216244864128
0x01
0x13
0x22
0x34
0x46
0x612
0x716
0x824
0x948
0x1064
0x11128

SIO1/SIO2 EPLL (500MHz)

[23:0] RW sio12clk_sel
Fsio=(sio12clk_selFepll)/2^27
SC_PERCTRL16
SC_PERCTRL16 4

0x0070 SC_PERCTRL16 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sio2_blk_edge
sio1_blk_edge
sio0_blk_edge
mddrc1_gate
Name reserved sio2_lrclk_sel sio2_bclk_sel
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MDDRC1
[31] RW mddrc1_gate 0
1
[30:11] - reserved

3-160 02 (2010-01-19)

Hi3520
3
SIO2
[10] RW sio2_blk_edge 0
1
SIO1
1
SIO0
1
SIO2 SIO2 248

16324864128256
0x02
0x14
0x28
0x316
0x432
0x548
0x664
0x7128
0x8256

SIO2 SIO2 123

4681216244864128
0x01
0x13
0x22
0x34
0x46
0x612
0x716
0x824
0x948
0x1064
0x11128

02 (2010-01-19) 3-161

Hi3520
3
SC_PERCTRL17
SC_PERCTRL17 ARM926

0x0074 SC_PERCTRL17 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved arm9_bootaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
ARM926 8 0xC0
[7:0] RW arm9_bootaddr
ARM926 0x00xx_xxxx 0xC0xx_xxxx
SC_PERCTRL18
SC_PERCTRL18 1

0x0078 SC_PERCTRL18 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
count_en_port1
count_en_port0
Name over_value_port1 over_value_port0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI timeout
[31] RW count_en_port1 0
1
VI timeout
[30:16] RW over_value_port1
over_value_port12
VO timeout
1

3-162 02 (2010-01-19)

Hi3520
3
VO timeout
over_value_port02
SC_PERCTRL19
SC_PERCTRL19 2

0x007C SC_PERCTRL19 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
count_en_port3
count_en_port2
Name over_value_port3 over_value_port2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TDE1 timeout
1
TDE1 timeout
over_value_port32
TDE0 timeout
1
TDE0 timeout
over_value_port22
SC_PERCTRL22
SC_PERCTRL22 5

02 (2010-01-19) 3-163

Hi3520
3

0x0088 SC_PERCTRL22 0x0000_A72E
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pri_port3
pri_port2
pri_port1
pri_port0
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
[31:12] - reserved
TDE1
[11:9] RW pri_port3 06

TDE0

VI

VO

SC_PERCTRL23
SC_PERCTRL23 PLL

0x008C SC_PERCTRL23 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
arm0_pmuirq
nf_addr_num
nf_page_size
nf_ecc_type
boot_mode
vpll1_lock
vpll0_lock
debug_sel
epll_lock
apll_lock
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:15] - reserved

3-164 02 (2010-01-19)

Hi3520
3
NAND Flash boot ECC

bit[14] bit[13]{NFECC0, NFECC1}

{NFECC1, NFECC0}
[14:13] RO nf_ecc_type
00
011bit
104bit
118bit
NAND Flash boot

bit[12] bit[11]{NFNUM0, NFNUM1}

{NFNUM1, NFNUM0}
[12:11] RO nf_addr_num
003
014
105
116
NAND Flash boot

bit[10] bit[9]{NFPAGE0, NFPAGE1}

{NFPAGE1, NFPAGE0}
[10:9] RO nf_page_size
00
012KB
104KB
11
ARM debug
00debug ARM1176
[8:7] RO debug_sel 10debug ARM926
11

00 NOR Flash
[6:5] RO boot_mode
10 NAND Flash
X1 DDR
ARM1176 PMU
[4] RO arm0_pmuirq 0
1

02 (2010-01-19) 3-165

Hi3520
3
GMAC PLL
[3] RO epll_lock 0
1
Video1 PLL
[2] RO vpll1_lock 0
1
Video0 PLL
[1] RO vpll0_lock 0
1
ARM PLL
[0] RO apll_lock 0
1
SC_SYSID0
SC_SYSID0 ID 0

0xEE0 SC_SYSID0 0x00
Bit 7 6 5 4 3 2 1 0
Name sysid0
Reset 0 0 0 0 0 0 0 0
[7:0] RO sysid0 0x00
SC_SYSID1
SC_SYSID1 ID 1

3-166 02 (2010-01-19)

Hi3520
3

Bit 7 6 5 4 3 2 1 0
Name sysid1
Reset 0 0 0 0 0 0 0 1
SC_SYSID2
SC_SYSID2 ID 2

Bit 7 6 5 4 3 2 1 0
Name sysid2
Reset 0 0 1 0 0 0 0 0
SC_SYSID3
SC_SYSID3 ID 3

0xEEC SC_SYSID3 0x35
Bit 7 6 5 4 3 2 1 0
Name sysid3
Reset 0 0 1 1 0 1 0 1

02 (2010-01-19) 3-167

Hi3520
3
3.11
3.11.1
Hi3520

z
NORMAL

z

z DDR
DDR
3.11.2
4 3.10.3
3.11.3

z VEDU
z PCI
z MMC
z VIU
z VOU
z TDE
z CIPHER
z GMAC
z SIO
z UART
z SMI
z NANDC
z USB 2.0 HOST
z SSP
z IR
Normal
1 DDR
2 Flash TCMTightly-Coupled Memory

3-168 02 (2010-01-19)

Hi3520
3
3 DDRC_DLL_CONFIG[dll_cali_en] 1 DLLDelay Locked Loop
4 DDRC_CTRL[sr_req] 1
5 DDRC_STATUS[in_sr] 1 6
6 SC_PLLCTRL[27:3] PLL
7 SC_PERCTRL0 SC_PERCTRL1 PLL PLL

PLL DDRC
9 DDRC_STATUS[in_sr] 0
10 DDRC_DLL_CONFIG[dll_cali_en] 0 DLL
11 DDR
----

PCISMI MMC
3.11.4 DDR
DDR DDR
z DDRC_CONFIG[pd_en] DDRC_CONFIG[pd_prd] DDR
DDRC DDR

z DDRC_CTRL[sr_req] 1 DDR
DDR
flash DDR
DDR

02 (2010-01-19) 3-169

Hi3520
4
4.1 DDR
4.1.1
DDRCDDR2 SDRAM Controller DDR2 DDR2 SDRAM
Hi3520 2 DDRC DDRC0DDRC1
4.1.2
DDRC
z 1 DDR2 SDRAM 16bit 32bit DDRC1
16bit
z DDRC 16bit 256MB32bit 512MB
z DDR2 SDRAM burst 4
z
z DDR SDRAM DDR2 SDRAM AUTO RefreshSELF Refresh
z
z DDR2 SDRAM 400MHz
4.1.3
DDRC 4-1
4-1 DDRC
DDRA_CKP0 O 0 DDRA_CKP0
/DDRB_CKP0 /DDRB_CKP0
DDRA_CKN0 O 0 DDRA_CKN0
/DDRB_CKN0 /DDRB_CKN0

02 (2010-01-19) 4-1

Hi3520
4
DDRA_CKP1 O 1 DDRA_CKP1
/DDRB_CKP1 /DDRB_CKP1
DDRA_CKN1 O 1 DDRA_CKN1
/DDRB_CKN1 /DDRB_CKN1
DDRA_CKE O DDR2 SDRAM DDRA_CKE
/DDRB_CKE /DDRB_CKE
DDRA_CSN O DDR2 SDRAM DDRA_CSN
/DDRB_CSN /DDRB_CSN
DDRA_RASN O DDR2 SDRAM RAS DDRA_RASN
/DDRB_RASN /DDRB_RASN
DDRA_CASN O DDR2 SDRAM CAS DDRA_CASN
/DDRB_CASN /DDRB_CASN
DDRA_WEN O DDR2 SDRAM WE DDRA_WEN
/DDRB_WEN /DDRB_WEN
DDRA_ODT O DDR2 SDRAM DDRA_ODT
/DDRB_ODT /DDRB_ODT
DDRA_BA0 O DDR2 SDRAM Bank 0 DDRA_BA0
/DDRB_BA0 /DDRB_BA0
/DDRB_BA1 /DDRB_BA1
/DDRB_BA2 /DDRB_BA2
DDRA_ADR[13:0] O DDR SDRAM DDRA_ADR13
/DDRB_ADR[13:0] DDRA_ADR
/DDRB_ADR13
DDRB_ADR
DDRA_LDM0 O DDR2 SDRAM0 DDRA_LDM0

/DDRB_LDM0 DQ0DQ7 /DDRB_LDM0
DDRA_UDM0 O DDR2 SDRAM0 DDRA_UDM0
/DDRB_UDM0 DQ8 /DDRB_UDM0
DQ15
DDRA_LDM1 O DDR2 SDRAM1 DDRA_LDM1

/DDRB_LDM1 DQ16 /DDRB_LDM1
DQ23

4-2 02 (2010-01-19)

Hi3520
4
DDRA_UDM1 O DDR2 SDRAM1 DDRA_UDM1

/DDRB_UDM1 DQ24 /DDRB_UDM1
DQ31
DDRA_DQSP0 I/O DQS0 DDRA_DQSP0

/DDRB_DQSP0 DQ0DQ7 /DDRB_DQSP0
DDRA_DQSN0 I/O DQS0 DDRA_DQSN0
/DDRB_DQSN0 DQ0DQ7 /DDRB_DQSN0
DDRA_DQ[31:0] I/O DDRA_DQ31
/DDRB_DQ[31:0] DDRA_DQ0
/DDRB_DQ31
DDRB_DQ0

CSChip Select
RASRow Address Select
CASColumn Address Select
WEWrite Enable
DQSData Strobe
DMData Mask
4.1.4
4.1.4.1

02 (2010-01-19) 4-3

Hi3520
4
DDRC0DDRC1 DDRCDDRADDRB
DDR32bit DDRC0
DDRC SoC CPU DDR2 SDRAM

CPU DDRC JEDECJESD79 DDR2
SDRAM
DDRC DDR2 SDRAM

z 16bit
DDRC 1 16bit DDR2 SDRAM
4-1
z 32bit
DDRC0 2 16bit DDR2 SDRAM DDRC1
32bit 4-2
4-1 DDRC 1 DDR2 SDRAM
Hi3520
DDR_CKP0 CK
DDR_CKN0 CK# DDR2 SDRAM 0
DDR_DQ[15:0] DQ[15:0]
DDR_DQSP[1:0] DQS[1:0]
DDR_DQSN[1:0] DQS#[1:0]
DDR_DM[1:0] DM[1:0] (UDM,LDM)
DDR_CKE
DDR_CSN
DDR_RASN
DDRC DDR_CASN
DDR_WEN (CKE/CS/RAS/CAS
DDR_ODT /WEBAAxODT)
DDR_BA[2:0]
DDR_ADR[13:0]
DDR_CKP1
DDR_CKN1
DDR_DQ[31:16]
DDR_DQSP[3:2]
DDR_DQSN[3:2]
DDR_DM[3:2]

#
DDR2 SDRAM0 16bit 4-1 Hi3520 16bit DDR2
DDRC DDR2 SDRAM

4-4 02 (2010-01-19)

Hi3520
4
DDRC DDR_CKEDDR_CSNDDR_RASNDDR_CASNDDR_WENDDR_BA[2:0]
DDR_ADR[13:0] DDR2 SDRAM0 4-1 CKE/CS/RAS/CAS
/WEBAAx
DDRC DDR_CKP1DDR_CKN1DDR_DQ[31:16]DDR_DQSP[3:2]DDR_DQSN[3:2]
DDR_DM[3:2]
DDR2 SDRAM 1Gbit DDRC DDR_BA[2]
4-2 DDRC 2 DDR2 SDRAM
Hi3520
DDR_CKP0 CK
DDR_DQ[15:0] DQ[15:0]
DDR_CKE
DDR_CSN
DDR_RASN
DDRC DDR_CASN
DDR_WEN (CKE/CS/RAS/CAS
DDR_ODT /WEBAAxODT)
DDR_BA[2:0]
DDR_ADR[13:0]
DDR_CKP1 CK
DDR_DQ[31:16] DQ[15:0]

#
DDR2 SDRAM0 DDR2 SDRAM1 16bit 4-2 32bit DDR2
DDRC0 DDR2 SDRAM
DDRC DDRA_CKEDDRA_CSNDDRA_RASNDDRA_CASNDDRA_WEN
DDRA_BA[2:0]DDRA_ADR[13:0] DDR2 SDRAM0 4-2 CKE
/CS/RAS/CAS/WEBAAx
DDR2 SDRAM 1Gbit DDRC0 DDR_BA[2]
4.1.4.2
DDRC DRAM DDR2 SDRAM 4-2
DDR2
SDRAM

02 (2010-01-19) 4-5

Hi3520
4
4-2 DDRC DDR2 SDRAM
200MHz 333MHz 400MHz
JESD79 DDR2-400 DDR2-667 DDR2-800 12

DDR2 Standard DDR2-533 DDR2-800
DDR2-667
DDR2-800
Micron -5E DDR2-400 -3 DDR2-667 -25 DDR2-800 3
-37E DDR2-533 -3E DDR2-667 -25E DDR2-800
-3 DDR2-667 -25 DDR2-800
-3E DDR2-667 -25E DDR2-800
-25 DDR2-800
-25E DDR2-800
ELPIDA -4A DDR2-400 -6E DDR2-667 -8E DDR2-800 3
-5C DDR2-533 -6C DDR2-667
-6E DDR2-667 -8E DDR2-800
-6C DDR2-667
-8E DDR2-800
Hynix -E3 DDR2-400 -Y4 DDR2-667 -S5 DDR2-800 3
-C4 DDR2-533 -Y5 DDR2-667 -S6 DDR2-800
-Y4 DDR2-667 -S5 DDR2-800
-Y5 DDR2-667 -S6 DDR2-800
-S5 DDR2-800
-S6 DDR2-800
Samsung -CC DDR2-400 -E6 DDR2-667 -E7 DDR2-800 3
-D5 DDR2-533 -E7 DDR2-800
-E6 DDR2-667
-E7 DDR2-800

1DDRC JESD79 DDRC
DRAM DDRC 4-2

2 DDR2 SDRAM
DDRC 4-2 DDR2 SDRAM DDR2
SDRAM
3 DDR2 SDRAM BurstLength 4
DDRC JESD79 DDR2 SDRAM DDR2 SDRAM

DDR2 SDRAM DDR2 SDRAM
AUTO Refresh

4-6 02 (2010-01-19)

Hi3520
4
DDRC DDR2 SDRAM DDRC Command Truth

Table 4-3
4-3 DDRC
FUNCTION DDR DDR DDR DDR DDR DDRADR DDRBA

CKE CSN RASN CASN WEN 11 AP(10) 9:0
DESELECT H H X X X X X X X
NOP H L H H H X X X X
ACTIVE H L L H H V V V V
READ H L H L H V V V V
WRITE H L H L L V V V V
PRECHARGE H L L H L X L X V
PRECHARGE H L L H L X H X X
ALL
AUTO H L L L H X X X X
Refresh
SELF Refresh L L L L H X X X X
MODE H L L L L V V V V
REGISTER
SET
1DDRADR AP PRECHARGE BANK PRECHARGE
BANK PRECHARGE AP DDR JEDEC
2H L V X
3DDRC DDR2 Burst Length 4 DDR2 Burst Terminate

DDRC_TIMING2[taref]DDRC AUTO Refresh

DDR2 SDRAM DDR2 SDRAM 64ms
8192 7.8sDDRC_TIMING2[taref]
TarefT=7.8s
TTaref%16DDR
DDRC_TIMING2[taref]DDRC taref
0 DDRC taref

02 (2010-01-19) 4-7

Hi3520
4
DDRC
z
pd_prd DDRC DDR2 SDRAM
PowerDown
DDRC_CONFIG[pd_en][pr_prd]DDRC
DDR2 SDRAM DDRC_CONFIG[pd_en] 1
DDRC DDRC_CONFIG[pr_prd]
DDR2 SDRAM
z
DDRC DDR2
SDRAM DDR2 SDRAM
DDR2 SDRAM DDR2 SDRAM
DDRC_CTRL[sr_req]DDRC DDR2 SDRAM
DDRC_CTRL[sr_req] 1 DDRC DDR2
SDRAM DDRC_CTRL
[sr_req] 0
DDRC DDRC_QOS[pri]DDRC
DDR2 SDRAM
DDRC_QOS[qos_en][qos]DDRC

DDRC DDR2 SDRAM DDR2

SDRAM DDRC_CONFIG[mem_map][mem_row][mem_col]
DDRC DDR2 SDRAM
DDR2 SDRAM
29 BUS_ADR[28:0] BUS_ADR[m1:0]Hi3520 DDRC
DDR_ADR[13:0]DDR2 SDRAM DDR_ROW[x1:0]
DDR_COL[y1:0]BANK DDR_BA[z1:0] 1Gbit DDR2 SDRAM
[row_addrcol_addrbank_addr][13103] x=13y=10z=3
DDRC DW
z DDRC_CONFIG[mem_map] 0 RBC
BUS_ADR[m1:0]={DDR_ROW[x1:0]DDR_BA[z1:0]DDR_COL[y1:0]
DW{b0}}
z DDRC_CONFIG[mem_map] 1 BRC
BUS_ADR[m1:0]={DDR_BA[z1:0]DDR_ROW[x1:0]DDR_COL[y1:0]
DW{b0}}
m=x+y+z+DW

4-8 02 (2010-01-19)

Hi3520
4
z DDRC 16bit DW 1
z DDRC 32bit DW 2
RBC A10 DDR AP DDR2 SDRAM

4-4 4-5
BRC
4-4 DDRC 16bit
DDRBA DDRADR

Mbit%bw 2 1 0 13 12 11 10/AP 9 8 7:0
256Mbit 4bank
- 24 23 22 21 20 [19:12]
16%16 13 9 - 11 10
- - - AP - 9 [8:1]
512Mbit 4bank
- 25 24 23 22 21 [20:13]
32%16 13 10 - 12 11
- - - AP 10 9 [8:1]
1Gbit 8bank
- 26 25 24 23 22 [21:14]
64%16 13 10 13 12 11
- - - AP 10 9 [8:1]
2Gbit 8bank
27 26 25 24 23 22 [21:14]
128%16 14 10 13 12 11
- - - AP 10 9 [8:1]
4-5 DDRC 32bit
DDRBA DDRADR

Mbit%bw 2 1 0 13 12 11 10/AP 9 8 [7:0]
256Mbit 4bank
- 25 24 23 22 21 [20:13]
1616 13 9 - 12 11
- - - AP - 10 [9:2]
512Mbit 4bank
- 26 25 24 23 22 [21:14]
3216 13 10 - 13 12
- - - AP 11 10 [9:2]

02 (2010-01-19) 4-9

Hi3520
4
DDRBA DDRADR

Mbit%bw 2 1 0 13 12 11 10/AP 9 8 [7:0]
1Gbit 8bank
- 27 26 25 24 23 [22:15]
6416 13 10 14 13 12
- - - AP 11 10 [9:2]
2Gbit 8bank
28 27 26 25 24 23 [22:15]
12816 14 10 14 13 12
- - - AP 11 10 [9:2]
4.1.5
4.1.5.1
DDRC
DDRC
DDRC
1 Flash
2 DDRC_CONFIG[sr_cc] 1
5 DDRC
----
DDRC
1 NORMAL DDRC
2 DDRC DLLDelay Lock Loop
----

4-10 02 (2010-01-19)

Hi3520
4
4.1.5.2
DDRC DDRC
DDRC DDR2 SDRAM
4.1.5.3
DDR2 SDRAM DDR2
SDRAM
z DDR2 SDRAM JEDEC VDD
VDDQ VREF VTT
z NORMAL
DDR2 SDRAM
1 200s
2 DDRC_CTRL 0x0000_0000
3 400ns
4 DDRC_EMRS01 0x32 DDRC_EMRS23 0x00

DDR2 SDRAM DDR cas
latency 6burst length 8
DDR2 SDRAM 0
z Cas Latency DDRC_EMRS01[tcl]

z DDRC_EMRS01 DDR2 SDRAM MRS 1
EMRS1 DDR2 SDRAM A15-A0
3 bank
z DDR2 1EMRS1 RDQS DQS

5 DDRC_CONFIG 0x7000_7022
RBC AP A10 10 13
7 AUTO RefreshDDRC_CONFIG[pd_en]

6 DDRC_TIMING0DDRC_TIMING1DDRC_TIMING2DDRC_TIMING3
cl DDRC_EMRS01
7 DDRC_ODT_CONFIG DDR2
odt odt
8 DDRC_QOS DDRC_QOS DDRC_QOS[qos]

1 0x0020x3FF
9 DDRC_CTRL 0x2

02 (2010-01-19) 4-11

Hi3520
4
10 DDRC_STATUS bit[3] 1
----
DDR2 SDRAM
4.1.6
DDRC0 DDRC1
DDR0 0xC000_0000
DDR1 0xE000_0000
DDRC0 0x2011_0000
DDRC1 0x2012_0000
DDRC 4-6
4-6
0x000 DDRC_STATUS 4-13
0x004 DDRC_CTRL 4-13
0x008 DDRC_EMRS01 1 4-14
0x00C DDRC_EMRS23 2 4-16
0x010 DDRC_CONFIG 4-16
0x020 DDRC_TIMING0 0 4-18
0x02C DDRC_TIMING3 3 4-22
0x094 DDRC_ODT_CONFIG ODT 4-23
0x104 DDRC_QOS_CONFIG QOS 4-23
0x108+n%4 DDRC_QOS 4-24
0x200 DDRC_DLL_CONTROL DLL 4-25
0x244 DDRC_DLL_SRST DLL 4-25
0x268 DDRC_IO_CONFIG IO 4-26
n 16ID QOS 015

4-12 02 (2010-01-19)

Hi3520
4
4.1.7
DDRC_STATUS
DDRC_STATUS

0x000 DDRC_STATUS 0x0000_004D
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
in_init
in_sr
busy
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1
[31:4] RO reserved
Initialization
[3] RO in_init 0
1
SELF Refresh
[2] RO in_sr 0
1
[1] RO reserved

[0] RO busy 0
1
DDRC_CTRL
DDRC_CTRL

02 (2010-01-19) 4-13

Hi3520
4

0x004 DDRC_CTRL 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clk_ratio
init_req
sr_req
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:2] - reserved
1
[1] RW init_req 0
1
SELF Refresh
[0] RW sr_req 0
1
DDRC_EMRS01
DDRC_EMRS01 1

0x008 DDRC_EMRS01 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ddr_dll_en
ddr_rtt1
ddr_rtt0
ddr_drv
ddr_tm
ddr_wr
ddr_rst
ddr_bt
Name reserved ddr_al reserved ddr_cas ddr_bl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:23] RW reserved 0

4-14 02 (2010-01-19)

Hi3520
4
DDR2 SDRAM ddr_rtt0

[ddr_rtt1ddr_rtt0]
00
[22] RW ddr_rtt1 0175
10150
1150
DDR2 SDRAM
[21:19] RW ddr_al 0
DDR2 SDRAM ddr_rtt1

[ddr_rtt1ddr_rtt0]
00
[18] RW ddr_rtt0 0175
10150
1150
DDR2 SDRAM
DDR2 SDRAM
0
[17] RW ddr_drv
1
SI
DDR2 SDRAM DLL

[16] RW ddr_dll_en 0
1
[15:12] RW reserved 0
DDR2 SDRAM
0102
0113
[11:9] RW ddr_wr 1004
1015
1106

DDR2 SDRAM DLL

[8] RW ddr_rst 0
1

02 (2010-01-19) 4-15

Hi3520
4
DDR2 SDRAM
[7] RW ddr_tm 0
1
DDR2 SDRAM CAS

0113
1004
[6:4] RW ddr_cas
1015
1106

DDR2 SDRAM burst

[3] RW ddr_bt 0
1
DDR2 SDRAM burst

0104
[2:0] RW ddr_bl
0118

DDRC_EMRS23
DDRC_EMRS23 2

0x00C DDRC_EMRS23 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name emrs3 emrs2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] RW emrs3 0
[15:0] RW emrs2 0
DDRC_CONFIG
DDRC_CONFIG

4-16 02 (2010-01-19)

Hi3520
4

0x010 DDRC_CONFIG 0x0000_6022
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mem_bank
mem_map
mem_row
mem_col
reserved
reserved
reserved
reserved
pd_en
sr_cc
Name init_arefnum pr_prd mem_type
ap
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0
AUTO Refresh
0x00x22
[31:28] RW init_arefnum
0x30xFn
n
power down CLK

CKE
0x00 pd_en

[27:20] RW pr_prd
0x010xn pd_en n

n 0x033

[19] RW reserved

[18] RW sr_cc 0
1
[17] RW reserved
power down DDR2 SDRAM CKE

PD_PRD
[16] RW pd_en CKE
0 power down
1 power down

0x616bit DDR2
[15:12] RW mem_type
0x732bit DDR2

[11:10] RW reserved

02 (2010-01-19) 4-17

Hi3520
4
PRECHARGE ALL
[9] RW ap 0a10
1a8
memory
[8] RW mem_map 0RowBankColDw
1BankRowColDw
memory bank
[7] RW mem_bank 04bank
18bank

00011
00112
01013
[6:4] RW mem_row
01114
10015
10116

[3] RW reserved

0008
0019
[2:0] RW mem_col 01010
01111
10012

DDRC_TIMING0
DDRC_TIMING0 0

4-18 02 (2010-01-19)

Hi3520
4

0x020 DDRC_TIMING0 0x7FFF_3F1F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
Name tmrd trrd trp trcd trc tras
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1
[31] RW reserved
LMR
0000011
[30:28] RW tmrd
010111n
n 0102
BANK A BANK B ACT bank a to ACT bank

b
[27:24] RW trrd 0x00x11
0x20xFn
n 0xF15
PRE period
0x00x11
[23:20] RW trp 0x20xEn
0xF
n 0x77
BANK ACT to READ or WRITE

[19:16] RW trcd 0x00x33
0x40xFn
n 00113
[15:14] RW reserved
BANK Active a bank to Active a

bank
[13:8] RW trc 0x000x011
0x020x0Fn
n 0x0F15
[7:5] RW reserved

02 (2010-01-19) 4-19

Hi3520
4
BANK ACT to PRE

[4:0] RW tras 0x000x011
0x000x0Fn
n 0x0F15
DDRC_TIMING1
DDRC_TIMING1 1

0x024 DDRC_TIMING1 0xFF01_23FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name tsre trdlat trtw twl tcl trfc
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1
SELF-Refresh
0x000xFFn
[31:24] RW tsre
n 0xFF255
200
DQS
[23:20] RW trdlat 0x00xFn+1
n 0x0 1
[19] RW reserved

[18:16] RW trtw 000110n+1
n 0x0 1

0x00xFn
[15:12] RW twl n 0x33
DDR2 twl tcl1twl
twltaond1
[11] RW reserved

4-20 02 (2010-01-19)

Hi3520
4
DDR CAS Latency

011CL=3
100CL=4
[10:8] RW tcl
101CL=5
110CL=6

AREF period or AREF

to ACT
[7:0] RW trfc 0x000x011
0x020xFFn
n 0x0F15
DDRC_TIMING2
DDRC_TIMING2 2

0x028 DDRC_TIMING2 0x33F3_F7FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
reserved
Name tcke twtr twr tfaw taref
Reset 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
[31:30] RW reserved
DDR
00011
[29:28] RW tcke
1011n
n
[27:26] RW reserved
Write to Read

[25:24] RW twtr 00011
0111n
n 113

02 (2010-01-19) 4-21

Hi3520
4
Write Recovery
0x00x11
[23:20] RW twr
0x20xfn
n 0x77
[19:18] RW reserved
4
[17:12] RW tfaw 0x000x3Fn
n 0x1420
[11] RW reserved

0x000
[10:0] RW taref 0x0010x7FFSDRAM 16%n
n 0x008128
SDRAM
DDRC_TIMING3
DDRC_TIMING3 3

0x02C DDRC_TIMING3 0x0000_0F02
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved taond reserved txard reserved trtp
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0
[31:22] RO reserved
ODTOn Die Termination

Taond/Taofd
002/2.5
[21:20] RW taond
013/3.5
104/4.5
115/5.5
[19:12] RW reserved

4-22 02 (2010-01-19)

Hi3520
4
DDR2 SDRAM
0x00xFn
[11:8] RW txard
n 0x7 7 txptxard
txards
[7:3] RW reserved

0000102
[2:0] RW trtp 011111n

AL+BL/2+Max(trtp,2)2
DDRC_ODT_CONFIG
DDRC_ODT_CONFIG ODT

0x094 DDRC_ODT_CONFIG 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wodt
rodt
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:2] RO reserved
ODT
[1] RW rodt 0
1
ODT
[0] RW wodt 0
1
DDRC_QOS_CONFIG
DDRC_QOS_CONFIG QOS

02 (2010-01-19) 4-23

Hi3520
4

0x104 DDRC_QOS_CONFIG 0x0000_3210
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved id_map
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
[31:16] RO reserved
ID 4 QOS
bit[15:12] ID bit[3]
bit[11:8] ID bit[2]
[15:0] RW id_map bit[7:4] ID bit[1]
bit[3:0] ID bit[0]
id_map 0x5320 ID {ID[5]
ID[3]ID[2]ID[0]} ID
DDRC_QOS
DDRC_QOS

0x108+n%4 DDRC_QOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
qos_en
Name reserved qos pri
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] RO reserved
QOS
[16] RW qos_en 0
1
[15:14] RW reserved
[13:4] RW qos 0x0020x3FF
[3] RW reserved

4-24 02 (2010-01-19)

Hi3520
4

000
001
[2:0] RW pri

111
000>001>>111
DDRC_DLL_CONTROL
DDRC_DLL_CONTROL DLL

0x240 DDRC_DLL_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved dll_bypass
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] RO reserved
DLL_BYPASS
bit[5] DLL
bit[4]ECC DLL
bit[3] 3 DLL
[5:0] RW dll_bypass bit[2] 2 DLL
bit[1] 1 DLL
bit[0] 0 DLL
0
1
DDRC_DLL_SRST
DDRC_DLL_SRST DLL

02 (2010-01-19) 4-25

Hi3520
4

0x244 DDRC_DLL_SRST 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dll_srst_n
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] RO reserved
DLL
[0] RW dll_srst_n 0
1
DDRC_IO_CONFIG
DDRC_IO_CONFIG IO

0x268 DDRC_IO_CONFIG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sstl_byte3_en
sstl_byte2_en
sstl_byte1_en
sstl_byte0_en
sstl_cmd_en
sstl_ecc_en
ddr_mode
cmd_ds
dqs_ds
dq_ds
ck_ds
Name reserved rtt

ae
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:14] RO reserved
IO
0
[13] RW ae
1
DLL

4-26 02 (2010-01-19)

Hi3520
4
IO
[12] RW ddr_mode 0DDR2
1DDR1
IO
DDR2 SDRAM
0SSTL_18
[11] RW ck_ds 1SSTL_18
DDR SDRAM
0SSTL_2class1
1SSTL_2class2
IO
DDR2 SDRAM
0SSTL_18
[10] RW cmd_ds 1SSTL_18
DDR SDRAM
0SSTL_2 class1
1SSTL_2 class2
DQ/DM IO
DDR2 SDRAM
0SSTL_18
[9] RW dqs_ds 1SSTL_18
DDR SDRAM
0SSTL_2 class1
1SSTL_2 class2
DQS IO DS
DDR2 SDRAM
0SSTL_18
[8] RW dq_ds 1SSTL_18
DDR SDRAM
0SSTL_2 class1
1SSTL_2 class2
IO ODT
00
[7:6] RW rtt 01150
1075
1150

02 (2010-01-19) 4-27

Hi3520
4
IO IDDQ
0SSTL
[5] RW sstl_cmd_en
1SSTL LVCMOS
ODT
IO IDDQ
0SSTL
[4] RW sstl_ecc_en
1SSTL LVCMOS
ODT
IO IDDQ
0SSTL
[3] RW sstl_byte3_en
1SSTL LVCMOS
ODT
IO IDDQ
0SSTL
1SSTL LVCMOS
ODT
IO IDDQ
0SSTL
1SSTL LVCMOS
ODT
IO IDDQ
0SSTL
1SSTL LVCMOS
ODT
4.2 SMI
4.2.1
SMIStatic Memory Interface SRAM
Static Random Access MemoryPSRAMPseudo Static Access MemoryROM
Read Only MemoryNOR Flash

4.2.2
SMI

4-28 02 (2010-01-19)

Hi3520
4
z SRAMPSRAMROM NOR Flash

z page
z
z 2 0 1
z 0
z 8bit
z 8bit 256Mbit
z TWSTRDTWSTWR burst
TWSTBURSTRD 31 SMI
z TWSTOENTWSTWEN
15 SMI
z TWSTIDLY 15
SMI
z
z
4.2.3
SMI 4-7
4-7 SMI
SMI_CS0 O SMI 0 SMICS0N

SMI_CS1 O SMI 1 SMICS1N

GPIO
4.2.5

SMI_OEN O SMI SMIOEN

SMI_WEN O SMI EBIWEN

SMI_ADDR[24:0] O SMI EBIADR24

SMI_ADDR[24:15] EBIADR0
BOOTSELFUNSELNF

4.2.5

02 (2010-01-19) 4-29

Hi3520
4
SMI_DATA[7:0] I/O SMI EBIDQ7

EBIDQ0
SMI_WAIT I SMI EBIRDYN

IRRCV
4.2.5

4.2.4
SMI
4-3
4-3 SMI
Hi3520 NOR Flash

SMI
SMI_CS1
SMI_CS0 CE#
SMI_OEN OE#
SMI_WEN WE#
SMI_ADDR ADDR
SMI_DATA DQ
SMI_WAIT

SMI SMI_CS0 SMI_CS1 SMI_CS0 8bit

SMI SMI_WAIT
SMI
4-4

4-30 02 (2010-01-19)

Hi3520
4
4-4 SMI
Hi3520

SMI
SMI_CS0
SMI_CS1 CE#
SMI_OEN OE#
SMI_WEN WE#
SMI_ADDR ADDR
SMI_DATA DQ
SMI_WAIT WAIT

SMI SMI_CS0 SMI_CS1 SMI_CS0 8bit

SMI SMI_WAIT/WAIT

SMI SMI
SMI SMI
4-8

4-8 SMI fBUSCLK=200MHz
fSMICLK=200MHz fSMICLK=100MHz
TWSTRD(max) 155ns 309ns
TWSTWR(max) 155ns 309ns
burst TWSTBURSTRD(max) 155ns 309ns
TWSTOEN(max) 75ns 150ns
TWSTWEN(max) 75ns 150ns
TWSTIDLY(max) 75ns 150ns

02 (2010-01-19) 4-31

Hi3520
4
SMI 0
SMI

z
SMI
SMI SMI

z
SMI
SMI

SMI
4-5 4-5 SMI

4-5 SMI
T_WSTIDLY
SMI_CS
T_WSTOEN
SMI_OEN
T_WSTWEN
T_WSTWR
SMI_WEN
T_WSTRD
SMI_DATA D(A) D(B)
4-9 SMI
4-9 SMI
T_WSTOEN 0 - TWSTOEN(max) SMI

T_WSTRD - - TWSTRD(max) SMI

T_WSTIDLY 0 - TWSTIDLY(max) SMI

4-32 02 (2010-01-19)

Hi3520
4
T_WSTWEN 0 - TWSTWEN(max) SMI

T_WSTWR 0 - TWSTWR(max) SMI

4-6 page SMI page

4-6 SMI page
SMI_ADDR A A+4 A+8 A+C
SMI_CS
T_WSTOEN
SMI_OEN
T_WSTBURSTRD
T_WSTBURSTRD
T_WSTRD T_WSTBURSTRD
SMI_DATA D(A) D(A+4) D(A+8) D(A+C)
4-10 SMI page
4-10 SMI page
T_WSTOEN 0 - TWSTOEN(max) SMI

T_WSTRD - - TWSTRD(max) SMI

T_WSTBURSTRD - - TWSTBURSTRD( SMI page

max)
4-7
4-7 SMI SMI_WAIT

02 (2010-01-19) 4-33

Hi3520
4
4-7 SMI wait
wait wait
SMI_ADDR A B
SMI_CS
SMI_OEN
SMI_WEN
SMI_DATA D(A) D(B)
SMI_WAIT
4.2.5
SMI SMI IO Config

reg71 reg74

SC_PERDIS[smiclkdis] 1 SMI
SMI SC_PEREN[smiclken]
1 SMI
SMI SC_PERCLKEN
SMI_CR SC_PERCTRL9[ssmcclk_sel]

SC_PERCTRL9[ssmcclk_sel] SMI
SMI
SMI 0 8bit

4-34 02 (2010-01-19)

Hi3520
4
SMI 0

SMI 4-11
4-11 SMI
0 0x8000_00000x81FF_FFFF
1 0x8400_00000x85FF_FFFF
SMI
SMI SMI
4.2.4
z SMI SMI
SMI_CR[memclkratio] SMI_BCR[mw]

z TWSTOEN TWSTRD TWSTWEN
TWSTWR
SMI 1
1 SMI_CR SMI
2 SMI_BIDCYR1[idcy] TWSTIDLY
3 SMI_BWSTRDR1[wstrd] TWSTRD
4 SMI_BWSTWRR1[wstwr] TWSTWR
5 SMI_BWSTOENR1[wstoen] TWSTOEN
6 SMI_BWSTWENR1[wstwen] TWSTWEN
7 SMI_BWSTBRDR1[wstbrdr] burst TWSTBURSTRD
8 SMI_BCR
----

02 (2010-01-19) 4-35

Hi3520
4
CPU SMI
SMI
SMI SMI

SMI 1
1 IO Config reg74 EBIRDYN SMI_WAIT
2 SMI_CR SMI
3 SMI_BCR
4 SMI_BCR[waitpol]
5 SMI_BCR[waiten] 1 SMI
----
SMI
4.2.6
4-12 SMI 0x1001_0000
0x000 SMI_BIDCYR1 SMI 1 4-37
0x004 SMI_BWSTRDR1 SMI 1 4-38
0x008 SMI_BWSTWRR1 SMI 1 4-38
0x00C SMI_BWSTOENR1 SMI 1 4-39

0x010 SMI_BWSTWENR1 SMI 1 4-40

0x014 SMI_BCR1 SMI 1 4-40
0x018 SMI_BSR1 SMI 1 4-42
0x01C SMI_BWSTBRDR1 SMI 1 4-42

0x020
RESERVED -
0x0DC
0x0E0 SMI_BIDCYR0 SMI 0 4-43
0x0E4 SMI_BWSTRDR0 SMI 0 4-44

4-36 02 (2010-01-19)

Hi3520
4
0x0E8 SMI_BWSTWRR0 SMI 0 4-44
0x0EC SMI_BWSTOENR0 SMI 0 4-45

0x0F0 SMI_BWSTWENR0 SMI 0 4-45

0x0F4 SMI_BCR0 SMI 0 4-46
0x0F8 SMI_BSR0 SMI 0 4-48
0x0FC SMI_BWSTBRDR0 SMI 0 4-48

0x100
RESERVED -
0x1FC
0x200 SMI_SR SMI 4-49
0x204 SMI_CR SMI 4-49
0x208
RESERVED -
0xFFC
4.2.7
SMI_BIDCYR1
SMI_BIDCYR1 SMI 1


0x000 SMI_BIDCYR1 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved idcy
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved

02 (2010-01-19) 4-37

Hi3520
4
TWSTIDLY
1
TWSTIDLY = idcy
[3:0] RW idcy f SMICLK
idcy SMI
fSMICLK SMI
SMI_BWSTRDR1
SMI_BWSTRDR1 SMI 1


0x004 SMI_BWSTRDR1 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstrd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved
TWSTRD
non burst
burst 1
SMI_BWSTBRDR1
[4:0] RW wstrd
1
TWSTRD = wstrd
f SMICLK
wstrd SMI
fSMICLK SMI
SMI_BWSTWRR1
SMI_BWSTWRR1 SMI 1

4-38 02 (2010-01-19)

Hi3520
4

0x008 SMI_BWSTWRR1 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstwr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved
TWSTWR
1
TWSTWR = wstwr
[4:0] RW wstwr f SMICLK
wstwr SMI
fSMICLK SMI
SMI_BWSTOENR1
SMI_BWSTOENR1 SMI 1


0x00C SMI_BWSTOENR1 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstoen
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved
TWSTOEN

1
[3:0] RW wstoen TWSTOEN = wstoen
f SMICLK
wstoen SMI
fSMICLK SMI

02 (2010-01-19) 4-39

Hi3520
4
SMI_BWSTWENR1
SMI_BWSTWENR1 SMI 1


0x010 SMI_BWSTWENR1 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstwen
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved
TWSTWEN

1
[3:0] RW wstwen TWSTWEN = wstwen
f SMICLK
wstwen SMI
fSMICLK SMI
SMI_BCR1
SMI_BCR1 SMI 1 1

0x014 SMI_BCR1 0x0030_3020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
burstlenwrite
burstlenread
reserved
reserved
reserved
reserved
reserved
reserved
reserved
bmwrite
bmread
waitpol
waiten
Name reserved reserved mw wp
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0
[31:22] - reserved
[21] RW reserved 1
[20] RW reserved 1

4-40 02 (2010-01-19)

Hi3520
4
burst burst burst

[19:18] RW burstlenwrite 00burst 4
01burst 8
1011
[17] RW reserved 0

[16] RW bmwrite 0 non burst
1 burst
[15] - reserved
[14] RW reserved 0
[13] RW reserved 1
[12] RW reserved 1
burst burst

00burst 4
[11:10] RW burstlenread
01burst 8
10burst 16
11
[9] RW reserved 0

[8] RW bmread 0 non burst
1 burst
[7] - reserved
[6] RW reserved 0
SMI 1
[5:4] RW mw 008bit

[3] RW wp 0 SRAM
1 ROM

02 (2010-01-19) 4-41

Hi3520
4
SMI 1
0 SMI 1
[2] RW waiten
1 SMI 1

[1] RW waitpol 0
1
[0] RW reserved 0
SMI_BSR1
SMI_BSR1 SMI 1 1

0x018 SMI_BSR1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
waittouterr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved

0
[0] RW waittouterr 1

0
1
SMI_BWSTBRDR1
SMI_BWSTBRDR1 SMI 1 burst burst
1

4-42 02 (2010-01-19)

Hi3520
4

0x01C SMI_BWSTBRDR1 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstbrd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved
TWSTBURSTRDburst
non burst
burst burst 1

burst 1
[4:0] RW wstbrd SMI_BWSTRDR1
1
TWSTBURSTRD = wstbrd
f SMICLK
wstbrd SMI
fSMICLK SMI
SMI_BIDCYR0
SMI_BIDCYR0 SMI 0


0x0E0 SMI_BIDCYR0 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved idcy
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved
TWSTIDLY
1
TWSTTIDLY = idcy
[3:0] RW idcy f SMICLK
idcy SMI
fSMICLK SMI

02 (2010-01-19) 4-43

Hi3520
4
SMI_BWSTRDR0
SMI_BWSTRDR0 SMI 0


0x0E4 SMI_BWSTRDR0 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstrd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved
TWSTRD
non burst
burst 1
SMI_BWSTBRDR0
[4:0] RW wstrd
1
TWSTRD = wstrd
f SMICLK
wstrd SMI
fSMICLK SMI
SMI_BWSTWRR0
SMI_BWSTWRR0 SMI 0


0x0E8 SMI_BWSTWRR0 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstwr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved

4-44 02 (2010-01-19)

Hi3520
4
TWSTWR
1
TWSTWR = wstwr
[4:0] RW wstwr f SMICLK
wstwr SMI
fSMICLK SMI
SMI_BWSTOENR0
SMI_BWSTOENR0 SMI 0


0x0EC SMI_BWSTOENR0 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstoen
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved
TWSTOEN

1
[3:0] RW wstoen TWSTOEN = wstoen
f SMICLK
wstoen SMI
fSMICLK SMI
SMI_BWSTWENR0
SMI_BWSTWENR0 SMI 0

02 (2010-01-19) 4-45

Hi3520
4

0x0F0 SMI_BWSTWENR0 0x0000_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstwen
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:4] - reserved
TWSTWEN

1
[3:0] RW wstwen TWSTWEN = wstwen
f SMICLK
wstwen SMI
fSMICLK SMI
SMI_BCR0
SMI_BCR0 SMI 0 0

0x0F4 SMI_BCR0 0x0030_3000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
burstlenwrite
burstlenread
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
bmwrite
bmread
waitpol
waiten
mw
wp
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
[31:22] - reserved
[21] RW reserved 1
[20] RW reserved 1
burst burst 4-6 burst

[19:18] RW burstlenwrite 00burst 4
01burst 8
1011

4-46 02 (2010-01-19)

Hi3520
4
[17] RW reserved 0

[16] RW bmwrite 0 non burst
1 burst
[15] - reserved
[14] RW reserved 0
[13] RW reserved 1
[12] RW reserved 1
burst burst burst

00burst 4
[11:10] RW burstlenread
01burst 8
10burst 16
11
[9] RW reserved 0

[8] RW bmread 0 non burst
1 burst
[7] - reserved
[6] RW reserved 0
SMI 0
[5:4] RW mw 008bit

[3] RW wp 0 SRAM
1 ROM
SMI 0
0 SMI 0
[2] RW waiten
1 SMI 0

[1] RW waitpol 0
1

02 (2010-01-19) 4-47

Hi3520
4
[0] RW reserved 0
SMI_BSR0
SMI_BSR0 SMI 0 0

0x0F8 SMI_BSR0 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
waittouterr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved

0
[0] RW waittouterr 1

0
1
SMI_BWSTBRDR0
SMI_BWSTBRDR0 SMI 0 burst burst


0x0FC SMI_BWSTBRDR0 0x0000_001F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved wstbrd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
[31:5] - reserved

4-48 02 (2010-01-19)

Hi3520
4
TWSTBURSTRDburst
non burst
burst burst 1

burst 1
[4:0] RW wstbrd SMI_BWSTRDR0
1
TWSTBURSTRD = wstbrd
f SMICLK
wstbrd SMI
fSMICLK SMI
SMI_SR
SMI_SR SMI


0x200 SMI_SR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
waitstatus
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
SMI
[0] RO waitstatus 0
1
SMI_CR
SMI_CR SMI SMI

02 (2010-01-19) 4-49

Hi3520
4

0x204 SMI_CR 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
memclkratio
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:3] - reserved
SMI
00SMI
[2:1] RW memclkratio
01SMI
1011
[0] RW reserved 1
4.3 NAND Flash

4.3.1
NANDCNAND Flash Controller NAND Flash

4.3.2
NANDC
z 2KB2048byte+128byte
z 2 1 ready/busy
z 8bit data-bus NAND Flash
z NAND Boot 2KB4KB page size NAND Flash
0 NAND Flash
z ECC
SLC 512byte Hamming ECCError Correcting Code
1bit
MLC 512byte 4/8byte
z ECC
z

4-50 02 (2010-01-19)

Hi3520
4
z NAND Flash
cache
z NAND Flash
z 2 NAND Flash
z NAND Flash
z lock lock-down Flashlock /Flash
/ Flashlock Flash
NANDC
z EDOEnhanced Data Out NAND Flash
4.3.3
NANDC 4-13
4-13 NANDC
I/O
NF_RB I NAND Flash / NF_RB

1
0
NF_CSN0 O 1 NAND Flash NF_CSN0

NF_CSN1 O 2 NAND Flash NF_CSN1

NF_REN O NAND Flash NF_REN

NF_WEN O NAND Flash NF_WEN

NF_CLE O NAND Flash NF_CLE
NF_ALE O NAND Flash NF_ALE
NF_ADNUM[1: I Boot NANDC NAND EBIADR18/EBIA

0] Flash DR17
003
014
105
116

02 (2010-01-19) 4-51

Hi3520
4
I/O
NF_PAGE[1:0] I Boot NAND Flash EBIADR21/EBIA

page DR20
00
012KB
104KB
11
NF_ECC0[1:0] I Boot ECC EBIADR16/EBIA

DR15
00 ECC
011bit
104bit
118bit
1bit
EBI_DQ[7:0] IO NAND Flash EBI_DQ0

8bits NAND Flash EBI_DQ7
8bits
4.3.4
4.3.4.1
2 1 ready/busy NAND Flash
ready_busy NF_RB

4-52 02 (2010-01-19)

Hi3520
4
4-8 NAND Flash Controller
NF_CSN[1:0]
NF_REN
NF_WEN
NAND
NF_CLE Flash
NF_ADNUM[1:0]
NF_ALE
NF_PAGE[1:0]
NF_ECC0[1:0] NF_RB
NANDFlash
Controller
EBI_DQ[7:0]
EBI
EBI
4.3.4.2
NAND Flash block page block
page NAND Flash block
page
NAND Flash
1 NAND Flash 0x00
2 block
NAND Flash
3 0x30NAND Flash RB NAND Flash

25sRB NAND Flash

4 CPU NF_REN NAND Flash
----
NANDC NAND Flash page 4-9

02 (2010-01-19) 4-53

Hi3520
4
4-9 NAND Flash page
NF_CSN0
NF_CLE
NF_ALE
NF_WEN
NF_REN
NF_RB
EBI_DQ[7:0] 00 ad0 ad1 ad2 ad3 ad4 30 data data data data data data
1 NAND Flash 0x80
2 block
NAND Flash
3 NAND Flash
4 CPU 0x10NAND Flash RB

NAND Flash 200msRB
NAND Flash
5 CPU 0x70
----
NANDC 4-10
4-10 NANDC
NF_CSN_0
NF_CLE
NF_ALE
NF_WEN
NF_REN
NF_RB
EBI_DQ[7:0] 80 ad0 ad1 ad2 ad3 data data 10 70 XX

4-54 02 (2010-01-19)

Hi3520
4
4.3.5
NF_RB GPIO3_1 ready_busy

NF_RB
NFCSN1 GPIO3_3 2 IO Config

reg72 NF_CSN1
NAND Flash NANDC
1 NANDC NFC_STATUS[nfc_ready]
2 NFC_STATUS[nfc_ready] 1 NAND Flash 3

1
3 SC_PERDIS[nandcclkdis] 1
----
NFC_OP NANDC NFC_STATUS[nfc_ready] 0

1 NAND Flash SLC Flash
4msMLC 11ms NANDC
SC_PERCTRL10 [nadc_srst] 1 NANDC

NAND Flash NAND Flash

NANDC
Boot
NANDC NAND Boot 2KB4KB page size 0
NAND Flash
NANDC Boot Boot NANDC

Boot NANDC
Boot 4-14

02 (2010-01-19) 4-55

Hi3520
4
4-14 Boot
I/O
NF_NUM[1:0] I Boot NANDC NAND Flash

003
014
105
116
NF_PAGE[1:0] I Boot NAND Flash page

00
012KB
104KB
11
NF_ECC[1:0] I Boot ECC

00 ECC
011bit
104bit
118bit
Boot
NANDC Boot 0 NAND Flash Boot Boot

z CPU 0x00_00000x01_FFFF
128KB
z NAND Flash Boot CPU NANDC NAND
Flash page
z CPU buffer
z NAND Flash Boot

NORMAL
NFC_CON[op_mode] 1 Normal CPU
NAND Flash
NAND Flash
NANDC
NAND Flash CPU

4-56 02 (2010-01-19)

Hi3520
4
NAND Flash Flash

NAND Flash
K9F2G08U0M 256M%8bitpage size 2KB 4-

15 A0A11 A12A27
4-15 K9F2G08U0M
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd cycle A8 A9 A10 A11 0 0 0 0
3rd cycle A12 A13 A14 A15 A16 A17 A18 A19
4th cycle A20 A21 A22 A23 A24 A25 A26 A27
K9GAG08X0M 2G%8bitpage size 4KB 4-

16 A0A12 A13A31
4-16 K9GAG08X0M
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
1st cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd cycle A8 A9 A10 A11 A12 0 0 0
3rd cycle A13 A14 A15 A16 A17 A18 A19 A20
4th cycle A21 A22 A23 A24 A25 A26 A27 A28
5th cylce A29 A30 A31 0 0 0 0 0
Normal NANDC
z NANDC buffer 0x7000_0000
z NANDC 0x1000_0000
NAND Flash NAND Flash

4-17

02 (2010-01-19) 4-57

Hi3520
4
4-17 NAND Flash
1st cycle 2nd cycle
READ 00H 30H -

PROGRAM 80H 10H -
BLOCK ERASE 60H D0H -
READ ID 90H - -
READ STATUS 70H - -
RESET FFH - -
NANDC buffer 2048+128byte NAND Flash NANDC

buffer
z 1bit ECC
512+16byte page size
512byte buffer 0x0000x1FF Spare area
0x7FF0x83F 4-11
2KB204864page size
2048byte buffer 0x0000x7FF 64byte spare
0x8000x80F
byte0byte511 Main Area 0x8000x80F Spare Area

Spare 512+16byte page size 4-12

ECC NAND Flash
Main Area Spare Area 4-13
4KB4096+128page size
4KB page size 4-12

4-58 02 (2010-01-19)

Hi3520
4
4-11 1bit ECC 512+16byte page size NAND Flash
Main Area RSV RSV RSV Spare Area RSV

(512byte) (512byte) (512byte) (512byte) (16byte) (112byte)
ext_data ( byte0byte10 ) S_ECC0 S_ECC1 ECC0 ECC1 ECC2
ECC0ECC1ECC2ECC code for main area data

S_ECC0S_ECC1ECC code for RSVbyte0byte10data
ext_data
4-12 2KB2048+ 64byte page size NAND Flash
Spare Spare Spare Spare

Main Area Main Area Main Area Main Area RSV
Area Area Area Area
(512byte) (512byte) (512byte) (512byte) (64byte)
(16byte) (16byte) (16byte) (16byte)
4-13 Main Area

Main Area Main Area Main Area Main Area
Area Area Area Area
boot 1bit ECC NAND Flash 4-12

z 4bit ECC
2KB204864page size
2048byte buffer 0x0000x7FF 64byte spare
0x8000x83F 4-14
byte0byte511 Main Area byte2048byte2063 Spare Area

ECC NAND Flash
Main Area Spare Area 4-13
4KB(4096+128) page size
4KB page size 4-14

02 (2010-01-19) 4-59

Hi3520
4
4-14 4bit ECC 2KB2048+64byte page size NAND Flash

Area Area Area Area
Spare Area
(16byte)
ext_data ( byte0byte5 ) ECC CODE(byte6byte15)
z 8bit ECC
NANDC buffer 2048+26%4byte 4KB
page size 4-15
ECC NAND Flash Main
Area Spare Area 4-13
4096+218byte208218
10 byte
4-15 8bit ECC 2048+26%4byte page size NAND Flash

Area Area Area Area
Spare Area
(26byte)
ext_data ( byte0byte5 ) ECC CODE(byte6byte25)

4-60 02 (2010-01-19)

Hi3520
4
1 NFC_CON[op_mode] 1 Normal page size

NFC_CON[page_size] ready_busy
NFC_CON[ecc_type]
2 NFC_PWIDTH
3 NFC_INTEN
op_done
----
NAND Flash

1 NFC_ADDRL NFC_ADDRH page NFC_CMD

0x0070_D060
2 NFC_OP 0x369 NANDC NAND Flash

NAND Flash 3 0
3 NFC_STATUS[nfc_ready] 1 4
NFC_INTS[op_done] 1 4
4 NFC_STATUS[nf_status]
----
4KB page size NAND Flash

1 CPU 4KB 2048byte main 104byte spare

NANDC buffer ecc_type 2b00 NFC_DATA_NUM

2 CPU NFC_ADDRL NFC_ADDRH NAND Flash page

NFC_CMD 0x0070_1080
3 CPU NFC_OP 0x570 NANDC NAND Flash

NAND Flash 5 0
NFC_INTS[op_done] op_done 5
5 CPU 4K 2048byte main 104byte spare

NANDC buffer NFC_OP 0x0d NANDC NAND Flash

7 CPU NFC_STATUS[nf_status]
----

02 (2010-01-19) 4-61

Hi3520
4
4KB page size NAND Flash page

1 CPU NFC_ADDRL NFC_ADDRH NAND Flash page

NFC_CMD 0x3000 ecc_type 2b00
NFC_DATA_NUM
2 CPU NFC_OP 0x56E NAND Flash 5

0 NANDC
4 CPU NFC_STATUS
5 CPU NANDC buffer
6 CPU NFC_OP 0x02 NANDC 4K pagesize

8 CPU NFC_STATUS
9 CPU NANDC buffer
----

z NAND Flash
NFC_CMD NAND Flash
NFC_OP address_cycles
NFC_PWIDTH
NFC_OPIDLE
z buffer NFC_OP NANDC
Flash NANDC Flash

z NFC_OP NAND Flash NFC_STATUS[nfc_ready]
0 NANDC buffer
4.3.6 NANDC
NANDC 4-18

4-62 02 (2010-01-19)

Hi3520
4
4-18 NANDC 0x1000_0000
0x00 NFC_CON NANDC 4-64
0x04 NFC_PWIDTH 4-65
0x08 NFC_OPIDLE 4-66
0x0C NFC_CMD 4-66
0x10 NFC_ADDRL 4-67
0x14 NFC_ADDRH 4-67
0x18 NFC_DATA_NUM 4-68
0x1C NFC_OP 4-69
0x20 NFC_STATUS 4-70
0x24 NFC_INTEN 4-71
0x28 NFC_INTS 4-73
0x2C NFC_INTCLR 4-74
0x30 NFC_LOCK 4-76
0x34 NFC_LOCK_SA0 0 4-77
0x3C NFC_LOCK_SA2 2 4-78
0x44 NFC_LOCK_EA0 0 4-79
0x4C NFC_LOCK_EA2 2 4-81
0x54 NFC_EXPCMD 4-82
0x58 NFC_EXBCMD 4-82
0x5C NFC_ECC_TEST ECC 4-83

02 (2010-01-19) 4-63

Hi3520
4
4.3.7 NANDC
NFC_CON
NFC_CON NANDC

0x00 NFC_CON -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ext_data_ecc_en
protection_en
op_mode
ecc_type
pagesize
reserved
edo_en
ecc_en
cs_ctrl
rb_sel
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 1 0 1 ? ? 0 0 0
[31:13] - reserved
EDO NAND Flash

0
[12] RW edo_en
1EDO

ECC
00 ECC
011bit ECC
[11:10] RW ecc_type
104bit ECC
118bit ECC
EBIADR16/EBIADR15

0
[9] RW ext_data_ecc_en
1
ecc_en 1

[8] RW protection_en 0
1
[7] - reserved

4-64 02 (2010-01-19)

Hi3520
4

0 NAND Flash busy 0
[6] RW cs_ctrl
1 NAND Flash busy 1
NAND Flash cs do not care
ECC
[5] RW ecc_en 0
1
[4:3] - reserved
NAND Flash
00
012KB
[2:1] RW pagesize
104KB
11
NFC_PAGE_SIZE
NANDC
[0] RW op_mode 0NANDC Boot
1NANDC NORMAL
NFC_PWIDTH
NFC_PWIDTH

0x04 NFC_PWIDTH -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved rw_hcnt r_lcnt w_lcnt
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 0 1 0 1 0 1 0 1 0 1
[31:12] - reserved
NAND Flash /
[11:8] RW rw_hcnt
0x00xF116
NAND Flash
[7:4] RW r_lcnt
0x00xF116
NAND Flash
[3:0] RW w_lcnt
0x00xF116

02 (2010-01-19) 4-65

Hi3520
4
NFC_OPIDLE
NFC_OPIDLE

0x08 NFC_OPIDLE -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
write_data_wait
Name reserved frb_wait cmd1_wait addr_wait cmd2_wait frb_idle
Reset ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[31:24] - reserved
ready
[23:20] RW frb_wait
frb_wait%8
Command1
[19:16] RW cmd1_wait
0x00xF116
Address
[15:12] RW addr_wait
0x00xF116

[11:8] RW write_data_wait
0x00xF116
Command2
[7:4] RW cmd2_wait
0x00xF116
NAND Flash ready ,

[3:0] RW frb_idle
frb_idle%8
NFC_CMD
NFC_CMD

4-66 02 (2010-01-19)

Hi3520
4

0x0C NFC_CMD -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved read_status_cmd cmd2 cmd1
Reset ? ? ? ? ? ? ? ? 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW read_status_cmd Read status
[15:8] RW cmd2 NANDC NAND Flash 2
[7:0] RW cmd1 NANDC NAND Flash 1
NFC_ADDRL
NFC_ADDRL

0x10 NFC_ADDRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name addr_l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW addr_l NAND Flash 32bit
NFC_ADDRH
NFC_ADDRH

0x14 NFC_ADDRH -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved addr_h
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved

02 (2010-01-19) 4-67

Hi3520
4
[15:0] RW addr_h NAND Flash 16bit
NFC_DATA_NUM
NFC_DATA_NUM

0x18 NFC_DATA_NUM -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved nfc_data_num
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0 0 0 1 0 0 0 0 0 0
[31:12] - reserved
NANDC 2152byte
[11:0] RW nfc_data_num 2048+26%4
ecc_type 00

4-68 02 (2010-01-19)

Hi3520
4
NFC_OP
NFC_OP

0x1C NFC_OP -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
address_cycles
read_status_en
wait_ready_en
write_data_en
read_data_en
cmd1_en
cmd2_en
addr_en
nf_cs
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0
[31:12] - reserved
NAND Flash
[11:9] RW address_cycles EBIADR18/EBIADR17
EBIADR18/EBIADR17 3
NAND Flash
00cs0
[8:7] RW nf_cs
01cs1

Command1
[6] RW cmd1_en 0
1
NAND Flash
[5] RW addr_en 0
1
NAND Flash
0
[4] RW write_data_en
1
read_data_en write_data_en 1
Command2
[3] RW cmd2_en 0
1

02 (2010-01-19) 4-69

Hi3520
4
ready/busy
[2] RW wait_ready_en 0
1
NAND Flash
0
[1] RW read_data_en
1
read_data_en write_data_en 1
1 NAND status 0x70

NAND Flash NANDC
NFC_STATUS buffer
NAND
[0] RW read_status_en
CPU
NAND
CPU
read_data_en 1
NFC_STATUS
NFC_STATUS

0x20 NFC_STATUS -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nfc_ready
reserved
reserved
ready
Name ecc_num nf_status
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0
ecc_type 10 11 sector
ext_dta_ecc_en 1 6 byte bit

bit[3:0]sector_0
bit[7:4]sector_1
[31:16] RO ecc_num
bit[11:8]sector_2
bit[15:12]sector_3
ecc_type=01 sector ext_data

bit[1:0]sector_0

4-70 02 (2010-01-19)

Hi3520
4
bit[3:2]sector_1
bit[5:4]sector_2
bit[7:6]sector_3
bit[9:8]ext_data_0
bit[11:10]ext_data_1

00
01 1bit
10
112bit 2bit
[15:13] - reserved
NAND Flash status

[12:5] RO nf_status NFC_OP read_status 1
nfc_ready 1
[4:2] - reserved
[1] RO ready NAND Flash ready/busy
NANDC ready/busy
0NANDC
[0] RO nfc_ready
1
NFC_OP NANDC
NFC_INTEN
NFC_INTEN

02 (2010-01-19) 4-71

Hi3520
4

0x24 NFC_INTEN -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wr_buf_busy_int_en
wr_buf_err_int_en
cs1_done_en
cs0_done_en
op_done_en
err_invalid
err_valid
reserved
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0
[31:9] - reserved
lock
[8] RW wr_buf_err_int_en 0
1
NANDC NAND Flash CPU NANDC

wr_buf_busy_int_e buffer
[7] RW
n 0
1
[6] RW err_invalid
[5] RW err_valid
[4:3] - reserved
ready busy
[2] RW cs1_done_en 0
1
ready busy
[1] RW cs0_done_en 0
1
NANDC
[0] RW op_done_en 0
1

4-72 02 (2010-01-19)

Hi3520
4
NFC_INTS
NFC_INTS

0x28 NFC_INTS -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wr_buf_busy_int
wr_buf_err_int
err_invalid
err_vavid
cs1_done
cs0_done
op_done
reserved
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0
[31:9] - reserved
lock
[8] RO wr_buf_err_int 0
1
NANDC NAND Flash CPU

NANDC buffer
[7] RO wr_buf_busy_int
0
1

0
1
1bit 512byte 2bit
[6] RO err_invalid
4bit 512byte 5bit

8bit 512byte 8bit

02 (2010-01-19) 4-73

Hi3520
4

0
1
1bit 512byte 1bit
[5] RO err_vavid
4bit 512byte 1bit4bit

8bit 512byte 1bit8bit

[4:3] - reserved
ready/busy
[2] RO cs1_done 0
1
ready busy
[1] RO cs0_done 0
1
NANC
0
[0] RO op_done
1
NFC_OP
NFC_INTCLR
NFC_INTCLR

0x2C NFC_INTCLR -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wr_buf_busy_int_clr
wr_buf_err_int_clr
r_5bit_err_clr
r_4bit_err_clr
cs1_done_clr
cs0_done_clr
op_done_clr
reserved
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0

4-74 02 (2010-01-19)

Hi3520
4
[31:9] - reserved
wr_buf_err_int
[8] WO wr_buf_err_int_clr 0
1
wr_buf_busy_int
wr_buf_busy_int_c
[7] WO 0
lr
1
r_5bit_err
[6] WO r_5bit_err_clr 0
1
r_4bit_err
[5] WO r_4bit_err_clr 0
1
[4:3] - reserved
cs1_done
[2] WO cs1_done_clr 0
1
cs0_done
[1] WO cs0_done_clr 0
1
op_done
[0] WO op_done_clr 0
1

02 (2010-01-19) 4-75

Hi3520
4
NFC_LOCK
NFC_LOCK

0x30 NFC_LOCK -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
lock_excmd_en
global_lock_en
lock_down
lock_en
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
[31:4] - reserved

[3] RW lock_excmd_en
0
1
Flash lock 1

[2] RW lock_en
0
1
Flash lock 1 NAND Flash

[1] RW global_lock_en
0
1
NAND Flash lock

0lock
[0] RW lock_down
1lock_down 1 reset
0

4-76 02 (2010-01-19)

Hi3520
4
NFC_LOCK_SA0
NFC_LOCK_SA0 0

0x34 NFC_LOCK_SA0 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Name reserved flash_lock_addr0
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
NAND Flash
00 0
[20:19] RW flash_lock_cs
01 1

[18:0] RW flash_lock_addr0 0 NAND Flash 5
NFC_LOCK_SA1
NFC_LOCK_SA1 1

0x38 NFC_LOCK_SA1 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved

02 (2010-01-19) 4-77

Hi3520
4
NAND Flash
00 0
01 1

NFC_LOCK_SA2
NFC_LOCK_SA2 2

0x3C NFC_LOCK_SA2 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
NAND Flash
00 0
01 1


4-78 02 (2010-01-19)

Hi3520
4
NFC_LOCK_SA3
NFC_LOCK_SA3 3

0x40 NFC_LOCK_SA3 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
NAND Flash
00 0
01 1

NFC_LOCK_EA0
NFC_LOCK_EA0 0

0x44 NFC_LOCK_EA0 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Name reserved flash_lock_eaddr0
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved

02 (2010-01-19) 4-79

Hi3520
4
NAND Flash
00 0
01 1

[18:0] RW flash_lock_eaddr0 0 NAND Flash 5
NFC_LOCK_EA1
NFC_LOCK_EA1 1

0x48 NFC_LOCK_EA1 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
NAND Flash
00 0
01 1


4-80 02 (2010-01-19)

Hi3520
4
NFC_LOCK_EA2
NFC_LOCK_EA2 2

0x4C NFC_LOCK_EA2 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
NAND Flash
00 0
01 1

NFC_LOCK_EA3
NFC_LOCK_EA3 3

0x50 NFC_LOCK_EA3 -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
flash_lock_cs
Reset ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved

02 (2010-01-19) 4-81

Hi3520
4
NAND Flash
00 0
01 1

NFC_EXPCMD
NFC_EXPCMD

0x54 NFC_EXPCMD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ex_pcmd3 ex_pcmd2 ex_pcmd1 ex_pcmd0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] RW ex_pcmd3 NAND Flash 3
NFC_EXBCMD
NFC_EXBCMD

0x58 NFC_EXBCMD -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved ex_bcmd1 ex_bcmd0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:8] RW ex_bcmd1 NAND Flash 1
[7:0] RW ex_bcmd0 NAND Flash 0

4-82 02 (2010-01-19)

Hi3520
4
NFC_ECC_TEST
NFC_ECC_TEST ECC

0x5C NFC_ECC_TEST 0x0020_F001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ecc_mask
dec_only
enc_only
Name version empty reserved
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1
[31:16] RO version NANDC
NANDC FIFO empty

bit[15]ECC8 FIFO empty
[15:12] RO empty bit[14]ECC FIFO empty
bit[13] NAND Flash FIFO empty
bit[12] NAND Flash FIFO empty
[11:3] - reserved
ECC
0 ecc_type
[2] RW ecc_mask
1 ecc NAND Flash
ecc_type

[1] RW dec_only 1 ECC NAND
Flash 0
[0] RW enc_only 1 ECC NAND

Flash 1 ECC
0

02 (2010-01-19) 4-83

Hi3520
5 GMAC
5 GMAC
5.1
GMACGigibit Media Access ControlGMAC
10Mbit/s100Mbit/s 1000Mbit/s
MII/RGMII GMAC MAC/
/

5.2
GMAC
z MII 10Mbit/s 100Mbit/s
z RGMII 10Mbit/s100Mbit/s 1000Mbit/s
z MII/RGMII
z MII
z
z CRC
z 64byte 64byte
z
z 2.5MHz/18MHz MDIO
z
z 8KB 4KB
z
z
z
z 2
z

02 (2010-01-19) 5-1

Hi3520
5 GMAC
5.3
5-1
5-1
PHY_RXC I MIIMII 100M/10M GRCLK

25MHz 2.5MHz
RGMIIRGMII
1000M/100M/10M
125MHz25MHz 2.5MHz
PHY_RXD[3:0] I MIIMII GRXD0

PHY_RXD[3:0] GRXD3
RGMIIRGMII
PHY_RXD[3:0]
PHY_RXDV I MIIMII GRXDV

RGMIIRGMII
PHY_COL I MIIMII GCOL

RGMIIRGMII
GPIO
PHY_CRS I MIIMII GCRS

RGMIIRGMII
GPIO
PHY_TXC I MIIMII 100M/10M GTCLK

25MHz 2.5MHz
RGMII
PHY_GTXC O MII GTCLKOUT

RGMIIRGMII
1000M/100M/10M
125MHz25MHz 2.5MHz
GPIO
PHY_TXEN O MIIMII GTXEN

RGMIIRGMII

5-2 02 (2010-01-19)

Hi3520
5 GMAC
PHY_TXD[3:0] O MIIMII GTXD0

PHY_TXD[3:0] GTXD3
RGMIIRGMII
PHY_TXD[3:0]
FE_MDC O MIIMDIO 2.5MHz MDCK

18MHz
RGMII MII
FE_MDIO I/O MIIMDIO MDIO

RGMII MII
5.4
5.4.1
5-1
5-1
MII/RGMII TX
PHY GMAC
MII/RGMII RX
MDIO MDC
MDIO MDIODATA
5.4.2
GMAC Ethernet II Ethernet II 5-2
5-2 Ethernet II
DA SA Etype Data FCS

02 (2010-01-19) 5-3

Hi3520
5 GMAC
Ethernet II 5-2
5-2 Ethernet II
byte
DA 6 MAC
SA 6 MAC
Etype 2 Ethernet 0x05DD
Data 461500 Ethernet PAD
FCS 4 CRC
5.4.3 GMAC
CPU FIFO GMAC
z GMAC
CPU FIFO
z GMAC CPU FIFO

5-3
5-3
SDRAM

SRAM
GE/FE GMAC FIFO CPU
FIFO
GEGigibit Ethernet
FEFast Ethernet
FIFO
FIFO FIFO 512%43bit
FIFO
CRF_RX_BASE_ADDR bit[8:0] FIFO

5-4 02 (2010-01-19)

Hi3520
5 GMAC
FIFO =512 FIFO
0
FIFO CRF_FIFO_CLR 0x0274

FIFO
FIFO 5-4
5-4 FIFO
32bit
Address 1
Address 2
Address N
FIFO SDRAM 32bitCPU

GMAC
FIFO
FIFO 5-5
5-5 FIFO
bit[42:11] bit[10:0]
Address 1 Length 1
Address 2 Length 2
Address N Length N
FIFO 43bit GMAC

CPU CPU GMAC

z Address SDRAM bit[31:0] 32bit

02 (2010-01-19) 5-5

Hi3520
5 GMAC
z Length11 142000byte 0
1.6KB 1.6KB
1600byte+128byte GMAC

SDRAM
GMAC FIFO
SDRAM GMAC SDRAM 5-6
5-6 SDRAM

16bit 16bit
Addr n
N byte
SDRAM
CPU 5-7 SDRAM
SDRAM 5-7
5-7 SDRAM

16bit 16bit
Addr
N byte
5.4.4 GMAC
GMAC

GMAC 3
z

5-6 02 (2010-01-19)

Hi3520
5 GMAC
z IP
z
T
T 125s

z CONTROL_WORD bit[20] 1
z FLOW_CTRL_PKG_THRSLD bit[15:0]
z CRF_FLOW_TIME_THRSLD bit[7:0]
IP
IP IP
z CONTROL_WORD bit[21] 1 IP
z FLOW_CTRL_PKG_THRSLD bit[31:16] IP
z CRF_FLOW_TIME_THRSLD bit[7:0]
1s

z CONTROL_WORD bit[16] 1
z CRF_BM_PKT_THRSLD
z CRF_BM_TIME_THRSLD
5.4.5 GMAC
CRF_INTRPT_THRSLD

z GMAC SDRAM

z GMAC

02 (2010-01-19) 5-7

Hi3520
5 GMAC
0
CRF_INTRPT_CLR[rx_crf_intrpt] 1
CPU CRF_INTRPT_CLR bit[18] 1

0 CRF_INTRPT_CLR bit[18] 0
5.4.6 GMAC
GMAC
2 MAC IP Protocol

z 4
CRF_CTRL_0_TYPECRF_CTRL_3_TYPE

z MAC IP
Protocol FILTER_LIST0FILTER_LIST15
IP IP Protocol
5.5
5.5.1 GMAC PHY
GMAC MDIO PHY MDIO
1 CPU MDIO MDIO_SINGLE_CMD bit[9:8] PHY

MDIO_SINGLE_CMD bit[4:0] PHY
MDIO_SINGLE_CMD bit[20] 1 MDIO_SINGLE_CMD bit[17:16] 10
MDIO
2 MDIO PHY MDIO

MDIO_SINGLE_DATA bit[31:16] MDIO_SINGLE_CMD bit[20] 0
3 CPU MDIO_SINGLE_DATA bit[31:16] MDIO PHY

----
z MDIO_SINGLE_CMD bit[20] 0 PHY

PHY
z PHY PHY

5-8 02 (2010-01-19)

Hi3520
5 GMAC
1 CPU PHY MDIO_SINGLE_DATA bit[15:0]
2 MDIO_SINGLE_CMD bit[9:8] PHY MDIO_SINGLE_CMD bit[4:0]

PHY MDIO_SINGLE_CMD bit[20] 1
MDIO_SINGLE_CMD bit[17:16] 01 MDIO
3 MDIO MDIO_SINGLE_DATA bit[15:0] PHY

MDIO MDIO_SINGLE_CMD bit[20] 0
----
5.5.2 GMAC
GMAC
GMAC
GMAC CPU SDRAM

1 5.4.5 GMAC
2 FIFO CRF_CFF_DATA_NUM
z FIFO FIFO
0x1009_0480 5-4
3
z
3 GMAC 5-6
SDRAM CPU

----
GMAC
GMAC CPU FIFOGMAC FIFO
SDRAM
1 CPU SDRAM 5-7
CONTROL_WORD bit[22] 0 5-7

2 CPU FIFO FIFO

CRF_CFF_DATA_NUM

02 (2010-01-19) 5-9

Hi3520
5 GMAC
z FIFO 0x1009_0400
0x1009_0580 5-5 3
z
3 GMAC
----
5.6 GMAC
GMAC 5-3
5-3 GMAC 0x1009_0000
0x0000 STATION_ADDR_L MAC 32bit 5-16

OW
0x0004 STATION_ADDR_H MAC 16bit 5-16
IGH
0x000C FD_FC_TYPE 5-17
0x001C FC_TX_TIMER 5-17
0x0020 FD_FC_ADDR_LO 32bit 5-18

W
0x0024 FD_FC_ADDR_HIG 16bit 5-18
H
0x0030 IPG_TX_TIMER 5-19
0x0038 PAUSE_THR 5-19
0x003C MAX_FRM_SIZE 5-20
0x0040 PORT_MODE 5-21
0x0044 PORT_EN 5-21
0x0048 PAUSE_EN 5-22
0x0050 SHORT_RUNTS_TH 5-22

R
0x0054 DROP_UNK_CTL_F 5-23
RM
0x0060 TRANSMIT_CONT 5-23
ROL
0x0064 REC_FILT_CONTR 5-24
OL

5-10 02 (2010-01-19)

Hi3520
5 GMAC
0x0068 PORT_MC_ADDR_ 32bit 5-25

LOW
0x006C PORT_MC_ADDR_ 16bit 5-25
HIGH
0x0080 RX_OCTETS_TOTA 5-26
L_OK
0x0084 RX_OCTETS_BAD 5-26
0x0088 RX_UC_PKTS MAC 5-26
0x008C RX_MC_PKTS 5-27
0x0090 RX_BC_PKTS 5-27
0x0094 RX_PKTS_64OCTE 64byte 5-28

TS
0x0098 RX_PKTS_65TO127 65byte127byte 5-28
OCTETS
0x009C RX_PKTS_128TO25 128byte255byte 5-28

5OCTETS
0x00A0 RX_PKTS_256TO51 256byte511byte 5-29

1OCTETS

23OCTETS

518OCTETS
0x00AC RX_PKTS_1519TO 1519byte 5-30

MAXOCTETS
0x00B0 RX_FCS_ERRORS CRC 5-30
0x00B4 RX_TAGGED TAG 5-31
0x00B8 RX_DATA_ERR 5-31
0x00BC RX_ALIGN_ERROR 5-32

S
0x00C0 RX_LONG_ERROR 5-32

S CRC
0x00C4 RX_JABBER_ERRO 5-32

RS CRC byte

02 (2010-01-19) 5-11

Hi3520
5 GMAC
0x00C8 RX_PAUSE_MACC 5-33

ONTROL_FRAMCO
UNTER
0x00CC RX_UNKNOWN_M MAC 5-33
ACCONTROL_FRA
MCOUNTER
0x00D0 RX_VERY_LONG_ 5-34
ERR_CNT
0x00D4 RX_RUNT_ERR_CN 64byte 12byte 5-34
T
0x00D8 RX_SHORT_ERR_C 96bit 5-35

NT
0x0100 OCTETS_TRANSMI 5-35
TTED_OK
0x0104 OCTETS_TRANSMI 5-35
TTED_BAD
0x0108 TX_UC_PKTS 5-36
0x010C TX_MC_PKTS 5-36
0x0110 TX_BC_PKTS 5-37
0x0114 TX_PKTS_64OCTE 64byte 5-37

TS
0x0118 TX_PKTS_65TO127 65byte127byte 5-37
OCTETS
0x011C TX_PKTS_128TO25 128byte255byte 5-38

5OCTETS

1OCTETS

23OCTETS

518OCTETS
0x012C TX_PKTS_1519TO 1519byte 5-39

MAXOCTETS
0x014C TX_EXCESSIVE_LE 5-40

NGTH_DROP
0x0150 TX_UNDERRUN 5-40

5-12 02 (2010-01-19)

Hi3520
5 GMAC
0x0158 TX_CRC_ERROR CRC 5-40

0x015C TX_PAUSE_FRAME PAUSE 5-41

S
0x01A8 LINE_LOOP_BACK MAC 5-41
0x01B0 CF_CRC_STRIP CRC 5-42
0x01B4 MODE_CHANGE_E 5-43

N
0x01DC LOOP_REG 5-43
0x01E0 RECV_CONTROL 5-44
0x01EC RX_OVERRUN_CN FIFO 5-44

T
0x01F4 RX_LENGTHFIELD PAD 5-45
_ERR_CNT
0x0200 MAC_SA_ADDR_L MAC 32bit 5-45
0x0204 MAC_SA_ADDR_H MAC 16bit 5-46
0x0208 MAC_DA_ADDR_L MAC 32bit 5-46
0x020C MAC_DA_ADDR_H MAC 16bit 5-47
0x0214 CONTROL_WORD 5-47
0x0218 FLOW_CTRL_PKG_ 5-49

THRSLD
0x021C CRF_FLOW_TIME_ 5-49
THRSLD
0x0220 FILTER_LIST0 0 5-50
0x022C FILTER_LIST3 3 5-52

02 (2010-01-19) 5-13

Hi3520
5 GMAC
0x0248 FILTER_LIST10 10 5-59
0x0250 FILTER_LIST12 12 5-61
0x0254 FILTER_LIST13 13 5-62
0x0258 FILTER_LIST14 14 5-63
0x0264 CRF_TX_FIFO_THR FIFO 5-65

SLD
0x0268 CRF_RX_FIFO_THR FIFO 5-66
SLD
0x026C CRF_RX_BASE_AD FIFO 5-66
DR
0x0270 CRF_INTRPT_THRS 5-67
LD
0x0274 CRF_FIFO_CLR FIFO 5-68
0x027C CRF_INTRPT_CLR 5-69
0x0280 ERR_GIVEN_PKG_ MAC 5-70

CNT
0x0288 ERR_FRM_TYPE_C 5-70

NT
0x028C ERR_IP_TYPE_CNT IP 5-70

0x0294 OVER_FLOW_CNT FIFO 5-71

0x0298 OVER_LENGTH_C 5-71

NT
0x02A8 CRF_CFF_DATA_N FIFO 5-72

UM
0x02AC FLOW_OUT_IP_CN IP 5-72
T
0x02B0 FLOW_OUT_CTRL_ 5-72
CNT
0x02B4 IP_CHK_ERR_CNT IP 5-73

5-14 02 (2010-01-19)

Hi3520
5 GMAC
0x02B8 UDP_CHK_ERR_CN UDP 5-73

T
0x02BC TX_RUNT_ERR_PK FIFO 5-74
G_CNT
0x02C0 RX_ERR_TOTAL_C 5-74

NT
0x02C8 RX_TRANS_PKG_C 5-74
NT
0x02CC TX_TRANS_PKG_C 5-75
NT
0x02D0 RX_BM_OVERFLO 5-75
W
0x02D4 TX_ADDR_OVERF CPU FIFO 5-75

LOW
0x02D8 RX_ADDR_OVERF CPU FIFO 5-76
LOW
0x0340 CRF_TX_PAUSE 5-76
0x0344 CRF_RX_ADDR_N 5-77

UM
0x0348 CRF_CTRL_0_TYPE 0 5-77
0x034C CRF_CTRL_1_TYPE 1 5-78
0x0358 CRF_BM_PKT_THR 5-79

SLD
0x035C CRF_BM_TIME_TH 5-80

RSLD
0x03C0 MDIO_SINGLE_CM MDIO 5-80
D
0x03C4 MDIO_SINGLE_DA MDIO 5-81
TA
0x03CC MDIO_CTL MDIO 5-82
0x03D0 MDIO_RDATA_ST MDIO 5-83

ATUS
0x0400+m TX_CFF_LEN 5-83
0x4

02 (2010-01-19) 5-15

Hi3520
5 GMAC
0x0580+m TX_CFF_ADDR 5-83

0x4
0x0480+n RX_CFF_ADDR 5-84
0x4
GMAC 5-4
5-4 GMAC
m 031 FIFO 32
n 031 FIFO 32
5.7 GMAC
STATION_ADDR_LOW
STATION_ADDR_LOW MAC 32bit

0x0000 STATION_ADDR_LOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name station_addr_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW station_addr_low MAC_CORE MAC 32bit
STATION_ADDR_HIGH
STATION_ADDR_HIGH MAC 16bit

5-16 02 (2010-01-19)

Hi3520
5 GMAC
PMU MAC MAC_SA_ADDR_H/ MAC_SA_ADDR_L MAC

MAC STATION_ADDR_HIGH/ STATION_ADDR_LOW


0x0004 STATION_ADDR_HIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden station_addr_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
[15:0] RW station_addr_high MAC_CORE MAC 16bit
FD_FC_TYPE
FD_FC_TYPE

0x000C FD_FC_TYPE 0x0000_8808
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden fd_fc_type
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
[31:16] - forbidden
[15:0] RW fd_fc_type TYPE
FC_TX_TIMER
FC_TX_TIMER

02 (2010-01-19) 5-17

Hi3520
5 GMAC

0x001C FC_TX_TIMER 0x0000_00FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden fc_tx_timer
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[31:16] - forbidden
512bit
[15:0] RW fc_tx_timer 128 TXC25MHz
64 TXC125MHz
FD_FC_ADDR_LOW
FD_FC_ADDR_LOW 32bit

0x0020 FD_FC_ADDR_LOW 0xC200_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name fd_fc_addr_low
Reset 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
DA 32bit
[31:0] RW fd_fc_addr_low

FD_FC_ADDR_HIGH
FD_FC_ADDR_HIGH 16bit

5-18 02 (2010-01-19)

Hi3520
5 GMAC

0x0024 FD_FC_ADDR_HIGH 0x0000_0180
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden fd_fc_addr_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
[31:16] - forbidden
DA 16bit
[15:0] RW fd_fc_addr_high

IPG_TX_TIMER
IPG_TX_TIMER

0x0030 IPG_TX_TIMER 0x0000_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden ipg_tx_timer
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
[31:8] - forbidden
byte
[7:0] RW ipg_tx_timer

PAUSE_THR
PAUSE_THR

02 (2010-01-19) 5-19

Hi3520
5 GMAC

0x0038 PAUSE_THR 0x0000_002F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden pause_thr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1
[31:16] - forbidden
MAC
512bit
[15:0] RW pause_thr
128 TXC25MHz
64 TXC125MHz
MAX_FRM_SIZE
MAX_FRM_SIZE
max_frm_size PMU CONTROL_WORD[crf_large_packet]


0x003C MAX_FRM_SIZE 0x0000_05EE
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden max_frm_size
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0
[31:14] - forbidden
MAC Byte

[13:0] RW max_frm_size

5-20 02 (2010-01-19)

Hi3520
5 GMAC
PORT_MODE
PORT_MODE

0x0040 PORT_MODE 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
port_mode
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:3] - forbidden
MAC
00010Mbit/s MII
001100Mbit/s MII
0101000Mbit/s GMII
[2:0] RW port_mode
01110Mbit/s RGMII
100100Mbit/s RGMII
1011000Mbit/s RGMII

PORT_EN
PORT_EN

0x0044 PORT_EN 0x0000_0006
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
forbidden
rx_en
tx_en
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
[31:3] - forbidden

02 (2010-01-19) 5-21

Hi3520
5 GMAC

[2] RW tx_en 0
1

[1] RW rx_en 0
1
[0] - forbidden
PAUSE_EN
PAUSE_EN

0x0048 PAUSE_EN 0x0000_0007
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rx_fdfc
tx_fdfc
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
[31:2] - forbidden

[1] RW tx_fdfc 0
1

[0] RW rx_fdfc 0
1
SHORT_RUNTS_THR
SHORT_RUNTS_THR

5-22 02 (2010-01-19)

Hi3520
5 GMAC

0x0050 SHORT_RUNTS_THR 0x0000_000C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden short_runts_thr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
[31:5] - forbidden

[4:0] RW short_runts_thr
byte
DROP_UNK_CTL_FRM
DROP_UNK_CTL_FRM

0x0054 DROP_UNK_CTL_FRM 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
drop_unk_ctl_frm
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] - forbidden

[0] RW drop_unk_ctl_frm 0
1
TRANSMIT_CONTROL
TRANSMIT_CONTROL

02 (2010-01-19) 5-23

Hi3520
5 GMAC

0x0060 TRANSMIT_CONTROL 0x0000_00D0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pad_enab
crc_add
Name forbidden forbidden
le
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0
[31:8] - forbidden
PAD
0
[7] RW pad_enable
1
PAD FCS
FCS
[6] RW crc_add 0
1
[5:0] - forbidden
REC_FILT_CONTROL
REC_FILT_CONTROL

0x0064 REC_FILT_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mc_match_en
uc_match_en
crc_err_pass
bc_drop_en
forbidden
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] - forbidden
CRC
[5] RW crc_err_pass 0
1

5-24 02 (2010-01-19)

Hi3520
5 GMAC
[4:3] - forbidden

[2] RW bc_drop_en 0
1
DA
[1] RW mc_match_en 0
1
DA
[0] RW uc_match_en 0
1
PORT_MC_ADDR_LOW
PORT_MC_ADDR_LOW 32bit

0x0068 PORT_MC_ADDR_LOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name port_mc_addr_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW port_mc_addr_low 32bit
PORT_MC_ADDR_HIGH
PORT_MC_ADDR_HIGH 16bit

0x006C PORT_MC_ADDR_HIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden port_mc_addr_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden

02 (2010-01-19) 5-25

Hi3520
5 GMAC
[15:0] RW port_mc_addr_high 16bit
RX_OCTETS_TOTAL_OK
RX_OCTETS_TOTAL_OK

0x0080 RX_OCTETS_TOTAL_OK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_octets_total_ok
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_octets_total_ok
RX_OCTETS_BAD
RX_OCTETS_BAD

0x0084 RX_OCTETS_BAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_octets_bad
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_octets_bad CRC
RX_UC_PKTS
RX_UC_PKTS MAC

5-26 02 (2010-01-19)

Hi3520
5 GMAC

0x0088 RX_UC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_uc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_uc_pkts bad
RX_MC_PKTS
RX_MC_PKTS

0x008C RX_MC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_mc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_mc_pkts bad
RX_BC_PKTS
RX_BC_PKTS

0x0090 RX_BC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_bc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_bc_pkts bad

02 (2010-01-19) 5-27

Hi3520
5 GMAC
RX_PKTS_64OCTETS
RX_PKTS_64OCTETS 64byte

0x0094 RX_PKTS_64OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_pkts_64octets
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_pkts_64octets 64byte bad
RX_PKTS_65TO127OCTETS
RX_PKTS_65TO127OCTETS 65byte127byte

0x0098 RX_PKTS_65TO127OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_pkts_65to127octets
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_65to127oct
[31:0] RC 65byte127byte bad
ets

5-28 02 (2010-01-19)

Hi3520
5 GMAC

0x009C RX_PKTS_128TO255OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_128to255o
ctets

0x00A0 RX_PKTS_255TO511OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_256to511o
ctets


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_512to1023
octets

02 (2010-01-19) 5-29

Hi3520
5 GMAC


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_1024to151
8octets
RX_PKTS_1519TOMAXOCTETS
RX_PKTS_1519TOMAXOCTETS 1519byte


0x00AC RX_PKTS_1519TOMAXOCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_pkts_1519tomaxoctes
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pkts_1519tomax
[31:0] RC 1519byte byte bad
octes
RX_FCS_ERRORS
RX_FCS_ERRORS CRC

5-30 02 (2010-01-19)

Hi3520
5 GMAC

0x00B0 RX_FCS_ERRORS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_fcs_errors
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_fcs_errors CRC
RX_TAGGED
RX_TAGGED TAG

0x00B4 RX_TAGGED 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_tagged
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_tagged TAG
RX_DATA_ERR
RX_DATA_ERR

0x00B8 RX_DATA_ERR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_data_err
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_data_err

02 (2010-01-19) 5-31

Hi3520
5 GMAC
RX_ALIGN_ERRORS
RX_ALIGN_ERRORS

0x00BC RX_ALIGN_ERRORS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_align_errors
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_align_errors
RX_LONG_ERRORS
RX_LONG_ERRORS CRC


0x00C0 RX_LONG_ERRORS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_long_errors
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_long_errors CRC
RX_JABBER_ERRORS
RX_JABBER_ERRORS CRC byte

5-32 02 (2010-01-19)

Hi3520
5 GMAC

0x00C4 RX_JABBER_ERRORS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_jabber_errors
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRC byte
[31:0] RC rx_jabber_errors
nibble
RX_PAUSE_MACCONTROL_FRAMCOUNTER
RX_PAUSE_MACCONTROL_FRAMCOUNTER
Register Name
Offset Address Total Reset Value
RX_PAUSE_MACCONTROL_FRAMC
0x00C8 0x0000_0000
OUNTER
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_pause_maccontrol_framecounter
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_pause_maccontr CRC CRC

[31:0] RC
ol_framecounter
RX_UNKNOWN_MACCONTROL_FRAMCOUNTER
RX_UNKNOWN_MACCONTROL_FRAMCOUNTER MAC

02 (2010-01-19) 5-33

Hi3520
5 GMAC
Register Name
RX_UNKNOWN_MACCONTROL_FR
0x00CC 0x0000_0000
AMCOUNTER
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_unknown_maccontrol_framecounter
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_unknown_macc
[31:0] RC ontrol_framecounte
r
RX_VERY_LONG_ERR_CNT
RX_VERY_LONG_ERR_CNT

0x00D0 RX_VERY_LONG_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_very_long_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_very_long_err_c
[31:0] RC 2
nt
RX_RUNT_ERR_CNT
RX_RUNT_ERR_CNT 64byte 12byte

0x00D4 RX_RUNT_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_runt_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_runt_err_cnt 64byte 12byte

5-34 02 (2010-01-19)

Hi3520
5 GMAC
RX_SHORT_ERR_CNT
RX_SHORT_ERR_CNT 96bit

0x00D8 RX_SHORT_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_short_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_short_err_cnt 12byte
OCTETS_TRANSMITTED_OK
OCTETS_TRANSMITTED_OK

0x0100 OCTETS_TRANSMITTED_OK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name octets_transmitted_ok
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
octets_transmitted_
[31:0] RC
ok
OCTETS_TRANSMITTED_BAD
OCTETS_TRANSMITTED_BAD

02 (2010-01-19) 5-35

Hi3520
5 GMAC

0x0104 OCTETS_TRANSMITTED_BAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name octets_transmitted_bad
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
octets_transmitted_
[31:0] RC
bad
TX_UC_PKTS
TX_UC_PKTS

0x0108 TX_UC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_uc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_uc_pkts
TX_MC_PKTS
TX_MC_PKTS

0x010C TX_MC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_mc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_mc_pkts

5-36 02 (2010-01-19)

Hi3520
5 GMAC
TX_BC_PKTS
TX_BC_PKTS

0x0110 TX_BC_PKTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_bc_pkts
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_bc_pkts
TX_PKTS_64OCTETS
TX_PKTS_64OCTETS 64byte

0x0114 TX_PKTS_64OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_pkts_64octets
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_pkts_64octets 64byte
TX_PKTS_65TO127OCTETS
TX_PKTS_65TO127OCTETS 65byte127byte

0x0118 TX_PKTS_65TO127OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_pkts_65to127octets
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_65to127oct
[31:0] RC 65byte127byte
ets

02 (2010-01-19) 5-37

Hi3520
5 GMAC

0x011C TX_PKTS_128TO255OCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_128to255o
ctets

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_256to511o
ctets

5-38 02 (2010-01-19)

Hi3520
5 GMAC

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_512to1023
octets


Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_1024to151
[31:0] RC 1024byte1518byte
8octets
TX_PKTS_1519TOMAXOCTETS
TX_PKTS_1519TOMAXOCTETS 1519byte

0x012C TX_PKTS_1519TOMAXOCTETS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_pkts_1519tomaxoctes
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_pkts_1519tomax
[31:0] RC 1519byte
octes

02 (2010-01-19) 5-39

Hi3520
5 GMAC
TX_EXCESSIVE_LENGTH_DROP
TX_EXCESSIVE_LENGTH_DROP


0x014C TX_EXCESSIVE_LENGTH_DROP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_excessive_length_drop
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_excessive_lengt
[31:0] RC
h_drop
TX_UNDERRUN
TX_UNDERRUN

0x0150 TX_UNDERRUN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_underrun
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_underrun
TX_CRC_ERROR
TX_CRC_ERROR CRC

5-40 02 (2010-01-19)

Hi3520
5 GMAC

0x0158 TX_CRC_ERROR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_crc_error
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_crc_error CRC
TX_PAUSE_FRAMES
TX_PAUSE_FRAMES PAUSE

0x015C TX_PAUSE_FRAMES 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_pause_frames
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_pause_frames PAUSE
LINE_LOOP_BACK
LINE_LOOP_BACK MAC

02 (2010-01-19) 5-41

Hi3520
5 GMAC

0x01A8 LINE_LOOP_BACK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line_loop_back
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - forbidden
MAC
[0] RW line_loop_back 0
1
CF_CRC_STRIP
CF_CRC_STRIP CRC

0x01B0 CF_CRC_STRIP 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cf_crc_strip
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] - forbidden
MAC CRC
[0] RW cf_crc_strip 0 CRC 4byte
1 CRC 4byte

5-42 02 (2010-01-19)

Hi3520
5 GMAC
MODE_CHANGE_EN
MODE_CHANGE_EN

0x01B4 MODE_CHANGE_EN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mode_change_en
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - forbidden

[0] RW mode_change_en 0
1
LOOP_REG
LOOP_REG

0x01DC LOOP_REG 0x0000_0002
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cf_ext_drive
cf2mi_lp_en
forbidden
lp
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
[31:3] - forbidden

0
[2] RW cf2mi_lp_en
1

02 (2010-01-19) 5-43

Hi3520
5 GMAC
MAC
[1] RW cf_ext_drive_lp 0 MAC
1 MAC
[0] - forbidden
RECV_CONTROL
RECV_CONTROL

0x01E0 RECV_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
strip_pad_en
runt_pkt_en
forbidden
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:5] - forbidden

[4] RW runt_pkt_en 0 19byte
1 19byte
PAD
[3] RW strip_pad_en 0
1
[2:0] - forbidden
RX_OVERRUN_CNT
RX_OVERRUN_CNT FIFO

5-44 02 (2010-01-19)

Hi3520
5 GMAC

0x01EC RX_OVERRUN_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_overrun_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_overrun_cnt MAC FIFO
RX_LENGTHFIELD_ERR_CNT
RX_LENGTHFIELD_ERR_CNT PAD

0x01F4 RX_LENGTHFIELD_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_lengthfield_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rx_lengthfield_err_ MAC PAD PAD

[31:0] RC
cnt 64
MAC_SA_ADDR_L
MAC_SA_ADDR_L MAC 32bit

0x0200 MAC_SA_ADDR_L 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name mac_sa_addr_l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMU MAC 32bit SA

[31:0] RW mac_sa_addr_l
32bit

02 (2010-01-19) 5-45

Hi3520
5 GMAC
MAC_SA_ADDR_H
MAC_SA_ADDR_H MAC 16bit
PMU MAC MAC_SA_ADDR_H/ MAC_SA_ADDR_L MAC

MAC STATION_ADDR_HIGH/ STATION_ADDR_LOW


0x0204 MAC_SA_ADDR_H 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden mac_sa_addr_h
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
[15:0] RW mac_sa_addr_h PMU MAC 16bit
MAC_DA_ADDR_L
MAC_DA_ADDR_L MAC 32bit

0x0208 MAC_DA_ADDR_L 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name mac_da_addr_l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMU MAC 32bit DA

[31:0] RW mac_da_addr_l
32bit

5-46 02 (2010-01-19)

Hi3520
5 GMAC
MAC_DA_ADDR_H
MAC_DA_ADDR_H MAC 16bit

0x020C MAC_DA_ADDR_H 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden mac_da_addr_h
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
[15:0] RW mac_da_addr_h PMU MAC 16bit
CONTROL_WORD
CONTROL_WORD
crf_large_packet MAC MAX_FRM_SIZE


0x0214 CONTROL_WORD 0x0C00_0640
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_ip_head_chk_en
crf_udp_sum_chk_e
crf_filt_unused_pkg
crf_remove_0_byte
crf_ctrl_flow_ctrl
crf_insert_0_byte
crf_bm_flow_ctrl
crf_ip_flow_ctrl
crf_tx_standard
crf_add_da_sa
crf_peel_dsa
forbidden
forbidden
Name forbidden crf_large_packet

n
Reset 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0
[31:28] - forbidden

02 (2010-01-19) 5-47

Hi3520
5 GMAC
IP
crf_ip_head_chk_e
[27] RW 0
n
1
UDP
crf_udp_sum_chk_
[26] RW 0
en
1
FIFO
0 FIFO
FIFO 4
[25] RW crf_tx_standard MAC
1 FIFO MAC

1
[24] - forbidden
2byte 0
0
[23] RW crf_insert_0_byte 1
4
0
2byte 0
0
[22] RW crf_remove_0_byte 1
4
4 0

IP
[21] RW crf_ip_flow_ctrl 0
1

[20] RW crf_ctrl_flow_ctrl 0
1
[19:18] - forbidden

crf_filt_unused_pk
[17] RW 0
g
1

5-48 02 (2010-01-19)

Hi3520
5 GMAC

[16] RW crf_bm_flow_ctrl 0
1
DA/SA
[15] RW crf_peel_dsa 0
1
DA/SA
[14] RW crf_add_da_sa 0
1
1600bytePMU
[13:0] RW crf_large_packet

FLOW_CTRL_PKG_THRSLD
FLOW_CTRL_PKG_THRSLD

0x0218 FLOW_CTRL_PKG_THRSLD 0xFFFF_FFFF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name crf_ip_pkg_thrsld crf_ctrl_pkg_thrsld
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IP T IP
[31:16] RW crf_ip_pkg_thrsld

T
[15:0] RW crf_ctrl_pkg_thrsld

CRF_FLOW_TIME_THRSLD
CRF_FLOW_TIME_THRSLD

02 (2010-01-19) 5-49

Hi3520
5 GMAC

0x021C CRF_FLOW_TIME_THRSLD 0x0000_00FF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_flow_time_thrsld
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[31:8] - forbidden
crf_flow_time_thrsl 125s
[7:0] RW
d T=crf_flow_time_thrsld+1125s
FILTER_LIST0
FILTER_LIST0 0

0x0220 FILTER_LIST0 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg0
crf_filt_id0
Name forbidden crf_filt_frm_type0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
0
0
[17] RW crf_filt_cfg0 1
1

[16] RW crf_filt_id0 0 Ethernet Type
1 IP PROTOCOL

5-50 02 (2010-01-19)

Hi3520
5 GMAC

crf_filt_id0=0 16bit Ethernet Type
[15:0] RW crf_filt_frm_type0
crf_filt_id0=1 8bit IP PROTOCOL

FILTER_LIST1
FILTER_LIST1 1

0x0224 FILTER_LIST1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg1
crf_filt_id1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
1
0
1

1 IP PROTOCOL


FILTER_LIST2
FILTER_LIST2 2

02 (2010-01-19) 5-51

Hi3520
5 GMAC

0x0228 FILTER_LIST2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg2
crf_filt_id2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
2
0
1

1 IP PROTOCOL


FILTER_LIST3
FILTER_LIST3 3

5-52 02 (2010-01-19)

Hi3520
5 GMAC

0x022C FILTER_LIST3 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg3
crf_filt_id3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
3
0
1

1 IP PROTOCOL


FILTER_LIST4
FILTER_LIST4 4

02 (2010-01-19) 5-53

Hi3520
5 GMAC

0x0230 FILTER_LIST4 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg4
crf_filt_id4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
4
0
1

1 IP PROTOCOL


FILTER_LIST5
FILTER_LIST5 5

5-54 02 (2010-01-19)

Hi3520
5 GMAC

0x0234 FILTER_LIST5 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg5
crf_filt_id5
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
5
0
1

1 IP PROTOCOL


FILTER_LIST6
FILTER_LIST6 6

02 (2010-01-19) 5-55

Hi3520
5 GMAC

0x0238 FILTER_LIST6 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg6
crf_filt_id6
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
6
0
1

1 IP PROTOCOL


FILTER_LIST7
FILTER_LIST7 7

5-56 02 (2010-01-19)

Hi3520
5 GMAC

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg7
crf_filt_id7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
7
0
1

1 IP PROTOCOL


FILTER_LIST8
FILTER_LIST8 8

02 (2010-01-19) 5-57

Hi3520
5 GMAC

0x0240 FILTER_LIST8 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg8
crf_filt_id8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
8
0
1

1 IP PROTOCOL


FILTER_LIST9
FILTER_LIST9 9

5-58 02 (2010-01-19)

Hi3520
5 GMAC

0x0244 FILTER_LIST9 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg9
crf_filt_id9
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
9
0
1

1 IP PROTOCOL


FILTER_LIST10
FILTER_LIST10 10

02 (2010-01-19) 5-59

Hi3520
5 GMAC

0x0248 FILTER_LIST10 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg10
crf_filt_id10
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
10
0
1

1 IP PROTOCOL


FILTER_LIST11
FILTER_LIST11 11

5-60 02 (2010-01-19)

Hi3520
5 GMAC

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg11
crf_filt_id11
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
11
0
1

1 IP PROTOCOL


FILTER_LIST12
FILTER_LIST12 12

02 (2010-01-19) 5-61

Hi3520
5 GMAC

0x0250 FILTER_LIST12 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg12
crf_filt_id12
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
12
0
1

1 IP PROTOCOL


FILTER_LIST13
FILTER_LIST13 13

5-62 02 (2010-01-19)

Hi3520
5 GMAC

0x0254 FILTER_LIST13 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg13
crf_filt_id13
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
13
0
1

1 IP PROTOCOL


FILTER_LIST14
FILTER_LIST14 14

02 (2010-01-19) 5-63

Hi3520
5 GMAC

0x0258 FILTER_LIST14 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg14
crf_filt_id14
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
14
0
1

1 IP PROTOCOL


FILTER_LIST15
FILTER_LIST15 15

5-64 02 (2010-01-19)

Hi3520
5 GMAC

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_filt_cfg15
crf_filt_id15
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - forbidden
15
0
1

1 IP PROTOCOL


CRF_TX_FIFO_THRSLD
CRF_TX_FIFO_THRSLD FIFO

0x0264 CRF_TX_FIFO_THRSLD 0x0271_017C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_tx_p_full_th forbidden crf_tx_p_empty_th
Reset 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0
[31:26] - forbidden

02 (2010-01-19) 5-65

Hi3520
5 GMAC
FIFO
[25:16] RW crf_tx_p_full_th

[15:10] - forbidden
FIFO
[9:0] RW crf_tx_p_empty_th

CRF_RX_FIFO_THRSLD
CRF_RX_FIFO_THRSLD FIFO

0x0268 CRF_RX_FIFO_THRSLD 0x0640_0190
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_rx_p_full_th forbidden crf_rx_p_empty_th
Reset 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0
[31:26] - forbidden
FIFO
[25:16] RW crf_rx_p_full_th

[15:10] - forbidden
[9:0] RW crf_rx_p_empty_th FIFO
CRF_RX_BASE_ADDR
CRF_RX_BASE_ADDR FIFO

0x026C CRF_RX_BASE_ADDR 0x0000_0100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_rx_base_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
[31:9] - forbidden

5-66 02 (2010-01-19)

Hi3520
5 GMAC
FIFO
[8:0] RW crf_rx_base_addr
FIFO =512-crf_rx_base_addr
CRF_INTRPT_THRSLD
CRF_INTRPT_THRSLD

0x0270 CRF_INTRPT_THRSLD 0x001E_000F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cfg_fifoemp_intrpt_en
crf_time_intrpt_en
crf_pkg_intrpt_en
crf_rxint_en
crf_txint_en
forbidden
Name crf_intrpt_pkt crf_intrpt_time
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
[31:30] - forbidden

[29] RW crf_rxint_en 0
1

[28] RW crf_txint_en 0
1
FIFO
cfg_fifoemp_intrpt
[27] RW 0
_en
1

[26] RW crf_pkg_intrpt_en 0
1

[25:17] RW crf_intrpt_pkt

02 (2010-01-19) 5-67

Hi3520
5 GMAC

[16] RW crf_time_intrpt_en 0
1
125s
[15:0] RW crf_intrpt_time

CRF_FIFO_CLR
CRF_FIFO_CLR FIFO

0x0274 CRF_FIFO_CLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_tx_st_rst
crf_cff_clr
crf_rff_clr
crf_tff_clr
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:4] - forbidden

[3] RW crf_tx_st_rst 0
1
FIFO
0
[2] RW crf_cff_clr 1
1 FIFO
0 FIFO 0
FIFO
[1] RW crf_rff_clr 0
1
FIFO
[0] RW crf_tff_clr 0
1

5-68 02 (2010-01-19)

Hi3520
5 GMAC
CRF_INTRPT_CLR
CRF_INTRPT_CLR

0x027C CRF_INTRPT_CLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cfg_fifoemp_intrpt_sta
cfg_fifo_emp_intrpt
rx_intrpt_sta
rx_crf_intrpt
tx_intrpt_sta
tx_crf_intrpt
Name forbidden forbbiden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:19] - forbidden
1
[18] RW rx_crf_intrpt 0
1
1
[17] RW tx_crf_intrpt 0
1
FIFO 1
cfg_fifo_emp_intrp
[16] RW 0
t
1
[15:3] - forbbiden

[2] RO rx_intrpt_sta 0
1

[1] RO tx_intrpt_sta 0
1

02 (2010-01-19) 5-69

Hi3520
5 GMAC
FIFO
cfg_fifoemp_intrpt
[0] RO 0
_sta
1
ERR_GIVEN_PKG_CNT
ERR_GIVEN_PKG_CNT MAC

0x0280 ERR_GIVEN_PKG_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name err_given_pkg_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC err_given_pkg_cnt MAC
ERR_FRM_TYPE_CNT
ERR_FRM_TYPE_CNT

0x0288 ERR_FRM_TYPE_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name err_frm_type_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC err_frm_type_cnt
ERR_IP_TYPE_CNT
ERR_IP_TYPE_CNT IP

5-70 02 (2010-01-19)

Hi3520
5 GMAC

0x028C ERR_IP_TYPE_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name err_ip_type_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC err_ip_type_cnt IP
OVER_FLOW_CNT
OVER_FLOW_CNT FIFO

0x0294 OVER_FLOW_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name over_flow_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC over_flow_cnt FIFO
OVER_LENGTH_CNT
OVER_LENGTH_CNT

0x0298 OVER_LENGTH_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name over_length_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC over_length_cnt

02 (2010-01-19) 5-71

Hi3520
5 GMAC
CRF_CFF_DATA_NUM
CRF_CFF_DATA_NUM FIFO

0x02A8 CRF_CFF_DATA_NUM 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_rx_cfg_num forbidden crf_tx_cfg_num
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - forbidden
[25:16] RO crf_rx_cfg_num FIFO
[15:10] - forbidden
[9:0] RO crf_tx_cfg_num FIFO
FLOW_OUT_IP_CNT
FLOW_OUT_IP_CNT IP

0x02AC FLOW_OUT_IP_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name flow_out_ip_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC flow_out_ip_cnt IP
FLOW_OUT_CTRL_CNT
FLOW_OUT_CTRL_CNT

5-72 02 (2010-01-19)

Hi3520
5 GMAC

0x02B0 FLOW_OUT_CTRL_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name flow_out_ctrl_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC flow_out_ctrl_cnt
IP_CHK_ERR_CNT
IP_CHK_ERR_CNT IP

0x02B4 IP_CHK_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ip_chk_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IP
[31:0] RC ip_chk_err_cnt IP IP

UDP_CHK_ERR_CNT
UDP_CHK_ERR_CNT UDP

0x02B8 UDP_CHK_ERR_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name udp_chk_err_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC udp_chk_err_cnt UDP

02 (2010-01-19) 5-73

Hi3520
5 GMAC
TX_RUNT_ERR_PKG_CNT
TX_RUNT_ERR_PKG_CNT FIFO

0x02BC TX_RUNT_ERR_PKG_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_runt_err_pkg_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tx_runt_err_pkg_cn
[31:0] RC FIFO
t
RX_ERR_TOTAL_CNT
RX_ERR_TOTAL_CNT

0x02C0 RX_ERR_TOTAL_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_err_total_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_err_total_cnt
RX_TRANS_PKG_CNT
RX_TRANS_PKG_CNT

0x02C8 RX_TRANS_PKG_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_trans_pkg_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_trans_pkg_cnt

5-74 02 (2010-01-19)

Hi3520
5 GMAC
TX_TRANS_PKG_CNT
TX_TRANS_PKG_CNT

0x02CC TX_TRANS_PKG_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_trans_pkg_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC tx_trans_pkg_cnt
RX_BM_OVERFLOW
RX_BM_OVERFLOW

0x02D0 RX_BM_OVERFLOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_bm_overflow
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RC rx_bm_overflow
TX_ADDR_OVERFLOW
TX_ADDR_OVERFLOW CPU FIFO

02 (2010-01-19) 5-75

Hi3520
5 GMAC

0x02D4 TX_ADDR_OVERFLOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_addr_overflow
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPU FIFO CPU FIFO

[31:0] RC tx_addr_overflow
FIFO
RX_ADDR_OVERFLOW
RX_ADDR_OVERFLOW CPU FIFO

0x02D8 RX_ADDR_OVERFLOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_addr_overflow
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPU FIFO CPU

[31:0] RC rx_addr_overflow
FIFO FIFO
CRF_TX_PAUSE
CRF_TX_PAUSE

5-76 02 (2010-01-19)

Hi3520
5 GMAC

0x0340 CRF_TX_PAUSE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
crf_tx_pause_auto
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - forbidden

0MAC PMU
[0] RW crf_tx_pause_auto
FIFO MAC
1 MAC
CRF_RX_ADDR_NUM
CRF_RX_ADDR_NUM

0x0344 CRF_RX_ADDR_NUM 0x0000_000A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_rx_addr_num
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
[31:8] - forbidden
FIFO
[7:0] RW crf_rx_addr_num
0
CRF_CTRL_0_TYPE
CRF_CTRL_0_TYPE 0

02 (2010-01-19) 5-77

Hi3520
5 GMAC

0x0348 CRF_CTRL_0_TYPE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_ctrl_0_type
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
0
[15:0] RW crf_ctrl_0_type

CRF_CTRL_1_TYPE
CRF_CTRL_1_TYPE 1

0x034C CRF_CTRL_1_TYPE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
1

CRF_CTRL_2_TYPE
CRF_CTRL_2_TYPE 2

5-78 02 (2010-01-19)

Hi3520
5 GMAC

0x0350 CRF_CTRL_2_TYPE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
2

CRF_CTRL_3_TYPE
CRF_CTRL_3_TYPE 3

0x0354 CRF_CTRL_3_TYPE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - forbidden
3

CRF_BM_PKT_THRSLD
CRF_BM_PKT_THRSLD

02 (2010-01-19) 5-79

Hi3520
5 GMAC

0x0358 CRF_BM_PKT_THRSLD 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_bm_pkt_thrsld
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:16] - forbidden

[15:0] RW crf_bm_pkt_thrsld

CRF_BM_TIME_THRSLD
CRF_BM_TIME_THRSLD

0x035C CRF_BM_TIME_THRSLD 0x0000_2710
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name forbidden crf_bm_time_thrsld
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0
[31:20] - forbidden
[19:0] RW crf_bm_time_thrsld 1s
MDIO_SINGLE_CMD
MDIO_SINGLE_CMD MDIO

5-80 02 (2010-01-19)

Hi3520
5 GMAC

0x03C0 MDIO_SINGLE_CMD 0x0001_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mdio_cmd
forbidden
forbidden
phy_addr
op_code
Name forbidden forbidden reg_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - forbidden
MDIO

0MDIO
[20] RW mdio_cmd 1MDIO

0
1 MDIO
[19:18] - forbidden

00
[17:16] RW op_code 01
10
11
[15:10] - forbidden
[9:8] RW phy_addr PHY 2bit 3bit 0
[7:5] - forbidden
[4:0] RW reg_addr PHY
MDIO_SINGLE_DATA
MDIO_SINGLE_DATA MDIO

02 (2010-01-19) 5-81

Hi3520
5 GMAC

0x03C4 MDIO_SINGLE_DATA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name mdio_rd_data mdio_wr_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] RO mdio_rd_data MDIO PHY
[15:0] RW mdio_wr_data MDIO
MDIO_CTL
MDIO_CTL MDIO

0x03CC MDIO_CTL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mdio_in_wor
mdio_in_wor
mdc_speed
forbidden
k en
Name forbidden
k
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:4] - forbidden
MDIO
[3] RO mdio_in_work 0
1
MDIO
[2] RW mdio_in_work_en 0
1
[1] - forbidden
MDIO
[0] RW mdc_speed 02.5MHz
118MHz

5-82 02 (2010-01-19)

Hi3520
5 GMAC
MDIO_RDATA_STATUS
MDIO_RDATA_STATUS MDIO

0x03D0 MDIO_RDATA_STATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mdio_rdata_status
Name forbidden
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - forbidden
MDIO
[0] RC mdio_rdata_status 0
1
TX_CFF_LEN
TX_CFF_LEN

0x0400+m0x4 TX_CFF_LEN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_cff_len
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW tx_cff_len
TX_CFF_ADDR
TX_CFF_ADDR

02 (2010-01-19) 5-83

Hi3520
5 GMAC

0x0580+m0x4 TX_CFF_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_cff_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW tx_cff_addr
RX_CFF_ADDR
RX_CFF_ADDR

0x0480+n0x4 RX_CFF_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_cff_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW rx_cff_addr

5-84 02 (2010-01-19)

Hi3520
6
6.1
6.1.1
VIUVideo Input Unit BT.656/601 DCDigital
CameraVIU
1/2 Down ScalingChrominance Re-
samplingVIU 6-1
6-1 VIU
BT.656

BT.601
FIFO

Digital

Camera
6.1.2
VIU
z 4
z 16
z BT.656
z 2 4
z
z 0 2 BT.601
z 0 2 Digital Camera 300

02 (2010-01-19) 6-1

Hi3520
6
z 0 1 2 3 BT 1120
z 0 1 2 3 16-bit
z
z CbYCrYCrYCbYYCbYCr YCrYCb 4
z 1/2 Down Scaling
z Co-Sited Interspersed
z 2
z
z
z
package YCbCr 4:2:2
SPYCbCr 4:2:0 SPYCbCr 4:2:2
z raw data Y/C
z
z AXI Master DDR
z AHB Slave VIU
6.1.3
6-1
6-1
VI_DATAIN_P0[7:0] I 0 VI0DAT7
VI0DAT0
VI1DAT0
VI2DAT0
VI3DAT0
CLK_VI_P0 I 0 VI0CK
CLK_VI_P1 I 1 VI1CK
CLK_VI_P2 I 2 VI2CK
CLK_VI_P3 I 3 VI3CK

6-2 02 (2010-01-19)

Hi3520
6
VI_P0_HSYNC_VD I 0 VI0HS

VIn_PORT_CFG[port_hsync]

port_hsync=0

VIn_PORT_CFG[port_hsync_neg]

port_hsync=1


VI_P2_HSYNC_VD I 2 VI2HS

VIn_PORT_CFG[port_hsync]

port_hsync=0


port_hsync=1


VI_P0_VSYNC_FIELD I 0 VI0VS

VIn_PORT_CFG[port_vsync]

port_vsync=0

VIn_PORT_CFG[port_vsync_neg]

port_vsync=1


02 (2010-01-19) 6-3

Hi3520
6
VI_P2_VSYNC_FIELD I 2 VI2VS

VIn_PORT_CFG[port_vsync]

port_vsync=0


port_vsync=1


6.1.4
6.1.4.1
VIU 6-2
6-2 VIU
ARM DDRC
ARM AHB
AXI
slave master
video input
VIU DDR

6.1.4.2
ITU-R BT. 656 YCbCr4:2:2

1.

6-4 02 (2010-01-19)

Hi3520
6
ITU-R BT.656 SAV

EAV FF 00 00FF00

SAV EAVITU-R BT. 656 6-2
6-2 ITU-R BT.656 YCbCr 4:2:2
720 YCbCr 4:2:2
FF 00 00 EAV 80 10 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cr718 Y719
SAV EAV SAV/EAV HSAV/EAV

VFSAV/EAV 6-3
6-3 SAV/EAV
Bit7 Bit6(F) Bit5(V) Bit4(H) Bit[3:0](P3P0)
1 SAVH=0
1st fieldF=0 VBIV=1 EAVH=1
2nd fieldF=1 Active videoV=0
ITU-R BT.656 8 SAV EAV4

2 SAV/EAV 6-4
6-4 SAV/EAV
SAV 10000000 1 -
EAV 10011101 1 -
SAV 10101011 1
EAV 10110110 1
SAV 11000111 2 -
EAV 11011010 2 -
SAV 11101100 2
EAV 11110001 2
4 P0P1P2P3 FV H
6-5

02 (2010-01-19) 6-5

Hi3520
6
6-5 ITU-R BT.656
F V H P3 P2 P1 P0
0 0 0 0 0 0 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 0
1 0 0 0 1 1 1
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 0 0 0 1

P0=F^V^H
P1=F^V
P2=F^H
P3=V^H
2.
SAV/EAV FV 525 625

6-3 6-4

6-6 02 (2010-01-19)

Hi3520
6
6-3 525 60 /
LINE4 LINE 1
BLANKING (V=1)
FIELD 1 LINE 21
F=0 (V=0)
FIELD 1
ODD
ACTIVE VIDEO
LINE 264
LINE 266 (V=1)
BLANKING
FIELD 2 LINE 283

F=1 (V=0)
EVEN FIELD 2
ACTIVE VIDEO
LINE 525
LINE 3 (V=0)
H=1 H=0
EAV SAV
6-4 625 50 /
LINE1 LINE 1
BLANKIN (V=1)
G
LINE 23
FIELD 1 (V=1)
F=0 FIELD 1
ODD ACTIVE
VIDEO
LINE 311
LINE 313 (V=1)
BLANKIN
G
LINE 336
FIELD 2 (V=1)
FIELD 2
F=1 ACTIVE
EVEN VIDEO
LINE 624
(V=1)
BLANKIN
LINE 625 G LINE 625
H=1 H=0 (V=1)
EAV SAV
VIU SAV/EAV

02 (2010-01-19) 6-7

Hi3520
6
BT.656
VIU BT.656 2 4 BT.656
6-5 6-6
VIU
6-5 2 BT.656
CLK_VI
(54MHz)
CH0 FF 00 00 XY Cb0 Y0 Cr0
CH1 Cb40 Y40 Cr40 Y41 Cb42 Y42 Cr42
VI_DATAIN FF Cb40 00 Y40 00 Cr40 XY Y41 Cb0 Cb42 Y0 Y42 Cr0 Cr42
CLK_VI
(54MHz)
CH0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4
CH1 Y43 Cb44 Y44 Cr44 Y45 Cb46 Y46
VI_DATAIN Y1 Y43 Cb2 Cb44 Y2 Y44 Cr2 Cr44 Y3 Y45 Cb4 Cb46 Y4 Y46
6-6 4 BT.656
CLK_VI
(54/108MHz)
CH0 FF 00 00 Cb0
CH1 Cb38 Y38 Cr38 Y40
CH2 Cr20 Y22 Cb24
CH3 Y82 Cb84 Y84
VI_DATAIN FF Cb38 Cr20 Y82 00 Y38 Y22 Cb84 00 Cr38 Cb24 Y84 Cb0 Y40
CLK_VI
(54/108MHz)
CH0 Y0 Cr0 Cb1
CH1 Cb42 Y42 Cr42
CH2 Y24 Cr24 Y26 Cb28
Cr84 Y86 Cb88 Y88

CH3
VI_DATAIN Y24 Cr84 Y0 Cb42 Cr24 Y86 Cr0 Y42 Y26 Cb88 Cb1 Cr42 Cb28 Y88
SAV/EAV 2
VIn_CH_CFG[correct_en] 0
SAV/EAV 6-6

6-8 02 (2010-01-19)

Hi3520
6
6-6 SAV/EAV
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1:0]
1 F V H x x
BT 1120
VIU Y/C 2
6-7 6-8
6-7
CLK_VI_P0
(74.25MHz)
VI_DATA
FF 00 00 XY Y0 Y1 Y2 Y3 Y4
IN_P0(Y)
VI_DATA
IN_P0(C) FF 00 00 XY Cb0 Cr0 Cb2 Cr2 Cb4
6-8
LINE 0
(V=1)
BLANKING
LINE 30
(V=0)
ACTIVE VIDEO
LINE 749
(V=0)
H=1 H=0
EAV SAV
ITU-R BT.601 YCbCr4:2:2

1.

02 (2010-01-19) 6-9

Hi3520
6
6-9 hoffPAL525
122%2NTSC625 132%2
act_width 720 704

6-9 ITU-R BT.601
VI_HYSNC_VD
hoff
VI_DATAIN_
PX[7:0] Cb0 Y0 Cr0 Y1
... Cb718 Y718 Cr718 Y719
act_width
2.
ITU-R BT.601 VSYNC/FIELD VSYNC

FIELD VIU 2
VI NTSC 625 PAL 525 6-10 6-

11 VI_HSYNC_VD VI_VSYNC_FIELD VSYNC=1
VSYNC=0
6-10 NTSC
3 4 5 6 7 8 9
VI_HSYNC_VD
VI_VSYNC_FILED
(VSYNC=1)
VI_VSYNC_FILED
(VSYNC=0) NTSC VerticalTiming(odd field)
264 265 266 267 268 269 270

VI_HSYNC_VD
VI_VSYNC_FILED
(VSYNC=1)
VI_VSYNC_FILED
(VSYNC=0) NTSC VerticalTiming(even field)
NTSC 1 4
3 7 VIU 22
261 240 2 266
3 269 VIU 285 524
240

6-10 02 (2010-01-19)

Hi3520
6
6-11 PAL
625 1 2 3 4 5 6
VIHS
VIVS
(VSYNC=1)
VIVS
(VSYNC=0)
PAL VerticalTiming(odd field)
311 312 313 314 315 316 317

VIHS
VIVS
(VSYNC=1)
VIVS
(VSYNC=0) PAL verticalTiming(even field)
PAL 1 1
2.5 3 VIU 24 310
288 2 313
2.5 316 VIU 336
623 288
BT.601 VIU

VIU QXGA2048x1536
1.
VIU VI_HSYNC_VD
6-12
6-12
VI_HSYNC_VD
VI_DATAI
INVALID DATA Cb0 Y0 Cr0 Y1 ... Yn INVALID DATA Cb0 Y0
N_Px[7:0]
2.
VIU 6-13 6-14

02 (2010-01-19) 6-11

Hi3520
6
6-13
one frame
VI_VSYNC_FILED
VI_HSYNC_VD
VI_DATAI last
N_Px[7:0] row0 row1
row
frame timing diagram
6-14
one frame
VI_VSYNC_FILED
VI_HSYNC_VD
VI_DATAI row0 row1 last row

N_Px[7:0]
frame timing diagram
VIU VIU

16-bit
VIU YC 16-bit 0 1 1
0 2 3 1
2
1.
16bit 6-15
6-15 16bit
act_hoff act_width
CLK_VI
VI_HSYNC_VD
act_hoff act_width VI_Px_HSYNCvi_px_hsync_vd

VIn_PORT_CFG

6-12 02 (2010-01-19)

Hi3520
6
2.
16bit 6-16
6-16 16-bit
act1_voff act_height
VI_HSYNC_VD
VI_VSYNC_FILED
act1_voff act1_height VI_Px_VSYNC1vi_px_vsync_field

VIn_PORT_CFG
6-17

6-17
odd_line_start field1
frame_oddline_load
active
start_y
pixel_start video
height
capture video
start_x
frame_height
width
field2
even_line_start
frame_evenline_load
active
video
capture video
frame_width
6.1.7 VIn_CAP_START

02 (2010-01-19) 6-13

Hi3520
6
VIU DDR VIU

co-sited interspersed
1/2
1. YCbCr 4:2:2
co-sited interspersed 6-18 6-19
6-18 YCbCr 4:2:2 co-sited
CbCr Y
6-19 YCbCr 4:2:2 interspersed
CbCr Y
2. co-sited interspersed
BT.656/601YcbCr 4:2:2 co-sited VIU co-sited

interspersed
z co-sited

6-18
YCbCr 4:2:2 co-sited
z interspersed
6-19
interspersed
3. 1/2
1/2 VIU YCbCr

z Y 8 FIR
z 4 FIR
CbCr

6-14 02 (2010-01-19)

Hi3520
6
1/2 co-sited interspersed

z semi-planar YcbCr
z package
z raw data
1. semi-planar YcbCr
semi-planar
DDR
z 1
z 2 offset
DDR base_addr VI
6-20
6-20 YCbCr4:2:2
Width
luma_base_addr
Y0 Y1 Y2 .... Yw-1 Yw
luma_line_offset
Height
....
Width
chroma_base_addr
Cr0 Cb0 Cr2 .... Crw-1 Cbw-1
chroma_line_offset
Height
....

02 (2010-01-19) 6-15

Hi3520
6
DDR word32bit 4 8bit 32bit

word 4 word 2 big endian little endian 6-21
big endian little endian
6-21 big endian little endian
31 0 31 0
little endian Y3 Y2 Y1 Y0 Cb1 Cr1 Cb0 Cr0
big endian Y0 Y1 Y2 Y3 Cr0 Cb0 Cr1 Cb1

word word

VIU little endian DDR
2. package
package 4:2:2 Y/Cb/Cr 6-22
6-22 package
Width
base_addr
Cb0 Y0 Cr0 Y1 .... Crw-1 Yw
line_offset
Height
....
3. raw data
raw data word DDR 1

word 4 8bit 8bit 6-23

6-16 02 (2010-01-19)

Hi3520
6
6-23 raw data 8bit
Width
base_addr
D0 D1 D2 .... Dw-1 Dw
line_offset
Height
....
VIU
32bit

1 2 VIU
6-24

02 (2010-01-19) 6-17

Hi3520
6
6-24
anc_hos anc_size
anc_vos
anc_loc=2'b00

anc_loc=2'b01

anc_hos anc_size
anc_vos
anc_loc=2'b10

anc_loc=2'b11

VIU 4 16
6-25

6-18 02 (2010-01-19)

Hi3520
6
6-25 VIU
DATA PATH CHANNEL 0
DATA PATH CHANNEL 1

PORT 0
DATA PATH CHANNEL 2
DATA PATH CHANNEL 3
DATA PATH CHANNEL 4
DATA PATH CHANNEL 5

PORT 1
DATA PATH CHANNEL 6
BUS INTERFACE
DATA PATH CHANNEL 7
DATA PATH CHANNEL 8
DATA PATH CHANNEL 9

PORT 2
DATA PATH CHANNEL 10

PORT 3

0 0 1 4

6.1.5
6.1.5.1
VI VOGPIO IO Config reg0reg35
VI

02 (2010-01-19) 6-19

Hi3520
6
6.1.5.2
SC_PERCTRL8 bit[25:23] VIU 0 3
SC_PERCTRL8 bit[21] VIU

SC_PERCTRL8
6.1.5.3
VIU SC_PERCTRL9 bit[13:4]
SC_PERCTRL9
z vi1_vi0_selvi3_vi2_sel 1 3
0 1 0
1 vi1_vi0_sel 1 2 3
2 3 vi3_vi2_sel 1
z vi0div_selvi1div_selvi2div_selvi3div_sel
4
4 2 2
VIU 6-26
6-26 VIU
vi0div_sel
clk for port0 clk for ch0 to
CLK_VI_PO
ch3
vi1_vi0_sel vi1div_sel
CLK_VI_P1 ch7
vi2div_sel

CLK_VI_P2
ch11
vi3_vi2_sel vi3div_sel

CLK_VI_P3 ch15
6.1.5.4
VIU 17 VIU 8 VIU
VIn_INT_EN
VIn_INT_STATUS

6-20 02 (2010-01-19)

Hi3520
6
6.1.5.5
VIU reg_newer
z VIU
VIU VIn_REG_NEWER
reg_newer 1 VIU
z VIU VIU /
reg_newer 0 VIU SNOOZE
/
reg_newer 1
(reg_update_int) busy
z busy /
reg_newer 0/
reg_newer 1/
VIU 6-27
6-27 VIU
VIU

/
SNOOZE

reg_newer1
vi_busy=1
image done=1
vi_busy=0

02 (2010-01-19) 6-21

Hi3520
6
BT.656/601 digital camera /

VIU reg_newer reg_newer 1
VIU VIU load
reg_newer 0/
reg_newer 1 /
6-28
6-28
reg_newer=1
frame_pulsereg_update

/
,reg_newer=1
cc

BT.656 digital camera

VIn_CAP_SIZEVIn_LINE_OFFSETVIn_YBASE_ADDR
VIn_UBASE_ADDRVIn_VBASE_ADDRVIn_CH_CTRLVIn_CAP_START
BT.601 VI_Px_VSYNC1VI_Px_VSYNC2
VI_Px_HSYNC1 PAL
6-29

6-22 02 (2010-01-19)

Hi3520
6
6-29
reg_newer1
6.1.6
VIU 6-7
6-7 VIU 0x1010_0000
0x0000+n%0x1000 VIn_PORT_CFG 6-25
0x0004+n%0x1000 VIn_CH_CFG 6-27
0x0008+n%0x1000 VIn_CH_CTRL 6-30
0x000C+n%0x1000 VIn_REG_NEWER 6-32
0x0010+n%0x1000 VIn_CAP_START 6-32
0x0014+n%0x1000 VIn_CAP_SIZE 6-34
0x0018+n%0x1000 VIn_Y_STORESIZE Y 6-34
0x001C+n%0x1000 VIn_U_STORESIZE Cb 6-35
0x0020+n%0x1000 VIn_V_STORESIZE Cr 6-35
0x0024+n%0x1000 VIn_LINE_OFFSET 6-38
0x0028+n%0x1000 VIn_YBASE_ADDR Y 6-38
0x002C+n%0x1000 VIn_UBASE_ADDR Cb 6-39

02 (2010-01-19) 6-23

Hi3520
6
0x0030+n%0x1000 VIn_VBASE_ADDR Cr 6-39
0x0034 VI_INT_DLY_CNT 6-40
0x0038+n%0x1000 VIn_INT_EN 6-40
0x003C+n%0x1000 VIn_INT_STATUS 6-42
0x0040+n%0x1000 VIn_RAW_INT 6-43
0x0044 VI_INT_INDICATOR 6-45
0x0048+n%0x1000 VI_RAW_INT_INDIC 6-47

ATOR
0x004C+n%0x1000 VIn_STATUS 6-49
0x0050+n%0x1000 VIn_LUM_ADDER 6-50
0x0054+n%0x1000 VIn_LUM_STRH 6-50
0x0058+n%0x1000 VIn_LUM_DIFF_AD 6-51

DER
0x005C+n%0x1000 VIn_BLOCK0_STAR 0 6-52
T
0x0060+n%0x1000 VIn_BLOCK1_STAR 1 6-52
T
T
T
0x006C+n%0x1000 VIn_BLOCK0_SIZE 0 6-53
0x0070+n%0x1000 VIn_BLOCK1_SIZE 1 6-54
0x007C+n%0x1000 VIn_BLOCK0_COLO 0 6-55

R
0x0080+n%0x1000 VIn_BLOCK1_COLO 1 6-56
R
R
R

6-24 02 (2010-01-19)

Hi3520
6
0x009C+n%0x1000 VIn_ANC0_START 0 6-57

0x00A0+n%0x1000 VIn_ANC0_SIZE 0 6-58
0x00A4+n%0x1000 VIn_ANC1_START 1 6-59

0x00A8+n%0x1000 VIn_ANC1_SIZE 1 6-59
0x00AC+n%0x1000 VIn_ANC_WORD 6-60
0x00CC+n%0x1000 VIn_ANC_WORD 6-60
0x00EC VI_P0_VSYNC1 0 6-61
0x80EC VI_P2_VSYNC1 2 6-62
0x00F0 VI_P0_VSYNC2 0 6-62
0x80F0 VI_P2_VSYNC2 2 6-63
0x00F4 VI_P0_HSYNC 0 6-64
0x80F4 VI_P2_HSYNC 2 6-64
0x00F8 VI_PRIO_CONFIG 6-64
0x00FC+n%0x1000 VIn_LUM_COEF0 0 6-67
0x0100+n%0x1000 VIn_LUM_COEF1 1 6-67
0x0104+n%0x1000 VIn_LUM_COEF2 2 6-68
0x0108+n%0x1000 VIn_LUM_COEF3 3 6-68
0x010C+n%0x1000 VIn_CHROMA_COE 0 6-69

F0
0x0110+n%0x1000 VIn_CHROMA_COE 1 6-70
F1
VIn_ABC n VI 0n15 n
6.1.7
VIn_PORT_CFG
VIn_PORT_CFG
VIn_PORT_CFG n=04812

02 (2010-01-19) 6-25

Hi3520
6

0x0000+n%0x1000 VIn_PORT_CFG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
port_mux_mode
port_scan_mode
port_vsync_neg
port_hsync_neg
port_cap_mode
port_vsync
port_hsync
reserved
port_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:12] - reserved

bit[11]
0
[11:10] RW port_scan_mode 1
bit[10]
0
1

00BT.656
01BT.601
[9:8] RW port_cap_mode 10

1 3
BT.656

001 D1
[7:6] RW port_mux_mode 012 D1
104 D1 half D1

[5] - reserved
VI_P_VSYNC_FIELD
0
[4] RW port_vsync z BT.601
z camera
1

6-26 02 (2010-01-19)

Hi3520
6
16-bit bit
VI_P_VSYNC_FIELD
0
port_vsync=1
port_vsync=0

[3] RW port_vsync_neg
1
port_vsync=1
port_vsync=0

VI_P_HSYNC_VD
0VI_P_HSYNC_VD
[2] RW port_hsync
1VI_P_HSYNC_VD
16-bit 1
VI_P_HSYNC_VD
0
port_hsync=1
[1] RW port_hsync_neg port_hsync=0
1
port_hsync=1
port_hsync=0

[0] RW port_en 0
1
VIn_CH_CFG
VIn_CH_CFG

02 (2010-01-19) 6-27

Hi3520
6

0x0004+n%0x1000 VIn_CH_CFG 0x0000_1480
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
chroma_resample
down_scaling
even_line_sel
store_method
odd_line_sel
chrom_swap
little_endian
store_mode
seav_f_neg
yc_channel
data_width
correct_en
ch_id_en
fix_code
reserved
cap_seq
cap_sel
ch_id
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0
[31:27] - reserved
BT.656 bit
[26] RW fix_code 0 1
1 0
Y/C
0 Y
[25] RW yc_channel
1 C
Y/C
BT.656 F
[24] RW seav_f_neg 01st field:F=02nd field:F=1
11st field:F=12nd field:F=0
swap
0
1halfword
[23] RW chrom_swap Y/C 4
12
0 Cr1Cb1Cr0Cb0
1 Cb1Cr1Cb0Cr0

0
[22] RW ch_id_en 1
2 4

6-28 02 (2010-01-19)

Hi3520
6

00 00
01 01
[21:20] RW ch_id 10 10
11 11

[19:17] - reserved

00
01
10

[16:15] RW even_line_sel
0
YcbCr 4:2:0
DC even_line_sel

4 12

00
01
10

[14:13] RW odd_line_sel 0
YcbCr 4:2:0
DC
odd_line_sel

4
12
SAVStart of Active Video/EAVEnd of Activevideo

[12] RW correct_en
0
1
1/2
0
[11] RW down_scaling
1
Y/C

02 (2010-01-19) 6-29

Hi3520
6

0
[10] RW chroma_resample 1co-sited interspersed
co-sited interspersed
Y/C
Store Method
00planar Y/Cb/Cr
[9:8] RW store_method 01semi-planar YCbCr
10package YCbCr4:2:2
11raw data Y/C

00
[7:6] RW cap_sel 01
10

YCbCr
00CbYCrY
[5:4] RW cap_seq 01CrYCbY
10YCbYCr
11YCrYCb
[3] - reserved
Store Mode
0
[2] RW store_mode 1

Data Width
008bit
[1:0] RW data_width
1010bit

VIn_CH_CTRL
VIn_CH_CTRL VIn_CH_CTRL
VIU reg_newer

6-30 02 (2010-01-19)

Hi3520
6

0x0008+n%0x1000 VIn_CH_CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
lum_strh_en
block3_en
block2_en
block1_en
block0_en
debug_en
anc1_en
anc0_en
ch_en
Name reserved reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved

0
[15] RW debug_en
1
0

0
[14] RW lum_strh_en
1

1
[13] RW anc1_en 0
1
0
[12] RW anc0_en 0
1
[11:8] - reserved
3
[7] RW block3_en 0
1
2
[6] RW block2_en 0
1
1
[5] RW block1_en 0
1

02 (2010-01-19) 6-31

Hi3520
6
0
[4] RW blcok0_en 0
1
[3:1] - reserved
VIU
0
[0] RW ch_en 1
BT.656 BT.601
bit 0 1
VIn_REG_NEWER
VIn_REG_NEWER /


0x000C+n%0x1000 VIn_REG_NEWER 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reg_newer
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
/
0/
/
[0] RW reg_newer 1//
/
VIU

VIn_CAP_START
VIn_CAP_START

6-32 02 (2010-01-19)

Hi3520
6
VIn_CAP_SIZE
VIn_CAP_START VIn_CAP_SIZE 6-
30
z VIn_CAP_START start_y
start_x
z VIn_CAP_SIZE widthheight
width start_x YCbCr 4:2:2

height start_y
6-30
0 M-1
0
start_y

start_x
height

width
N-1
start_y start_x VIn_CAP_START 12bit

width height VIn_CAP_SIZE 12

0x0010+n%0x1000 VIn_CAP_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved start_y start_x
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:12] RW start_y
[11:0] RW start_x

02 (2010-01-19) 6-33

Hi3520
6
VIn_CAP_SIZE
VIn_CAP_SIZE

0x0014+n%0x1000 VIn_CAP_SIZE 0x0012_02d0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved height width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0
[31:24] - reserved

1/2VI
[23:12] RW height

VI 1

[11:0] RW width
VI 4
VIn_Y_STORESIZE
VI_Y_STORESIZE Y

0x0018+n%1000 VIn_Y_STORESIZE 0x000F_00A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved y_height y_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
[31:24] - reserved
[23:12] RW y_height ,,
YCbCr4:2:0 ,

Y 1 128bit
[11:0] RW y_width
128 128

6-34 02 (2010-01-19)

Hi3520
6
VIn_U_STORESIZE
VIn_U_STORESIZE Cb package
semi-planar YCbCr planar YCbCr
Cb

0x001C+n%0x1000 VIn_U_STORESIZE 0x000F_00A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved c_height c_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
[31:24] - reserved
semi-planar YCbCr

[23:12] RW c_height planar YCbCr Cb

package raw data
semi-planar YCbCr 1
128bit 128bit 128bit
[11:0] RW c_width planar YCbCr Cb word
word word
package raw data
VIn_V_STORESIZE
VIn_V_STORESIZE Cr

0x0020+n%0x1000 VIn_V_STORESIZE 0x000F00A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved v_height v_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
[31:24] - reserved
[23:12] RW v_height Cr

02 (2010-01-19) 6-35

Hi3520
6
Cr 1 128bit
128bit 128bit
[11:0] RW v_width
semi-planar YCbCr package YCbCr
raw data
YCbCr4:2:2
1 cap_width 1
cap_width=cap_width-cap_width%2
2 1/2
down_scaling?
yes:cap_width=cap_width/2
no:cap_width=cap_width
1. Y/Cb/Cr
8bit
y_width=if(cap_width%16==0)
cap_width/16
else
cap_width/16+1
c_width = if(cap_width%32==0)
cap_width/32
else
cap_width/32+1
v_width=if(cap_width%32==0)
cap_width/32
else
cap_width/32+1
10bit
cap_width/8
else
cap_width/8+1
c_width=if(cap_width%16==0)
cap_width/16
else
cap_width/16+1
v_width=if(cap_width%16==0)
cap_width/16
else
cap_width/16+1

6-36 02 (2010-01-19)

Hi3520
6
2. planar Y/C
8bit
cap_width/16
else
cap_width/16+1
cap_width/16
else
cap_width/16+1
10bit
cap_width/8
else
cap_width/8+1
cap_width/8
else
cap_width/8+1
3. package
8bit
cap_width/8
else
cap_width/8+1
10bit
cap_width/4
else
cap_width/4+1
4. raw data
8bit
cap_width/16
else
cap_width/16+1
10bit
cap_width/8
else
cap_width/8+1
4
y_width=y_width-1

02 (2010-01-19) 6-37

Hi3520
6
c_width=c_width-1
v_width=v_width-1
----
VIn_LINE_OFFSET
VIn_LINE_OFFSET
word

0x0024+n%0x1000 VIn_LINE_OFFSET 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name yline_offset uline_offset vline_offset
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
128bit yline_offset 4bit

raw data stride
[31:20] RW yline_offset
package YCbCr4:2:2 stride
planar Y/C Y/Cb/Cr Y stride
128bit uline_offset 4bit

raw data
[19:10] RW uline_offset package YCbCr4:2:2
planar Y/C C stride
planar Y/Cb/Cr Cb stride
128bit vline_offset 4bit

raw data
[9:0] RW vline_offset package YCbCr4:2:2
planar Y/C
planarY/Cb/Cr Cr stride
VIn_YBASE_ADDR
VIn_YBASE_ADDR0 Y 0 Y
3bits 0

6-38 02 (2010-01-19)

Hi3520
6

0x0028+n%0x1000 VIn_YBASE_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vi_ybase_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Y
4 0128bit
raw data
[31:0] RW vi_ybase_addr
package YCbCr4:2:2
planar Y/C planar Y/Cb/Cr Y

VIn_UBASE_ADDR
VIn_UBASE_ADDR Cb 0 Cb
3bits 0

0x002C+n%0x1000 VIn_UBASE_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vi_ubase_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Cb
4 0128
raw data
[31:0] RW vi_ubase_addr package YCbCr4:2:2
planar Y/C C
planar Y/Cb/Cr Y/Cb/Cr Cb

VIn_VBASE_ADDR
VIn_VBASE_ADDR0 Cr 0 Cr
3bits 0

02 (2010-01-19) 6-39

Hi3520
6

0x0030+n%0x1000 VIn_VBASE_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vi_vbase_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Cr
4 0128
raw data
[31:0] RW vi_vbase_addr
package YCbCr4:2:2
planar Y/C
planar Y/Cb/Cr Cr
VI_INT_DLY_CNT
VI_INT_DLY_CNT

0x0034 VI_INT_DLY_CNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name int_dly_cnt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:0] RW int_dly_cnt 16
VIU
VIn_INT_EN
VIn_INT_EN

6-40 02 (2010-01-19)

Hi3520
6

0x0038+n%0x1000 VIn_INT_EN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ntsc_pal_trans_int_en
frame_pulse_int_en
field_throw_int_en
reg_update_int_en
chdiv_err_int_en
proc_err_int_en
buf_ovf_int_en
err_int_en
cc_int_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:9] - reserved

[8] RW chdiv_err_int_en 0
1

ntsc_pal_trans_int_
[7] RW 0
en
1

[6] RW frame_pulse_int_en 0
1

[5] RW reg_update_int_en 0
1
BT.656
[4] RW proc_err_int_en 0
1

[3] RW err_int_en 0
1
/
[2] RW field_throw_int_en 0
1

02 (2010-01-19) 6-41

Hi3520
6
FIFO
[1] RW buf_ovf_int_en 0
1

[0] RW cc_int_en 0
1
VIn_INT_STATUS
VIn_INT_STATUS 1


0x003C+n%0x1000 VIn_INT_STATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ntsc_pal_trans_int
frame_pulse_int
field_throw_int
reg_update_int
chdiv_err_int
proc_err_int
buf_ovf_int
error_int
cc_int
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:9] - reserved

[8] WC chdiv_err_int 0
1

0
[7] WC ntsc_pal_trans_int 1
N
P

[6] WC frame_pulse_int 0
1

6-42 02 (2010-01-19)

Hi3520
6

0
1
[5] WC reg_update_int VIn_CH_CFG[store_mode] 1

VIn_CH_CFG[store_mode] 0

BT.656
[4] WC proc_err_int 0
1
AHB
[3] WC error_int 0
1

0
[2] WC field_throw_int 1

FIFO
[1] WC buf_ovf_int 0
1

0
1
[0] WC cc_int VIn_CH_CFG[store_mode] 0

VIn_CH_CFG[store_mode] 1

VIn_RAW_INT
VIn_RAW_INT bit 1
DEBUG

02 (2010-01-19) 6-43

Hi3520
6

0x0040+n%0x1000 VIn_RAW_INT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ntsc_pal_trans_raw_int
frame_pulse_raw_int
field_throw_raw_int
reg_update_raw_int
chdiv_err_raw_int
proc_err_raw_int
buf_ovf_raw_int
error_raw_int
cc_raw_int
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:9] - reserved

[8] RO chdiv_err_raw_int 0
1

0
ntsc_pal_trans_raw
[7] RO 1
_int
N
P

frame_pulse_raw_i
[6] RO 0
nt
1

[5] RO reg_update_raw_int 0
1
BT.656
[4] RO proc_err_raw_int 0
1
AHB
[3] RO error_raw_int 0
1

field_throw_raw_in
[2] RO 0
t
1

6-44 02 (2010-01-19)

Hi3520
6
FIFO
[1] RO buf_ovf_raw_int 0
1
cc:capture
completion
0
[0] RO cc_raw_int
1
store_mode 0
store_mode 1
VI_INT_INDICATOR
VI_INT_INDICATOR 16


0x0044+n%0x1000 VI_INT_INDICATOR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch15_int_indicator
ch14_int_indicator
ch13_int_indicator
ch12_int_indicator
ch11_int_indicator
ch10_int_indicator
ch9_int_indicator
ch8_int_indicator
ch7_int_indicator
ch6_int_indicator
ch5_int_indicator
ch4_int_indicator
ch3_int_indicator
ch2_int_indicator
ch1_int_indicator
ch0_int_indicator
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
15
[15] RO ch15_int_indicator 0
1
14
1
13
1

02 (2010-01-19) 6-45

Hi3520
6
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1

6-46 02 (2010-01-19)

Hi3520
6
1
1
0
1
VI_RAW_INT_INDICATOR
VI_RAW_INT_INDICATOR 16


0x0048+n%0x1000 VI_RAW_INT_INDICATOR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch15_raw_int_indicator
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
15
ch15_raw_int_indic
[15] RO 0
ator
1
14
ch14_raw_int_indic
[14] RO 0
ator
1
13
ch13_raw_int_indic
[13] RO 0
ator
1
12
ch12_raw_int_indic
[12] RO 0
ator
1

02 (2010-01-19) 6-47

Hi3520
6
11
ch11_raw_int_indic
[11] RO 0
ator
1
10
ch10_raw_int_indic
[10] RO 0
ator
1
9
ch9_raw_int_indica
[9] RO 0
tor
1
8
ch8_raw_int_indica
[8] RO 0
tor
1
7
ch7_raw_int_indica
[7] RO 0
tor
1
6
ch6_raw_int_indica
[6] RO 0
tor
1
5
ch5_raw_int_indica
[5] RO 0
tor
1
4
ch4_raw_int_indica
[4] RO 0
tor
1
3
ch3_raw_int_indica
[3] RO 0
tor
1
2
ch2_raw_int_indica
[2] RO 0
tor
1
1
ch1_raw_int_indica
[1] RO 0
tor
1

6-48 02 (2010-01-19)

Hi3520
6
0
ch0_raw_int_indica
[0] RO 0
tor
1
VIn_STATUS
VIn_STATUS

0x004C+n%0x1000 VIn_STATUS 0x0000_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
image_done
frame_loss
proc_err
vi_busy
buf_ovf
bus_err
snooze
field2
Name reserved act_height
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:20] - reserved
[19:8] RO act_height
VIU
[7] RO vi_busy 0
1

[6] RO field2 0
1
VIU
[5] RO snooze 0
1

[4] RO proc_err 0
1

[3] RO bus_err 0
1

02 (2010-01-19) 6-49

Hi3520
6
VIU
[2] RO frame_loss 0
1
VIU buffer
[1] RO buf_ovf 0
1
VIU
[0] RO image_done 0
1
VIn_LUM_ADDER
VIn_LUM_ADDER


0x0050+n%0x1000 VIn_LUM_ADDER 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name lum_adder
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO vi_lum_adder
VIn_LUM_STRH

luma _ out = ( sign(luma _ in m0) * (k * | luma _ in m0 | +64) >> 7) + m0

m0 VIn_LUM_ADDER

k 6419664 196
128
m1 m0

6-50 02 (2010-01-19)

Hi3520
6

0x0054+n%0x1000 VIn_LUM_STRH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name m1 m0 k
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
[29:20] RW m1 1
[19:18] - reserved
[17:8] RW m0 0
[7:0] RW k
VIn_LUM_DIFF_ADDER
m1

z
VIn_LUM_STRH k
128
z
VIn_LUM_STRH k
128
0x0058+n%0x1000 VIn_LUM_DIFF_ADDER 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name lum_diff_adder
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
720p 0
[31:0] RO lum_diff_adder 4
/

02 (2010-01-19) 6-51

Hi3520
6
VIn_BLOCK0_START
VIn_BLOCK0_START 0

0x005C+n%0x1000 VIn_BLOCK0_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block0_starty block0_stone_startx
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:12] RW block0_starty 0
[11:0] RW block0_startx 0
VIn_BLOCK1_START
VIn_BLOCK1_START 1

0x0060+n%0x1000 VIn_BLOCK1 _START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block1_starty block1_stone_startx
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
VIn_BLOCK2_START
VIn_BLOCK2_START 2

6-52 02 (2010-01-19)

Hi3520
6

0x0064+n%0x1000 VIn_BLOCK2 _START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block2_stone_starty block2_stone_startx
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access name Description
[31:24] - reserved
VIn_BLOCK3_START
VIn_BLOCK3_START 3

0x0068+n%0x1000 VIn_BLOCK3_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block3_stone_starty block3_stone_startx
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Access name Description
[31:24] - reserved
VIn_BLOCK0_SIZE
VIn_BLOCK0_SIZE 0

02 (2010-01-19) 6-53

Hi3520
6

0x006C+n%0x1000 VIn_BLOCK0_SIZE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block0_stone_height block0_stone_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:12] RW block0_height 0
[11:0] RW block0_width 0
VIn_BLOCK1_SIZE
VIn_BLOCK1_SIZE 1

0x0070+n%0x1000 VIn_BLOCK1_SIZE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
VIn_BLOCK2_SIZE
VIn_BLOCK2_SIZE 2

6-54 02 (2010-01-19)

Hi3520
6

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
VIn_BLOCK3_SIZE
VIn_BLOCK3_SIZE 3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
VIn_BLOCK0_COLOR
VIn_BLOCK0_COLOR 0

z YCbCr
z VIU
0123 0 3

02 (2010-01-19) 6-55

Hi3520
6

0x007C+n%0x1000 VIn_BLOCK0_COLOR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block0_stone_y block0_stone_u block0_stoner_v
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW block0_y 0 Y
[15:8] RW block0_u 0 Cb
[7:0] RW block0_v 0 Cr
VIn_BLOCK1_COLOR
VIn_BLOCK1_COLOR 1

0x0080+n%0x1000 VIn_BLOCK1_COLOR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block1_stone_y block1_stone_u block1_stoner_v
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW block1_y 1 Y
VIn_BLOCK2_COLOR
VIn_BLOCK2_COLOR 2

6-56 02 (2010-01-19)

Hi3520
6

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block2_stone_y block2_stone_u block2_stone_v
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW block2_y 2 Y
VIn_BLOCK3_COLOR
VIn_BLOCK3_COLOR 3

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block3_stone_y block3_stone_u block3_stone_v
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW block3_y 3 Y
VIn_ANC0_START
VIn_ANC0_START 0

02 (2010-01-19) 6-57

Hi3520
6

0x009C+n%0x1000 VI_ANC0_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Vbi_location1
Name reserved Vbi-vos1 Vbi-hos1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

00
01
[25:24] RW anc0_loc 10
11
DC

[23:12] RW anc0_vos

[11:0] RW anc0_hos

VIn_ANC0_SIZE
VIn_ANC0_SIZE 0

0x00A0+n%0x1000 VIn_ANC0_SIZE 0x0000_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vbi-size1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:12] - reserved
[11:0] RW anc0_size

6-58 02 (2010-01-19)

Hi3520
6
VIn_ANC1_START
VIn_ANC1_START 1

0x00A4+n%0x1000 VIn_ANC1_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Vbi_location2
Name Reserved Vbi-vos2 Vbi-hos2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - Reserved

00
01
[25:24] RW anc1_loc 10
11
DC

[23:12] RW anc1_vos

[11:0] RW anc1_hos

VIn_ANC1_SIZE
VIn_ANC1_SIZE 1

0x00A8+n%0x1000 VIn_ANC1_SIZE 0x0000_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vbi-size2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:12] - reserved
[11:0] RW anc1_size

02 (2010-01-19) 6-59

Hi3520
6
VIn_ANC0_WORD
VIn_ANC0_WORD 16 word 1 1
8 32bit VIn_ANC0_WORD0

z 0x00ACVIn_ANC0_WORD0
z 0x00B0VIn_ANC0_WORD1
z 0x00BCVIn_ANC0_WORD4
z 0x00C0VIn_ANC0_WORD5
VIn_ANC0_WORD0

0x00AC+n%0x1000 VIn_ANC0_WORD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VIn_ANC0_WORD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:0] RO VIn_ANC0_WORD 1 1 word
VIn_ANC1_WORD
VIn_ANC1_WORD 16 word 2 2
8 32bit VIn_ANC1_WORD0

z 0x00CCVIn_ANC1_WORD0
z 0x00D0VIn_ANC1_WORD1
z 0x00DCVIn_ANC1_WORD4
z 0x00E0VIn_ANC1_WORD5

6-60 02 (2010-01-19)

Hi3520
6
VIn_ANC1_WORD0

0x00CC+n%0x1000 VIn_ANC1_WORD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VIn_ANC1_WORD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:0] RO VIn_ANC1_WORD 2 1 word
6-31
6-31
Byte0 Byte1 Byte2 ... ... Byte31
bit31 bit0
Byte0 Byte1 Byte2 Byte3 ANC_WORD0

... ...
VI_P0_VSYNC1
0 BT.601 VI_P0_VSYNC1 1
0 0 16-bit
VI_P0_VSYNC1 0 4

0x00EC VI_P0_VSYNC1 0x0001_511F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved act1_voff act1_height
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1
[31:24] - reserved
[23:12] RW act1_voff BT.601 1 16-bit

02 (2010-01-19) 6-61

Hi3520
6
1 21
BT.601 1 16-bit
[11:0] RW act1_height
1 287
16-bit ,()
VI_P2_VSYNC1
8 2 16-bit
VI_P2_VSYNC1 8 12

0x80EC VI_P0_VSYNC1 0x0001_511F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1
[31:24] - reserved
BT.601 1 16-bit
[23:12] RW act1_voff
1 21
BT.601 1 16-bit
1 287
16-bit ,,

VI_P0_VSYNC2
0

6-62 02 (2010-01-19)

Hi3520
6

0x00F0 VI_P0_VSYNC2 0x0001_611F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1
[31:24] - reserved
2
1 22
2
1 287
16-bit

VI_P2_VSYNC2
8

0x80F0 VI_P0_VSYNC2 0x0001_611F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1
[31:24] - reserved
2
1 22
2
1 287
16-bit ,,()

02 (2010-01-19) 6-63

Hi3520
6
VI_P0_HSYNC
VI_P0_HSYNC 0 BT.601
0 0 16-bit
0 4

0x00F4 VI_P0_HSYNC 0x0004_159F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved act_hoff act_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1
[31:24] - reserved

[23:12] RW act_hoff BT.601 2 1 263
16-bit 1

BT.601 2 1 1439720
[11:0] RW act_width

16-bit 1
16-bit
VI_P2_HSYNC
VI_P2_HSYNC 2 BT.601
8 0 16-bit
8 12

6-64 02 (2010-01-19)

Hi3520
6

0x80F4 VI_P2_HSYNC 0x0004_159F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved act_hoff act_width
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1
[31:24] - reserved

[23:12] RW act_hoff BT.601 2 1 263
16-bit 1

BT.601 2 1 1439720
[11:0] RW act_width

16-bit 1
16bit BT.601 ,,
VI_PRIO_CFG
VI_PRIO_CFG VIU 16 2


0x00F8 VI_PRIO_CFG 0x0004_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
outstanding_max
vi15_prio_ctrl
vi14_prio_ctrl
vi13_prio_ctrl
vi12_prio_ctrl
vi11_prio_ctrl
vi10_prio_ctrl
vi9_prio_ctrl
vi8_prio_ctrl
vi7_prio_ctrl
vi6_prio_ctrl
vi5_prio_ctrl
vi4_prio_ctrl
vi3_prio_ctrl
vi2_prio_ctrl
vi1_prio_ctrl
vi0_prio_ctrl
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:20] - reserved
[19:16] RW outstanding_max AXI Outstanding
15
[15] RW vi15_prio_ctrl 0
1

02 (2010-01-19) 6-65

Hi3520
6
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1

6-66 02 (2010-01-19)

Hi3520
6
0
1
2
1
1
1
0
1
VIn_LUM_COEF0
VIn_LUM_COEF0 0
lum_coef0lum_coef7 512
1/2 lum_coef0lum_coef7160145254
1450160

0x00FC+n%0x1000 VIn_LUM_COEF0 0x0000_0210
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved lum_coef1 reserved lum_coef0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
[31:26] - reserved
[25:16] RW lum_coef1 1 0
[15:10] - reserved
[9:0] RW lum_coef0 0-16
VIn_LUM_COEF1
VIn_LUM_COEF1 1

02 (2010-01-19) 6-67

Hi3520
6

0x0100+n%0x1000 VIn_LUM_COEF1 0x00FE_0091
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1
[31:26] - reserved
[25:16] RW lum_coef3 3 254
[15:10] - reserved
[9:0] RW lum_coef2 2 145
VIn_LUM_COEF2
VIn_LUM_COEF2 2

0x0104+n%0x1000 VIn_LUM_COEF2 0x0000_0091
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1
[31:26] - reserved
[25:16] RW lum_coef5 5 0
[15:10] - reserved
[9:0] RW lum_coef4 4 145
VIn_LUM_COEF3
VIn_LUM_COEF3 3

6-68 02 (2010-01-19)

Hi3520
6

0x0108+n%0x1000 VIn_LUM_COEF3 0x0000_0210
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
[31:26] - reserved
[25:16] RW lum_coef7 7 0
[15:10] - reserved
[9:0] RW lum_coef6 6-16
VIn_CHROMA_COEF0
VIn_CHROMA_COEF0 0
chroma_coef0chroma_coef3 512
1/2 chroma_coef0chroma_coef3148171148
45
chroma_coef0chroma_coef3-32416
160-32

02 (2010-01-19) 6-69

Hi3520
6

0x010C+n%0x1000 VIn_CHROMA_COEF0 0x00AB_0094
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved chroma_coef1 reserved chroma_coef0
Reset 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0
[31:26] - reserved
[25:16] RW chroma_coef1 1 171
[15:10] - reserved
VIn_CHROMA_COEF1
VIn_CHROMA_COEF1 1

0x0110+n%0x1000 VIn_CHROMA_COEF1 0x002D_0094
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved chroma_coef3 reserved chroma_coef2
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0
[31:26] - reserved
[15:10] - reserved

6-70 02 (2010-01-19)

Hi3520
6
6.2 VOU
6.2.1
VOUVideo Output Unit 3
HD AD SD VOU 8
3 4 1 VOU 3
BT.1120BT.656 RGB CVBSS-
VideoYPbPrRGB
6.2.2
VOU
z 2

10bit ITU-R BT.1120/YCbCr 4:2:2
8bit ITU-R BT.656/YCbCr 4:2:2 PAL/NTSC
@27MHz
30bit RGB

M-NTSCNTSC-J
BDGHIPALNPALNcPALMPAL
S-video
YPbPr
VGA
z 8

3
Semi-Planar YCbCr4:2:2Semi-Planar YCbCr4:2:0
alpha
2 4
8 4 YCbCr4:2:2 YCbCr4:2:0
2 32
4 4 YCbCr4:2:2 2
32
4 2 YCbCr4:2:0 2
32
2 de-interlace2 4
1440%1152 32%32

02 (2010-01-19) 6-71

Hi3520
6
3
Semi-Planar YCbCr4:2:2Semi-Planar YCbCr4:2:0
alpha
720%576 32%32
0
16bit ARGB1555

alpha alpha
BT.601 BT.709
1 0
2 0
3 0
0
z
AYCbCr4444
3 Mixer1 Mixer2 Mixer3

Mixer1 24 0 1

Mixer2 24 1 2

Mixer3 24 3

z 3

BT.1120
RGB
YPbPr 1080i 720p
VGA 1280%1024@60Hz
YCbCr to RGB
//
Gamma

VGA 800%600@60Hz
CVBS

6-72 02 (2010-01-19)

Hi3520
6
YCbCr to RGB
//
Gamma

CVBS NTSC/PAL
YCbCr to RGB
//
6.2.3
VOU 6-8
6-8 VOU
clk_vo0out O BT.656 VO0CK

clk_vo1out O BT.1120 VO1CK

vo_vga0_hsync O VO1DAT0
vo_vga0_vsync O VO1DAT1
vo_vga0_dv O VORGBDV
vo_vga1_hsync O VO1DAT13
vo_vga1_vsync O VO1DAT14
vo_656[0] VO0DAT0
vo_656[1] VO0DAT1
vo_656[2] VO0DAT2
vo_656[3] VO0DAT3
O BT.656
vo_656[4] VO0DAT4
vo_656[5] VO0DAT5
vo_656[6] VO0DAT6
vo_656[7] VO0DAT7
vo_1120[0] O BT.1120 VO1DAT0
vo_1120[1] VO1DAT1
vo_1120[2] VO1DAT2
vo_1120[3] VO1DAT3

02 (2010-01-19) 6-73

Hi3520
6
vo_1120[4] VO1DAT4
vo_1120[5] VO1DAT5
vo_1120[6] VO1DAT6
vo_1120[7] VO1DAT7
vo_1120[8] VO1DAT8
vo_1120[9] VO1DAT9
vo_1120[10] VO1DAT10
vo_1120[11] VO1DAT11
vo_1120[12] VO1DAT12
vo_1120[13] VO1DAT13
vo_1120[14] VO1DAT14
vo_1120[15] VO1DAT15
vo_dig0_g_y[0] VO0DAT7
O RGB G
vo_dig0_b_Pb[0] VO1DAT9
O RGB B
vo_dig0_b_Pb[7] GPIO3_0
vo_dig0_r_Pr[0] O RGB R VO0CK
vo_dig0_r_Pr[1] VO0DAT0

6-74 02 (2010-01-19)

Hi3520
6
VOU 6-9
6-9 VOU
vo_dac0 O DACVGA1R
vo_dac1 O DACVGA1G
vo_dac2 O DACVGA1B
vo_dac3 O / DACVGA0R
vo_dac4 O / DACVGA0G
vo_dac5 O DACVGA0B
6.2.4
VOU
VOU 6-32 VOMUX

02 (2010-01-19) 6-75

Hi3520
6
6-32 VOU
VOU {pdata_hd[19:12],pdata_hd[9,2]}
vo_1120 VO/DAC
VOU_
CORE vo_dig_r_pr
pdata_hd[29:0]
vo_dig_g_y RGB
vo_dig_b_pb
pdata_hd[29:0]
vo_dac0
DHD sel_0
VGA
mux vo_dac1
/YPbPr
HDATE sel_1
vo_dac2
pdata_ad[9:2]
vo_656 BT.656
DAD DATE_AD sel_00

VGA R
mux vo_dac3 /CVBS_AD
pdata_ad[9:0]
sel_01 /AD S-Video Y
pdata_ad[29:20]
sel_10
pdata_ad[19:10]
sel_10
mux CVBS_SD
DSD DATE_SD sel_00 vo_dac4 /VGA G
/SD S-Video Y
pdata_ad[9:0]
sel_01
pdata_ad[9:0]
sel_10
SD S-Video C
date_sd_sv_c[9:0] mux vo_dac5 /AD S-Video C
sel_00
date_ad_sv_c[9:0] /VGA B
sel_01
1. De-interlace
De-interlace 2
z 2
z 4
De-interlace 2

2
2 4
2.

6-76 02 (2010-01-19)

Hi3520
6
VOU 8 4 2 32 FIR

z 8 32 FIR
z 4 32 FIR
z YCbCr4:2:2 4 32 FIR
z YCbCr4:2:0 2 32 FIR
1. Alpha
VOU 5 0 1 2 3
alpha 129 alpha
z alpha alpha
z alpha 2
alpha
alpha
nn22 n alpha n alpha

alpha alpha alpha
1
alpha RGB1555 alpha 1bit bit

alpha alpha alpha alpha
alpha alpha0 alpha1
alpha 6-33

02 (2010-01-19) 6-77

Hi3520
6
6-33 alpha

alpha

1alpha pixel_alpha=1
alpha
pixel_alpha=key_alpha=0

alpha=pixel_alphagalpha
alpha
pixel_alpha alpha
galpha alpha
key_alpha alpha 0
2.

alpha 0

3 6-34
z
z
z

6-78 02 (2010-01-19)

Hi3520
6
z 00
z
6-34 3

vhdladdr VHDDFPOS

VHDSFPOS
ih vact
VHDVFPOS oh

VHDVLPOS

iw
stride
ow
hact
VHDDLPOS
VOU YCbCr RGBRGB YCbCr

z YCbCr RGB
YCbCr VGA YCbCr
RGB
z RGB YCbCr
RGB TV YCbCr 4:2:2
YCbCr RGB
R'255 coef 00 coef 01 coef 02 Y 'in _ dc0

G '255 = coef 10 coef 11 coef 12 Cb in _ dc1

B'255 coef 20 coef 21 coef 22 Cr in _ dc 2
RGB YCbCr

02 (2010-01-19) 6-79

Hi3520
6
Y ' out _ dc0 coef 00 coef 01 coef 02 R'255

Cb = out _ dc1 + coef 10 coef 11 coef 12 G '255

Cr out _ dc 2 coef 20 coef 21 coef 22 B'255
VOU 17

VOU
z 0 1 2
3
z
z
z
z
6.2.5
Surface
Surface 6-35
z surface
z surface regup

6-80 02 (2010-01-19)

Hi3520
6
6-35 Surface
Surface 0
Surface

......
Surface0Display Channel0
Surfaceregup
Display Channel0vtthdint
surface0 display channel0 surface0 display channel0

display channel0 vtthdint

2 surface
z working register
z buffered register
buffered register buffered
register working registerSurface 6-36

02 (2010-01-19) 6-81

Hi3520
6
6-36 Surface
ffc ffc ffc ffc

Display Timing frame1 frame2 frame3
Bufferred Register frame1 frame2 frame3
Working Register frame1 frame2 frame3

regup regup regup

6-37 regup_rate 6-37
ffc /
6-37 Surface
ffc ffc ffc ffc

Tfield1 Bfield1 Tfield2
Display Timing
Bufferred Register Tfield1 Bfield1 Tfield2
Working Register Tfield1 Bfield1 Tfield2

regup regup regup
Display channel
Display channel 2
z CSCCLIPGamma

z

CBM
Mixer1 Mixer2 surface 5 surface 2
MixerSurface Mixer
surface surface Mixer

2 CBCFG bit[29:24] surface Mixer

6-82 02 (2010-01-19)

Hi3520
6
3 surface
4 surface
----
Mixer1 Mixer2 surface CBCFG bit[14:0]

Mixer1 surface Mixer2 surface
surface Mixer
Mixer1 VDC_HDGDC_G0 GDC_G2Mixer2

VDC_AD GDC_G1
z VDC_HD,GDC_G0 GDC_G2 Mixer1
sur_attr0 = 0; sur_attr2 = 0; sur_attr4 = 0;
z VDC_AD GDC_G1 Mixer2

sur_attr1 = 1; sur_attr3 = 1;
z
mixer_prio0 = 1; mixer_prio1 = 3; mixer_prio2 =5; mixer_prio3 =
2;mixer_prio4 =4;
CPU APB Slave

AXI Master
AXI Master
6-38
APB Slave

02 (2010-01-19) 6-83

Hi3520
6
6-38

VHDHCOEFADVHDVCOEFAD

VO_PARAUP[vhd_hcoef_upd]
VO_PARAUP[vhd_vcoef_upd]
VOU

6.2.6
VOU 6-10
6-10 VOU 0x2013_0000
0x0000 VO_CTRL VO 6-98
0x0004 VO_INTSTA VO 6-98
0x0008 VO_INTMSK VO 6-100
0x000C VO_VERSION1 VO 1 6-102

6-84 02 (2010-01-19)

Hi3520
6
0x0010 VO_VERSION2 VO 2 6-103
0x001C VO_MUX VO 6-103
0x002C VO_PARAUP Gamma 6-104
0x0030 VHDHCOEFAD VHD 6-106

0x0034 VHDVCOEFAD VHD 6-106

0x0038 VADHCOEFAD VAD 6-106

0x003C VADVCOEFAD VAD 6-107

0x0040 DHDACCAD DHD ACC 6-107
0x0044 DADACCAD DAD ACC 6-107
0x0100 VHDCTRL VHD 6-108
0x0104 VHDUPD VHD 6-109
0x0108 VHDLADDR VHD De-interlace 6-110

0x010C VHDLCADDR VHD De-interlace 6-110

0x0110 VHDCADDR VHD De-interlace 6-110

0x0114 VHDCCADDR VHD De-interlace 6-111

0x0118 VHDNADDR VHD De-interlace 6-111

0x011C VHDNCADDR VHD De-interlace 6-112

0x0120 VHDSTRIDE VHD 6-112
0x0124 VHDCBMPARA VHD 6-112

0x0128 VHDORESO VHD 6-113

0x012C VHDIRESO VHD 6-113

02 (2010-01-19) 6-85

Hi3520
6
0x0130 VHDSFPOS VHD 6-114

0x0134 VHDDFPOS VHD 6-115

0x0138 VHDDLPOS VHD 6-115

0x013C VHDVFPOS VHD 6-116

0x0140 VHDVLPOS VHD 6-116

0x0144 VHDBK VHD 6-117
0x0150 VHDLMSP VHD 6-117
0x0154 VHDCHMSP VHD 6-118
0x0158 VHDLMHSP VHD 6-119

0x015C VHDLMVSP VHD 6-119

0x0160 VHDCHMHSP VHD 6-120
0x0164 VHDCHMVSP VHD 6-120
0x0170 VHDDIECTRL VHD De-interlace 6-121

0x0174 VHDDIETHD VHD De-interlace 6-123

0x0178 VHDDIEADDR VHD De-interlace buffer 6-123

0x0180+n VHDDIETSMIX VHD De-interlace 6-124

10x4
0x0190+n VHDDIETFLT VHD De-interlace 6-124

20x4
0x01A0+n VHDDIEVFLT VHD De-interlace 6-125

30x4
0x01F0 VHDSTATUS VHD 6-126

6-86 02 (2010-01-19)

Hi3520
6
0x0200 VADCTRL VAD 6-126
0x0204 VADUPD VAD 6-128
0x0208 VADLADDR VAD De-interlace 6-128

0x020C VADLCADDR VAD De-interlace 6-128

0x0210 VADCADDR VAD De-interlace 6-129

0x0214 VADCCADDR VAD De-interlace 6-129

0x0218 VADNADDR VAD De-interlace 6-130

0x021C VADNCADDR VAD De-interlace 6-130

0x0220 VADSTRIDE VAD 6-130
0x0224 VADCBMPARA VAD 6-131

0x0228 VADORESO VAD 6-131

0x022C VADIRESO VAD 6-132

0x0230 VADSFPOS VAD 6-133

0x0234 VADDFPOS VAD 6-133

0x0238 VADDLPOS VAD 6-134

0x023C VADVFPOS VAD 6-134

0x0240 VADVLPOS VAD 6-135

0x0244 VADBK VAD 6-135
0x0250 VADLMSP VAD 6-136

02 (2010-01-19) 6-87

Hi3520
6
0x0254 VADCHMSP VAD 6-137
0x0258 VADLMHSP VAD 6-138

0x025C VADLMVSP VAD 6-138

0x0260 VADCHMHSP VAD 6-139
0x0264 VADCHMVSP VAD 6-139
0x0270 VADDIECTRL VAD De-interlace 6-140

0x0274 VADDIETHD VAD De-interlace 6-142

0x0278 VADDIEADDR VAD De-interlace buffer 6-142

0x0280+n VADDIETSMIX VAD De-interlace 6-143

10x4
0x0290+n VADDIETFLT VAD De-interlace 6-143

20x4
0x02A0+n VADDIEVFLT VAD De-interlace 6-144

30x4
0x02F0 VADSTATUS VAD 6-145
0x0300 VSDCTRL VSD 6-145
0x0304 VSDUPD VSD 6-147
0x0310 VSDADDR VSD 6-147
0x0314 VSDCADDR VSD 6-147
0x0320 VSDSTRIDE VSD 6-148
0x0324 VSDCBMPARA VSD 6-148

0x0328 VSDORESO VSD 6-149

0x032C VSDIRESO VSD 6-149

0x0330 VSDSFPOS VSD 6-150

6-88 02 (2010-01-19)

Hi3520
6
0x0334 VSDDFPOS VSD 6-150

0x0338 VSDDLPOS VSD 6-151

0x033C VSDVFPOS VSD 6-151

0x0340 VSDVLPOS VSD 6-152

0x0344 VSDBK VSD 6-152
0x0400 G0CTRL G0 6-153
0x0404 G0UPD G0 6-154
0x0408 G0ADDR G0 6-154
0x040C G0STRIDE G0 6-155
0x0410 G0CBMPARA G0 6-155

0x0414 G0CKEYMAX G0 color key 6-156

0x0418 G0CKEYMIN G0 color key 6-156

0x041C G0IRESO G0 6-157

0x0420 G0ORESO G0 6-158

0x0424 G0SFPOS G0 6-158

0x0428 G0DFPOS G0 6-159

0x042C G0DLPOS G0 6-159

0x0500 G1CTRL G1 6-160
0x0504 G1UPD G1 6-160
0x0508 G1ADDR G1 6-161

02 (2010-01-19) 6-89

Hi3520
6



0x051C G1IRESO G1 6-164

0x0520 G1ORESO G1 6-165

0x0524 G1SFPOS G1 6-165

0x0528 G1DFPOS G1 6-166

0x052C G1DLPOS G1 6-166

0x0600 G2CTRL G2 6-167
0x0604 G2UPD G2 6-167
0x0608 G2ADDR G2 6-168



0x061C G2IRESO G2 6-171

0x0620 G2ORESO G2 6-172

0x0624 G2SFPOS G2 6-172

6-90 02 (2010-01-19)

Hi3520
6
0x0628 G2DFPOS G2 6-173

0x062C G2DLPOS G2 6-173

0x0700 G3CTRL G3 6-174
0x0704 G3UPD G3 6-174
0x0708 G3ADDR G3 6-175



0x071C G3IRESO G3 6-178

0x0720 G3ORESO G3 6-179

0x0724 G3SFPOS G3 6-179

0x0728 G3DFPOS G3 6-180

0x072C G3DLPOS G3 6-180

0x0800 HCCTRL HC 6-181
0x0804 HCUPD HC 6-181
0x0808 HCADDR HC 6-182
0x080C HCSTRIDE HC 6-182
0x0810 HCCBMPARA HC 6-183

0x0814 HCCKEYMAX HC color key 6-184

0x0818 HCCKEYMIN HC color key 6-184

02 (2010-01-19) 6-91

Hi3520
6
0x081C HCIRESO HC 6-185

0x0820 HCORESO HC 6-186

0x0824 HCSFPOS HC 6-186

0x0828 HCFPOS HC 6-187

0x082C HCDLPOS HC 6-187

0x0B00 CBMBKG1 Mixer1 6-188

0x0B04 CBMBKG2 Mixer2 6-188

0x0B0C CBCFG Colorbar 6-188
0x0C00 DHDCTRL HD 6-191

0x0C04 DHDVSYNC HD 6-193

0x0C08 DHDHSYNC1 HD 1 6-193

0x0C0C DHDHSYNC2 HD 2 6-194

0x0C10 DHDVPLUS HD 6-194

0x0C14 DHDPWR HD 6-195

0x0C18 DHDFIFOTHD HD FIFO 6-195

0x0C1C DHDVTTHD HD 6-196

0x0C20 DHDCSCIDC HD 6-196

0x0C24 DHDCSCODC HD 6-197

6-92 02 (2010-01-19)

Hi3520
6
0x0C28 DHDCSCP0 HD 0 6-197

0x0C2C DHDCSCP1 HD 1 6-198




0x0C3C DHDCLIPL HD 6-200

0x0C40 DHDCLIPH HD 6-200

0x0C44 DHDGMMTHD1 HD Gamma 1 6-201

0x0C48 DHDGMMTHD2 HD Gamma 2 6-201

0x0C50+t DHDGMMLOWt HD Gamma 6-201

10x4 low
0x0C60+t DHDGMMMEDt HD Gamma 6-202

20x4 med
0x0C70+t DHDGMMHIGHt HD Gamma 6-202

30x4 high
0x0C80+t DHDGMMMLt HD Gamma 6-203

40x4 middle_low
0x0CA0+t DHDGMMMHt HD Gamma 6-203

50x4 middle_high
0x0CB0 DHDGMM3LOW HD Gamma 6-204

0x0CB4 DHDGMM3MED HD Gamma 6-204

0x0CB8 DHDGMM3HIGH HD Gamma 6-205

0x0CC0 DHDGMM8MLOW HD Gamma 8 6-205

02 (2010-01-19) 6-93

Hi3520
6
0x0CC4 DHDGMM8MHIGH HD Gamma 8 6-206

0x0CE0 CCDIMGMOD 6-206
0x0CF0 DHDSTATE HD 6-207
0x0D00 DADCTRL AD 6-207

0x0D04 DADVSYNC AD 6-209

0x0D08 DADHSYNC1 AD 1 6-210

0x0D0C DADHSYNC2 AD 2 6-210

0x0D10 DADVPLUS AD 6-211

0x0D14 DADPWR AD 6-211

0x0D18 DADFIFOTHD AD FIFO 6-211

0x0D1C DADVTTHD AD 6-212

0x0D20 DADCSCIDC AD 6-212

0x0D24 DADCSCODC AD 6-213

0x0D28 DADCSCP0 AD 0 6-213

0x0D2C DADCSCP1 AD 1 6-214




6-94 02 (2010-01-19)

Hi3520
6
0x0D3C DADCLIPL AD 6-216

0x0D40 DADCLIPH AD 6-216

0x0D44 DADGMMTHD1 AD Gamma 1 6-217

0x0D48 DADGMMTHD2 AD Gamma 2 6-217

0x0D50+t DADGMMLOWt AD Gamma 6-218

10x4 low
0x0D60+t DADGMMMEDt AD Gamma 6-218

20x4 med
0x0D70+t DADGMMHIGHt AD Gamma 6-219

30x4 high
0x0D80+t DADGMMMLt AD Gamma 6-219

40x4 middle_low
0x0DA0+t DADGMMMHt AD Gamma 6-220

50x4 middle_high

0x0DB0 DADGMM3LOW AD Gamma 6-220

0x0DB4 DADGMM3MED AD Gamma 6-221

0x0DB8 DADGMM3HIGH AD Gamma 6-221

0x0DC0 DADGMM8MLOW AD Gamma 8 6-222

0x0DC4 DADGMM8MHIGH AD Gamma 8 6-222

0x0DF0 DADSTATE AD 6-222
0x0E00 DSDCTRL SD 6-223

0x0E04 DSDVSYNC SD 6-225

0x0E08 DSDHSYNC1 SD 1 6-225

02 (2010-01-19) 6-95

Hi3520
6
0x0E0C DSDHSYNC2 SD 2 6-226

0x0E10 DSDVPLUS SD 6-226

0x0E14 DSDPWR SD 6-227

0x0E18 DSDFIFOTHD SD FIFO 6-227

0x0E1C DSDVTTHD SD 6-228

0x0E20 DSDCSCIDC SD 6-228

0x0E24 DSDCSCODC SD 6-229

0x0E28 DSDCSCP0 SD 0 6-229

0x0E2C DSDCSCP1 SD 1 6-230




0x0E3C DSDCLIPL SD 6-232

0x0E40 DSDCLIPH SD 6-232

0x0EF0 DSDSTATE SD 6-233
0x0F00+ CCDSPOSm m 6-233

m0x4
0x0F80+ CCDFPOSm m 6-234

m0x4
0x1000 VHDHLCOEF VHD 6-235

0x111C

6-96 02 (2010-01-19)

Hi3520
6
0x1200 VHDHCCOEF VHD 6-236

0x128C
0x1300 VHDVLCOEF VHD 6-236

0x138C
0x1400 VHDVCCOEF VHD 6-237

0x148C
0x1500 VADHLCOEF VAD 6-238

0x161C
0x1700 VADHCCOEF VAD 6-238

0x178C
0x1800 VADVLCOEF VAD 6-239

0x188C
0x1900 VADVCCOEF VAD 6-240

0x198C
0x2300 VHDMIMGSPOSp VHD De-interlace p 6-240

0x237C
0x2380 VHDMIMGFPOSp VHD De-interlace p 6-241

0x23FC
0x2400 VADMIMGSPOSp VAD De-interlace p 6-242

0x247C
0x2480 VADMIMGFPOSp VAD De-interlace p 6-242

0x24FC
VOU 6-11
6-11 VOU
n1 03 De-interlace
n2 03 De-interlace
n3 03 De-interlace
t1 02 low
t2 02 med
t3 02 high

02 (2010-01-19) 6-97

Hi3520
6
t4 02 middle_low

t5 02 middle_high

m 031
6.2.7
VO_CTRL
VO_CTRL VO

0x0000 VO_CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved outstd_wid0 reserved outstd_rid0 reserved arb_mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:20] - reserved
[19:16] RW outstd_wid0 AXI ID0 outstanding
[15:12] - reserved
[11:8] RW outstd_rid0 AXI ID0 outstanding
[7:4] - reserved
VO Surface
0x0
[3:0] - arb_mode
0x1

VO_INTSTA
VO_INTSTA VO 1

6-98 02 (2010-01-19)

Hi3520
6

0x0004 VO_INTSTA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vhd_st_wr_int
vad_st_wr_int
dhdvtthd_int
dadvtthd_int
dsdvtthd_int
dhduf_int
daduf_int
dsduf_int
vhdrr_int
vadrr_int
vsdrr_int
reserved
g3rr_int
g2rr_int
g1rr_int
g0rr_int
hcrr_int
be_int
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AXI_Master
[31] WC be_int 0
1
[30] - reserved
VHD
[29] WC vhd_st_wr_int 0
1
VAD
[28] WC vad_st_wr_int 0
1

[27] WC hcrr_int 0
1
G3 3
[26] WC g3rr_int 0
1
G2 2
[25] WC g2rr_int 0
1
G1 1
[24] WC g1rr_int 0
1
G0 0
[23] WC g0rr_int 0
1

02 (2010-01-19) 6-99

Hi3520
6
VDC_HD
[22] WC vhdrr_int 0
1
VDC_AD
[21] WC vadrr_int 0
1
VDC_SD
[20] WC vsdrr_int 0
1
[19:6] - reserved
HD
[5] WC dhduf_int 0
1
HD
[4] WC dhdvtthd_int 0
1
AD
[3] WC daduf_int 0
1
AD
[2] WC dadvtthd_int 0
1
SD
[1] WC dsduf_int 0
1
SD
[0] WC dsdvtthd_int 0
1
VO_INTMSK
VO_INTMSK VO VO_INTSTA

6-100 02 (2010-01-19)

Hi3520
6

0x0008 VO_INTMSK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vhd_st_wr_intmask
vad_st_wr_intmask
dadvtthdg_intmsk
dhdvtthd_intmsk
dsdvtthd_intmsk
dhduf_intmsk
daduf_intmsk
dsduf_intmsk
vhdrr_intmsk
vadrr_intmsk
vsdrr_intmsk
g3rr_intmsk
g2rr_intmsk
g1rr_intmsk
g0rr_intmsk
hcrr_intmsk
be_intmsk
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AXI_Master
[31] RW be_intmsk 0
1
[30] - reserved
VHD
[29] RW vhd_st_wr_intmask 0
1
VAD
[28] RW vad_st_wr_intmask 0
1

[27] RW hcrr_intmsk 0
1
G3
[26] RW g3rr_intmsk 0
1
G2
1
G1
1

02 (2010-01-19) 6-101

Hi3520
6
G0
1
VDC_HD
[22] RW vhdrr_intmsk 0
1
VDC_AD
[21] RW vadrr_intmsk 0
1
VDC_SD
[20] RW vsdrr_intmsk 0
1
[19:6] - reserved
HD
[5] RW dhduf_intmsk 0
1
HD
[4] RW dhdvtthd_intmsk 0
1
AD
[3] RW daduf_intmsk 0
1
AD
[2] RW dadvtthdg_intmsk 0
1
SD
[1] RW dsduf_intmsk 0
1
SD
[0] RW dsdvtthd_intmsk 0
1
VO_VERSION1
VO_VERSION1 VO 1

6-102 02 (2010-01-19)

Hi3520
6

0x000C VO_VERSION1 0x7675_6F76
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name voversion0
Reset 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 0
[31:0] RO voversion0 VO
VO_VERSION2
VO_VERSION2 VO 2

0x0010 VO_VERSION2 0x3030_3034
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name voversion1
Reset 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0
[31:0] RO voversion1 VO
VO_MUX
VO_MUX VO

0x001C VO_MUX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bt1120_mu
dac5_mux
dac4_mux
dac3_mux
dac2_mux
dac1_mux
dac0_mux
reserved
reserved
Name reserved
x
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:14] - reserved

02 (2010-01-19) 6-103

Hi3520
6
VODAC5
00SD S-Video C
[13:12] RW dac5_mux 01AD S-Video C
10AD VGA B
11
VODAC4
00SD CVBS SD S-Video Y

[11:10] RW dac4_mux
01SD BT.656
10AD VGA G
11
VODAC3
00AD CVBS AD S-Video Y

[9:8] RW dac3_mux
01AD BT.656
10AD VGA R
11
[7] - reserved
BT.1120
[6] RW bt1120_mux 0BT.1120 INTF
1BT.1120 IPI
[5:3] - reserved
VODAC2
[2] RW dac2_mux 0HD VGA B
1HD YPbPr Pb
VODAC1
[1] RW dac1_mux 0HD VGA G
1HD YPbPr Y
VODAC0
[0] RW dac0_mux 0HD VGA R
1HD YPbPr Pr
VO_PARAUP
VO_PARAUP Gamma VO AXI
Master APB Slave

6-104 02 (2010-01-19)

Hi3520
6

0x002C VO_PARAUP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vhd_vcoef_upd
vhd_hcoef_upd
vad_vcoef_upd
vad_hcoef_upd
dhd_acc_upd
dad_acc_upd
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] - reserved
DAD ACC
[5] RW dad_acc_upd 0
1
DHD ACC
[4] RW dhd_acc_upd 0
1
VAD

[3] RW vad_vcoef_upd
0
1
VAD

[2] RW vad_hcoef_upd
0
1
VHD

[1] RW vhd_vcoef_upd
0
1
VHD

[0] RW vhd_hcoef_upd
0
1

02 (2010-01-19) 6-105

Hi3520
6
VHDHCOEFAD
VHDHCOEFAD VHD

0x0030 VHDHCOEFAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW coef_addr local memory
VHDVCOEFAD
VHDVCOEFAD VHD

0x0034 VHDVCOEFAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VADHCOEFAD
VADHCOEFAD VAD

0x0038 VADHCOEFAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6-106 02 (2010-01-19)

Hi3520
6
VADVCOEFAD
VADVCOEFAD VAD

0x003C VADVCOEFAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DHDACCAD
DHDACCAD DHD ACC

0x0040 DHDACCAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DADACCAD
DADACCAD DAD ACC

02 (2010-01-19) 6-107

Hi3520
6

0x0044 DADACCAD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name coef_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VHDCTRL
VHDCTRL VHD

0x0100 VHDCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
chm_rmode
bfield_first
regup_rate
lm_rmode
vhd_en
Name reserved reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW vhd_en 0
1
[30:18] - reserved
Surface
[17] RW regup_rate 0
1
TTop FieldBBottom Field)

[16] RW bfield_first 0T0B0T1B1T0B0
1B0T0B1T1B0T0

6-108 02 (2010-01-19)

Hi3520
6

00 buffer
[15:14] RW lm_rmode 01 buffer
10
11

00 buffer
[13:12] RW chm_rmode 01 buffer
10
11
[11:4] - reserved

0x3SPYCbCr4:2:0
[3:0] RW ifmt
0x4SPYCbCr4:2:2(1x2 )

VHDUPD
VHDUPD VHD

0x0104 VHDUPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved regup
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

02 (2010-01-19) 6-109

Hi3520
6
VHDLADDR
VHDLADDR VHD De-interlace package
buffer semi-planar buffer

0x0108 VHDLADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdladdr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdladdr De-interlace
VHDLCADDR
VHDLCADDR VHD De-interlace package
semi-planar buffer

0x010C VHDLCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdlcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdlcaddr De-interlace
VHDCADDR
VHDCADDR VHD De-interlace package

6-110 02 (2010-01-19)

Hi3520
6

0x0110 VHDCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdcaddr De-interlace
VHDCCADDR
VHDCCADDR VHD De-interlace package
semi-planar buffer

0x0114 VHDCCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdccaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdccaddr De-interlace
VHDNADDR
VHDNADDR VHD De-interlace package

0x0118 VHDNADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdnaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdnaddr De-interlace

02 (2010-01-19) 6-111

Hi3520
6
VHDNCADDR
VHDNCADDR VHD De-interlace package
semi-planar buffer

0x011C VHDNCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdncaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vhdncaddr De-interlace
VHDSTRIDE
VHDSTRIDE VHD

0x0120 VHDSTRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vhdcstride vhdstride
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
buffer stride semi-planar word

[31:16] RW vhdcstride


[15:0] RW vhdstride

VHDCBMPARA
VHDCBMPARA VHD

6-112 02 (2010-01-19)

Hi3520
6

0x0124 VHDCBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved galpha
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
alpha
[7:0] RW galpha
01270 127
VHDORESO
VHDORESO VHD

0x0128 VHDORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oh reserved ow
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

VHDIRESO
VHDIRESO VHD

02 (2010-01-19) 6-113

Hi3520
6
z YCbCr4:2:0
4
z YCbCr4:2:0 2


0x012C VHDIRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved ih reserved iw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

[27:16] RW ih
1
[15:12] - reserved

[11:0] RW iw
1
VHDSFPOS
VHDSFPOS VHD

0x0130 VHDSFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved src_yfpos reserved src_xfpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
[27:16] RW src_yfpos
0
[15:12] - reserved

6-114 02 (2010-01-19)

Hi3520
6
X
[11:0] RW src_xfpos
0
VHDDFPOS
VHDDFPOS VHD


0x0134 VHDDFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved disp_yfpos reserved disp_xfpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW disp_yfpos
[15:12] RW reserved
[11:0] RW disp_xfpos
VHDDLPOS
VHDDLPOS VHD


0x0138 VHDDLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved disp_ylpos reserved disp_xlpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW disp_ylpos
[15:12] - reserved
[11:0] RW disp_xlpos

02 (2010-01-19) 6-115

Hi3520
6
VHDVFPOS
VHDVFPOS VHD


0x013C VHDVFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved video_yfpos reserved video_xfpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW video_yfpos
[15:12] - reserved
[11:0] RW video_xfpos
VHDVLPOS
VHDVLPOS VHD


0x0140 VHDVLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved video_ylpos reserved video_xlpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW video_ylpos
[15:12] - reserved
[11:0] RW video_xlpos

6-116 02 (2010-01-19)

Hi3520
6
VHDBK
VHDBK VHD

0x0144 VHDBK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vbk_alpha vbk_y vbk_cb vbk_cr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:24] RW vbk_alpha
0128
[23:16] RW vbk_y Y
[15:8] RW vbk_cb Cb
[7:0] RW vbk_cr Cr
VHDLMSP
VHDLMSP VHD

0x0150 VHDLMSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
shift_field
hlmsc_en
vlmsc_en
hlmid_en
vlmid_en
Name reserved fld_offset
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31] RW hlmsc_en 0
1

[30] RW vlmsc_en 0
1

02 (2010-01-19) 6-117

Hi3520
6

[29] RW hlmid_en 0
1

[28] RW vlmid_en 0
1
[27:17] - reserved

[16] RW shift_field 0
1

[15:0] RW fld_offset 4.12

VHDCHMSP
VHDCHMSP VHD

0x0154 VHDCHMSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hchmsc_en
vchmsc_en
shift_field
hlmid_en
vlmid_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31] RW hchmsc_en 0
1

[30] RW vchmsc_en 0
1

6-118 02 (2010-01-19)

Hi3520
6

[29] RW hlmid_en 0
1

[28] RW vlmid_en 0
1
[27:17] - reserved

1


VHDLMHSP
VHDLMHSP VHD

0x0158 VHDLMHSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved lm_hphase lm_hratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW lm_hphase 0.12
[15:0] RW lm_hratio 4.12
VHDLMVSP
VHDLMVSP VHD

02 (2010-01-19) 6-119

Hi3520
6

0x015C VHDLMVSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved lm_vphase lm_vratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW lm_vphase 0.12
[15:0] RW lm_vratio 4.12
VHDCHMHSP
VHDCHMHSP VHD

0x0160 VHDCHMHSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved chm_hphase chm_hratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW chm_hphase 0.12
[15:0] RW chm_hratio 4.12
VHDCHMVSP
VHDCHMVSP VHD

6-120 02 (2010-01-19)

Hi3520
6

0x0164 VHDCHMVSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name chm_hphase chm_vratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:29] - reserved
[15:0] RW chm_vratio 4.12
VHDDIECTRL
VHDDIECTRL VHD De-interlace

0x0170 VHDDIECTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
lm_mov_tsmix_en
lm_st_tsmix_en
die_reff_cfg_en
die_chroma_en
chm_tsmix_en
die_chmmode
die_luma_en
die_rf_mode
die_lmmode
die_reff_cfg
stinfo_stop
lm_tflt_en
stinfo_rst
reserved
reserved
reserved
reserved
die_frt
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
De-interlace
[31] RW die_luma_en 0
1
De-interlace
[30] RW die_chroma_en 0
1
[29] - reserved

02 (2010-01-19) 6-121

Hi3520
6
De-interlace
[28] RW die_frt 0=
1=2
[27] - reserved
De-interlace
[26] RW die_lmmode 04
12
[25] - reserved
De-interlace
[24] RW die_chmmode 04
12
De-interlace4
[23] RW die_rf_mode 0
1 1/2
[22] - reserved

[21] RW lm_mov_tsmix_en 0
1

[20] RW lm_st_tsmix_en 0
1

[19] RW lm_tflt_en 0
1

[18] RW chm_tsmix_en 0
1

[17] RW stinfo_rst 0
1

[16] RW stinfo_stop 0
1
[15:2] - reserved

6-122 02 (2010-01-19)

Hi3520
6

0De-interlace
[1] RW die_reff_cfg_en 1De-interlace die_reff_cfg

De-interlace VHDCTRL[regup_date] 1

De-interlace
0
[0] RW die_reff_cfg
1
die_reff_cfg_en 1
VHDDIETHD
VHDDIETHD VHD De-interlace

0x0174 VHDDIETHD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
st_thd
Name reserved fld_diff_thd med_thd md_thd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:22] - reserved
[21:16] RW fld_diff_thd
[15:12] RW med_thd
[11] - reserved
[10:8] RW st_thd
[7:5] - reserved
[4:0] RW md_thd
VHDDIEADDR
VHDDIEADDR VHD De-interlace buffer

02 (2010-01-19) 6-123

Hi3520
6

0x0178 VHDDIEADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dieaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW dieaddr De-interlace buffer
VHDDIETSMIX
VHDDIETSMIX VHD De-interlace
4 8

0x0180+n10x4 VHDDIETSMIX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tsmix_n7 tsmix_n6 tsmix_n5 tsmix_n4 tsmix_n3 tsmix_n2 tsmix_n1 tsmix_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW tsmix_n7 n1 7n1=03
[27:24] RW tsmix_n6 n1 6n1=03
[23:20] RW tsmix_n5 n1 5n1=03
[19:16] RW tsmix_n4 n1 4n1=03
[15:12] RW tsmix_n3 n1 3n1=03
[11:8] RW tsmix_n2 n1 2n1=03
[7:4] RW tsmix_n1 n1 1n1=03
[3:0] RW tsmix_n0 n1 0n1=03
VHDDIETFLT
VHDDIETFLT VHD De-interlace
4 8

6-124 02 (2010-01-19)

Hi3520
6

0x0190+n20x4 VHDDIETFLT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tflt_n7 tflt_n6 tflt_n5 tflt_n4 tflt_n3 tflt_n2 tflt_n1 tflt_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW tflt_n7 n2 7n2=03
[27:24] RW tflt_n6 n2 6n2=03
[23:20] RW tflt_n5 n2 5n2=03
[19:16] RW tflt_n4 n2 4n2=03
[15:12] RW tflt_n3 n2 3n2=03
[11:8] RW tflt_n2 n2 2n2=03
[7:4] RW tflt_n1 n2 1n2=03
[3:0] RW tflt_n0 n2 0n2=03
VHDDIEVFLT
VHDDIEVFLT VHD De-interlace
4 8

0x01A0+n30x4 VHDDIEVFLT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vflt_n7 vflt_n6 vflt_n5 vflt_n4 vflt_n3 vflt_n2 vflt_n1 vflt_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW vflt_n7 n3 De-interlace 7n3=03

02 (2010-01-19) 6-125

Hi3520
6
VHDSTATUS
VHDSTATUS VHD

0x01F0 VHDSTATUS 0x0800_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
die_ref_field
Name reserved
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] - reserved
De-interlace de-interlace
0
[0] RO die_ref_field
0
1
VADCTRL
VADCTRL VAD

6-126 02 (2010-01-19)

Hi3520
6

0x0200 VADCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
chm_rmode
bfield_first
regup_rate
lm_rmode
vad_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW vad_en 0
1
[30:18] - reserved
Surface
1

1B0T0B1T1B0T0

00 buffer
10
11

00 buffer
10
11
[11:4] - reserved

0x3SPYCbCr4:2:0
[3:0] RW ifmt

02 (2010-01-19) 6-127

Hi3520
6
VADUPD
VADUPD VAD

0x0204 VADUPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

VADLADDR
VADLADDR VAD De-interlace package

0x0208 VADLADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadladdr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadladdr De-interlace
VADLCADDR
VADLCADDR VAD De-interlace package
semi-planar buffer

6-128 02 (2010-01-19)

Hi3520
6

0x020C VADLCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadlcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadlcaddr De-interlace
VADCADDR
VADCADDR VAD De-interlace package

0x0210 VADCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadcaddr De-interlace
VADCCADDR
VADCCADDR VAD De-interlace package
semi-planar buffer

0x0214 VADCCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadccaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadccaddr De-interlace

02 (2010-01-19) 6-129

Hi3520
6
VADNADDR
VADNADDR VAD De-interlace package

0x0218 VADNADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadnaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadnaddr De-interlace
VADNCADDR
VADNCADDR VAD De-interlace package
semi-planar buffer

0x021C VADNCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadncaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vadncaddr De-interlace
VADSTRIDE
VADSTRIDE VAD

6-130 02 (2010-01-19)

Hi3520
6

0x0220 VADSTRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vadcstride vadstride
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:16] RW vadcstride

buffer stride semi-planar

[15:0] RW vadstride
stride word
VADCBMPARA
VADCBMPARA VAD

0x0224 VADCBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
alpha
[7:0] RW galpha
01270 127
VADORESO
VADORESO VAD

02 (2010-01-19) 6-131

Hi3520
6

0x0228 VADORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

VADIRESO
VADIRESO VAD
z YCbCr4:2:0
4
z YCbCr4:2:0 2


0x022C VADIRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

6-132 02 (2010-01-19)

Hi3520
6

[27:16] RW ih
1
[15:12] RW reserved

[11:0] RW iw
1
VADSFPOS
VADSFPOS VAD

0x0230 VADSFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] - reserved
X
[11:0] RW src_xfpos
0
VADDFPOS
VADDFPOS VAD

02 (2010-01-19) 6-133

Hi3520
6

0x0234 VADDFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VADDLPOS
VADDLPOS VAD


0x0238 VADDLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VADVFPOS
VADVFPOS VAD

6-134 02 (2010-01-19)

Hi3520
6

0x023C VADVFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VADVLPOS
VADVLPOS VAD


0x0240 VADVLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VADBK
VADBK VAD

02 (2010-01-19) 6-135

Hi3520
6

0x0244 VADBK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0128
[23:16] RW vbk_y Y
[15:8] RW vbk_cb Cb
[7:0] RW vbk_cr Cr
VADLMSP
VADLMSP VAD

0x0250 VADLMSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
shift_field
hlmsc_en
vlmsc_en
hlmid_en
vlmid_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31] RW hlmsc_en 0
1

[30] RW vlmsc_en 0
1

[29] RW hlmid_en 0
1

6-136 02 (2010-01-19)

Hi3520
6

[28] RW vlmid_en 0
1
[27:17] - reserved

1


VADCHMSP
VADCHMSP VAD

0x0254 VADCHMSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hchmsc_en
vchmsc_en
shift_field
hlmid_en
vlmid_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31] RW hchmsc_en 0
1

[30] RW vchmsc_en 0
1

[29] RW hlmid_en 0
1

02 (2010-01-19) 6-137

Hi3520
6

[28] RW vlmid_en 0
1
[27:17] - reserved

1


VADLMHSP
VADLMHSP VAD

0x0258 VADLMHSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved lm_hphase lm_hratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW lm_hphase 0.12
[15:0] RW lm_hratio 4.12
VADLMVSP
VADLMVSP VAD

6-138 02 (2010-01-19)

Hi3520
6

0x025C VADLMVSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved lm_vphase lm_vratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW lm_vphase 0.12
[15:0] RW lm_vratio 4.12
VADCHMHSP
VADCHMHSP VAD

0x0260 VADCHMHSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved chm_hphase chm_hratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:0] RW chm_hratio 4.12
VADCHMVSP
VADCHMVSP VAD

02 (2010-01-19) 6-139

Hi3520
6

0x0264 VADCHMVSP 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name chm_hphase chm_vratio
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:29] - reserved
[15:0] RW chm_vratio 4.12
VADDIECTRL
VADDIECTRL VAD De-interlace

0x0270 VADDIECTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
lm_mov_tsmix_en
lm_st_tsmix_en
die_reff_cfg_en
die_chroma_en
chm_tsmix_en
die_chmmode
die_luma_en
die_rf_mode
die_lmmode
die_reff_cfg
stinfo_stop
lm_tflt_en
stinfo_rst
reserved
reserved
reserved
reserved
die_frt
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
De-interlace
[31] RW die_luma_en 0
1
De-interlace
[30] RW die_chroma_en 0
1
[29] - reserved

6-140 02 (2010-01-19)

Hi3520
6
De-interlace
[28] RW die_frt 0=
1=2
[27] - reserved
De-interlace
[26] RW die_lmmode 04
12
[25] - reserved
De-interlace
[24] RW die_chmmode 04
12
De-interlace4
[23] RW die_rf_mode 0
1 1/2
[22] - reserved

[21] RW lm_mov_tsmix_en 0
1

[20] RW lm_st_tsmix_en 0
1

[19] RW lm_tflt_en 0
1

[18] RW chm_tsmix_en 0
1

[17] RW stinfo_rst 0
1

[16] RW stinfo_stop 0
1
[15:2] - reserved

02 (2010-01-19) 6-141

Hi3520
6

0De-interlace
[1] RW die_reff_cfg_en 1De-interlace die_reff_cfg

De-interlace VADCTRL[regup_date] 1

De-interlace
0
[0] RW die_reff_cfg
1
die_reff_cfg_en 1
VADDIETHD
VADDIETHD VAD De-interlace

0x0274 VADDIETHD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
st_thd
Name reserved fld_diff_thd med_thd md_thd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:22] - reserved
[21:16] RW fld_diff_thd
[15:12] RW med_thd
[11] - reserved
[10:8] RW st_thd
[7:5] - reserved
[4:0] RW md_thd
VADDIEADDR
VADDIEADDR VAD De-interlace buffer

6-142 02 (2010-01-19)

Hi3520
6

0x0278 VADDIEADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name dieaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW dieaddr De-interlace buffer
VADDIETSMIX
VADDIETSMIX VAD De-interlace
4 8

0x0280+n10x4 VADDIETSMIX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tsmix_n7 tsmix_n6 tsmix_n5 tsmix_n4 tsmix_n3 tsmix_n2 tsmix_n1 tsmix_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW tsmix_n7 n1 7n1=03
[27:24] RW tsmix_n6 n1 6n1=03
[23:20] RW tsmix_n5 n1 5n1=03
[19:16] RW tsmix_n4 n1 4n1=03
[15:12] RW tsmix_n3 n1 3n1=03
[11:8] RW tsmix_n2 n1 2n1=03
[7:4] RW tsmix_n1 n1 1n1=03
[3:0] RW tsmix_n0 n1 0n1=03
VADDIETFLT
VADDIETFLT VAD De-interlace
4 8

02 (2010-01-19) 6-143

Hi3520
6

0x0290+n20x4 VADDIETFLT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tflt_n7 tflt_n6 tflt_n5 tflt_n4 tflt_n3 tflt_n2 tflt_n1 tflt_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW tflt_n7 n2 7n2=03
[27:24] RW tflt_n6 n2 6n2=03
[23:20] RW tflt_n5 n2 5n2=03
[19:16] RW tflt_n4 n2 4n2=03
[15:12] RW tflt_n3 n2 3n2=03
[11:8] RW tflt_n2 n2 2n2=03
[7:4] RW tflt_n1 n2 1n2=03
[3:0] RW tflt_n0 n2 0n2=03
VADDIEVFLT
VADDIEVFLT VAD De-interlace
4 8

0x02A0+n30x4 VADDIEVFLT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vflt_n7 vflt_n6 vflt_n5 vflt_n4 vflt_n3 vflt_n2 vflt_n1 vflt_n0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

6-144 02 (2010-01-19)

Hi3520
6
VADSTATUS
VADSTATUS VAD

0x02F0 VADSTATUS 0x0800_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
die_ref_field
Name reserved
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] - reserved
De-interlace de-interlace
0
[0] RO die_ref_field
0
1
VSDCTRL
VSDCTRL VSD

02 (2010-01-19) 6-145

Hi3520
6

0x0300 VSDCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
chm_rmode
bfield_first
regup_rate
lm_rmode
vsd_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW vsd_en 0
1
[30:18] - reserved
surface
1

1B0T0B1T1B0T0

00 buffer
10
11

00 buffer
10
11
[11:4] - reserved

0x3SPYCbCr4:2:0
[3:0] RW ifmt

6-146 02 (2010-01-19)

Hi3520
6
VSDUPD
VSDUPD VSD

0x0304 VSDUPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

VSDADDR
VSDADDR VSD package buffer
semi-planar buffer

0x0310 VSDADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vsdaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vsdaddr Surface buffer
VSDCADDR
VSDCADDR VSD package
semi-planar buffer

02 (2010-01-19) 6-147

Hi3520
6

0x0314 VSDCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vsdcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW vsdcaddr Surface buffer word
VSDSTRIDE
VSDSTRIDE VSD

0x0320 VSDSTRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name vsdcstride vsdstride
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[31:16] RW vsdcstride

buffer stride semi-planar

[15:0] RW vsdstride
stride word
VSDCBMPARA
VSDCBMPARA VSD

0x0324 VSDCBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved

6-148 02 (2010-01-19)

Hi3520
6
alpha
[7:0] RW galpha
01270 127
VSDORESO
VSDORESO VSD

0x0328 VSDORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] RW reserved

[11:0] RW ow 1

VSDIRESO
VSDIRESO VSD
z YCbCr4:2:0
4
z YCbCr4:2:0 2

02 (2010-01-19) 6-149

Hi3520
6

0x032C VSDIRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

[27:16] RW ih
1
[15:12] - reserved

[11:0] RW iw
1
VSDSFPOS
VSDSFPOS VSD

0x0330 VSDSFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] RW reserved
X
[11:0] RW src_xfpos
0
VSDDFPOS
VSDDFPOS VSD

6-150 02 (2010-01-19)

Hi3520
6

0x0334 VSDDFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VSDDLPOS
VSDDLPOS VSD


0x0338 VSDDLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VSDVFPOS
VSDVFPOS VSD

02 (2010-01-19) 6-151

Hi3520
6

0x033C VSDVFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VSDVLPOS
VSDVLPOS VSD


0x0340 VSDVLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
VSDBK
VSDBK VSD

6-152 02 (2010-01-19)

Hi3520
6

0x0344 VSDBK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0128
[23:16] RW vbk_y Y
[15:8] RW vbk_cb Cb
[7:0] RW vbk_cr Cr
G0CTRL
G0CTRL G0


0x0400 G0CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
csc_mo
csc_en
g0_en
bitext
de
Name reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW g0_en 0
1

[30] RW csc_en 0
1

[29] RW csc_mode 0BT.601
1BT.709
[28:10] - reserved

02 (2010-01-19) 6-153

Hi3520
6
Surface bit
0X 0
[9:8] RW bitext
10 bit
11 bit

[7:0] RW ifmt 0x49aRGB1555

G0UPD
G0UPD G0

0x0404 G0UPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

G0ADDR
G0ADDR G0

0x0408 G0ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name g0addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW g0addr Surface buffer

6-154 02 (2010-01-19)

Hi3520
6
G0STRIDE
G0STRIDE G0

0x040C G0STRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved g0stride
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] RW g0stride buffer
G0CBMPARA
G0CBMPARA G0

0x0410 G0CBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
palpha_range
key_mode
palpha_en
reserved
reserved
key_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
Color key
0 KeyminPixelKeymax
[15] RW key_mode
1 PixelKeymin PixelKeymax

Color key
[14] RW key_en 0
1

02 (2010-01-19) 6-155

Hi3520
6
[13] - reserved
alpha
[12] RW palpha_en 0
1
[11:9] - reserved
alpha
[8] RW palpha_range 00128
10255
alpha
[7:0] RW galpha
01270 127
G0CKEYMAX
G0CKEYMAX G0 color key

0x0414 G0CKEYMAX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name va0 keyr_max keyg_max keyb_max
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha0
[31:24] RW va0 alpha RGB1555 bit 0
alpha
[23:16] RW keyr_max Color key R
[15:8] RW keyg_max Color key G
[7:0] RW keyb_max Color key B
G0CKEYMIN
G0CKEYMIN G0 color key

6-156 02 (2010-01-19)

Hi3520
6

0x0418 G0CKEYMIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name va1 keyr_min keyg_min keyb_min
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha1
alpha
[23:16] RW keyr_min Color key R
[15:8] RW keyg_min Color key G
[7:0] RW keyb_min Color key B
G0IRESO
G0IRESO G0

0x041C G0IRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW ih

[15:12] - reserved

[11:0] RW iw 1

02 (2010-01-19) 6-157

Hi3520
6
G0ORESO
G0ORESO G0

0x0420 G0ORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

G0SFPOS
G0SFPOS G0

0x0424 G0SFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] - reserved

6-158 02 (2010-01-19)

Hi3520
6
X
[11:0] RW src_xfpos
0
G0DFPOS
G0DFPOS G0

0x0428 G0DFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
G0DLPOS
G0DLPOS G0

0x042C G0DLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved

02 (2010-01-19) 6-159

Hi3520
6
G1CTRL
G1CTRL G1


0x0500 G1CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
csc_mo
csc_en
g1_en
bitext
de
Name reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW g1_en 0
1

[30] RW csc_en 0
1

1BT.709
[28:10] - reserved
Surface bit
0X 0
[9:8] RW bitext
10 bit
11 bit


G1UPD
G1UPD G1

6-160 02 (2010-01-19)

Hi3520
6

0x0504 G1UPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

G1ADDR
G1ADDR G1

0x0508 G1ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name g1addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
G1STRIDE
G1STRIDE G1

02 (2010-01-19) 6-161

Hi3520
6

0x050C G1STRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
G1CBMPARA
G1CBMPARA G1

0x0510 G1CBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
palpha_range
key_mode
palpha_en
reserved
reserved
key_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
Color key
0 KeyminPixelKeymax
[15] RW key_mode

Color key
[14] RW key_en 0
1
[13] - reserved
alpha
[12] RW palpha_en 0
1

6-162 02 (2010-01-19)

Hi3520
6
[11:9] RW reserved
alpha
10255
alpha
[7:0] RW galpha
01270 127
G1CKEYMAX

0x0514 G1CKEYMAX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha0
alpha
G1CKEYMIN

02 (2010-01-19) 6-163

Hi3520
6

0x0518 G1CKEYMIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha1
alpha
G1IRESO
G1IRESO G1

0x051C G1IRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW ih

[15:12] - reserved

[11:0] RW iw 1

6-164 02 (2010-01-19)

Hi3520
6
G1ORESO
G1ORESO G1

0x0520 G1ORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

G1SFPOS
G1SFPOS G1

0x0524 G1SFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] - reserved

02 (2010-01-19) 6-165

Hi3520
6
X
[11:0] RW src_xfpos
0
G1DFPOS
G1DFPOS G1

0x0528 G1DFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved yfpos reserved xfpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW yfpos
[15:12] - reserved
[11:0] RW xfpos
G1DLPOS
G1DLPOS G1

0x052C G1DLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved ylpos reserved xlpos
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW ylpos
[15:12] - reserved
[11:0] RW xlpos

6-166 02 (2010-01-19)

Hi3520
6
G2CTRL
G2CTRL G2


0x0600 G2CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
csc_mo
csc_en
g2_en
bitext
de
Name reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW g2_en 0
1

[30] RW csc_en 0
1

1BT.709
[28:10] - reserved
Surface bit
0X 0
[9:8] RW bitext
10 bit
11 bit


G2UPD
G2UPD G2

02 (2010-01-19) 6-167

Hi3520
6

0x0604 G2UPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

G2ADDR
G2ADDR G2

0x0608 G2ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name g2addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
G2STRIDE
G2STRIDE G2

6-168 02 (2010-01-19)

Hi3520
6

0x060C G2STRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
G2CBMPARA
G2CBMPARA G2

0x0610 G2CBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
palpha_range
key_mode
palpha_en
reserved
reserved
key_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
Color key
0 KeyminPixelKeymax
[15] RW key_mode

Color key
[14] RW key_en 0
1
[13] - reserved
alpha
[12] RW palpha_en 0
1

02 (2010-01-19) 6-169

Hi3520
6
[11:9] - reserved
alpha
10255
alpha
[7:0] RW galpha
01270 127
G2CKEYMAX

0x0614 G2CKEYMAX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha0
alpha
G2CKEYMIN

6-170 02 (2010-01-19)

Hi3520
6

0x0618 G2CKEYMIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha1
alpha
G2IRESO
G2IRESO G2

0x061C G2IRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW ih

[15:12] - reserved

[11:0] RW iw 1

02 (2010-01-19) 6-171

Hi3520
6
G2ORESO
G2ORESO G2

0x0620 G2ORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

G2SFPOS
G2SFPOS G2

0x0624 G2SFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] - reserved

6-172 02 (2010-01-19)

Hi3520
6
X
[11:0] RW src_xfpos
0
G2DFPOS
G2DFPOS G2

0x0628 G2DFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW yfpos
[15:12] - reserved
[11:0] RW xfpos
G2DLPOS
G2DLPOS G2

0x062C G2DLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW ylpos
[15:12] - reserved
[11:0] RW xlpos

02 (2010-01-19) 6-173

Hi3520
6
G3CTRL
G3CTRL G3


0x0700 G3CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
csc_mo
csc_en
g3_en
bitext
de
Name reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW g3_en 0
1

[30] RW csc_en 0
1

1BT.709
[28:10] - reserved
Surface bit
0X 0
[9:8] RW bitext
10 bit
11 bit


G3UPD
G3UPD G3

6-174 02 (2010-01-19)

Hi3520
6

0x0704 G3UPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

G3ADDR
G3ADDR G3

0x0708 G3ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name g3addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
G3STRIDE
G3STRIDE G3

02 (2010-01-19) 6-175

Hi3520
6

0x070C G3STRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
G3CBMPARA
G3CBMPARA G3

0x0710 G3CBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
palpha_range
premult_en
key_mode
palpha_en
reserved
key_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
Color key
0 KeyminPixelKeymax
[15] RW key_mode

Color key
[14] RW key_en 0
1
[13] - premult_en
alpha
[12] RW palpha_en 0
1

6-176 02 (2010-01-19)

Hi3520
6
[11:9] - reserved
alpha
10255
alpha
[7:0] RW galpha
01270 127
G3CKEYMAX

0x0714 G3CKEYMAX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha0
alpha
G3CKEYMIN

02 (2010-01-19) 6-177

Hi3520
6

0x0718 G3CKEYMIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha1
alpha
G3IRESO
G3IRESO G3

0x071C G3IRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW ih

[15:12] - reserved

[11:0] RW iw 1

6-178 02 (2010-01-19)

Hi3520
6
G3ORESO
G3ORESO G3

0x0720 G3ORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

G3SFPOS
G3SFPOS G3

0x0724 G3SFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] RW reserved

02 (2010-01-19) 6-179

Hi3520
6
X
[11:0] RW src_xfpos
0
G3DFPOS
G3DFPOS G3

0x0728 G3DFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW yfpos
[15:12] - reserved
[11:0] RW xfpos
G3DLPOS
G3DLPOS G3

0x072C G3DLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[27:16] RW ylpos
[15:12] - reserved
[11:0] RW xlpos

6-180 02 (2010-01-19)

Hi3520
6
HCCTRL
HCCTRL HC


0x0800 HCCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
csc_mo
csc_en
hc_en
bitext
de
Name reserved ifmt
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Surface
[31] RW hc_en 0
1

[30] RW csc_en 0
1

1BT.709
[28:10] - reserved
Surface bit
0X 0
[9:8] RW bitext
10 bit
11 bit


HCUPD
HCUPD HC

02 (2010-01-19) 6-181

Hi3520
6

0x0804 HCUPD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regup
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
Surface
[0] RW regup 1

HCADDR
HCADDR HC

0x0808 HCADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name hcaddr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW hcaddr Surface buffer
HCSTRIDE
HCSTRIDE HC

6-182 02 (2010-01-19)

Hi3520
6

0x080C HCSTRIDE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hcstride
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] RW hcstride buffer
HCCBMPARA
HCCBMPARA HC

0x0810 HCCBMPARA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
palpha_range
key_mode
palpha_en
reserved
reserved
key_en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
Color key
0 KeyminPixelKeymax
[15] RW key_mode

Color key
[14] RW key_en 0
1
[13] - reserved
alpha
[12] RW palpha_en 0
1

02 (2010-01-19) 6-183

Hi3520
6
[11:9] - reserved
alpha
10255
alpha
[7:0] RW galpha
01270 127
HCCKEYMAX
HCCKEYMAX HC color key

0x0814 HCCKEYMAX 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha0
alpha
HCCKEYMIN
HCCKEYMIN HC color key

6-184 02 (2010-01-19)

Hi3520
6

0x0818 HCCKEYMIN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Alpha1
alpha
HCIRESO
HCIRESO HC

0x081C HCIRESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW ih

[15:12] - reserved

[11:0] RW iw 1

02 (2010-01-19) 6-185

Hi3520
6
HCORESO
HCORESO HC

0x0820 HCORESO 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

1
[27:16] RW oh

[15:12] - reserved

[11:0] RW ow 1

HCSFPOS
HCSFPOS HC

0x0824 HCSFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
Y
0
[15:12] - reserved

6-186 02 (2010-01-19)

Hi3520
6
X
[11:0] RW src_xfpos
0
HCFPOS
HCFPOS HC

0x0828 HCFPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved
HCDLPOS
HCDLPOS HC

0x082C HCDLPOS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved
[15:12] - reserved

02 (2010-01-19) 6-187

Hi3520
6
CBMBKG1
CBMBKG1 Mixer1

0x0B00 CBMBKG1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cbm_bkgcr1 cbm_bkgcb1 cbm_bkgy1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW cbm_bkgcr1 Mixer1 Y
[15:8] RW cbm_bkgcb1 Mixer1 Cb
[7:0] RW cbm_bkgy1 Mixer1 Cr
CBMBKG2
CBMBKG2 Mixer2

0x0B04 CBMBKG2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cbm_bkgcr2 cbm_bkgcb2 cbm_bkgy2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW cbm_bkgcr2 Mixer2 Y
[15:8] RW cbm_bkgcb2 Mixer2 Cb
[7:0] RW cbm_bkgy2 Mixer2 Cr
CBCFG
CBCFG Colorbar

6-188 02 (2010-01-19)

Hi3520
6

0x0B0C CBCFG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
mixer3_prio
mixer_prio4
mixer_prio3
mixer_prio2
mixer_prio1
mixer_prio0
sur_attr5
sur_attr4
sur_attr3
sur_attr2
sur_attr1
sur_attr0
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
GDC_HC
[29] RW sur_attr5 0Mixer1
1Mixer2
GDC_G2
1Mixer2
GDC_G1
1Mixer2
GDC_G0
1
VDC_AD
1Mixer2
VDC_HD
1
[23:16] - reserved
Mixer3
[15] RW mixer3_prio 0G3 VSD
1VSD G3

02 (2010-01-19) 6-189

Hi3520
6
Mixer1 Mixer2 4

000
001vdc_hd
[14:12] RW mixer_prio4 010vdc_ad
011gdc_g0
100gdc_g1
101gdc_g2

Mixer1 Mixer2 3

000
001vdc_hd
011gdc_g0
100gdc_g1
101gdc_g2

Mixer1 Mixer2 2

000
001vdc_hd
011gdc_g0
100gdc_g1
101gdc_g2

Mixer1 Mixer2 1

000
001vdc_hd
011gdc_g0
100gdc_g1
101gdc_g2

6-190 02 (2010-01-19)

Hi3520
6
Mixer1 Mixer2 0

000
001vdc_hd
011gdc_g0
100gdc_g1
101gdc_g2

DHDCTRL
DHDCTRL HD

0x0C00 DHDCTRL 0x0000_00EC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
slave_mo
gmmmod
reserved
cbar_sel
gmmen
intf_en
clipen
cscen
synm
intfb
idv
iop
ihs
ivs
de
Name reserved intfdm

e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0

0
[31] RW intf_en
1

[30] RW slave_mode 0
1 BT.1120 Capture
Colorbar
0001RGB
[29:28] RW cbar_sel
10YUV
11RGB
[27:17] - reserved

02 (2010-01-19) 6-191

Hi3520
6

[16] RW clipen 0
1

[15] RW cscen 0
1
Gamma
[14] RW gmmen 0
1
Gamma
[13] RW gmmmode 0Gamma
1Gamma
[12:11] - reserved

[10] RW idv 0
1

[9] RW ihs 0
1

[8] RW ivs 0
1

[7] RW iop 0
1

[6] RW synm 0 BT.656
1 LCD

00 1
[5:4] RW intfb 012 2
103 3
11

6-192 02 (2010-01-19)

Hi3520
6

0x0YCbCr4:2:2
[3:0] RW intfdm
OxCRGB888/YCbCr444

DHDVSYNC
DHDVSYNC HD

0x0C04 DHDVSYNC 0x0010_A257
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vfb vbb vact
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1
[31:28] - reserved

[27:20] RW vfb

[19:12] RW vbb

[11:0] RW vact
1
DHDHSYNC1
DHDHSYNC1 HD 1

02 (2010-01-19) 6-193

Hi3520
6

0x0C08 DHDHSYNC1 0x00D7_031F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name hbb hact
Reset 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1
[31:16] RW hbb
[15:0] RW hact
DHDHSYNC2
DHDHSYNC2 HD 2

0x0C0C DHDHSYNC2 0x0000_0027
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hfb
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1
[31:16] - reserved
[15:0] RW hfb
DHDVPLUS
DHDVPLUS HD

0x0C10 DHDVPLUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved bvfb bvbb bvact
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

6-194 02 (2010-01-19)

Hi3520
6
[27:20] RW bvfb
[19:12] RW bvbb

[11:0] RW bvact
1
DHDPWR
DHDPWR HD

0x0C14 DHDPWR 0x0003_007F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vpw hpw
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
[31:24] - reserved
[23:16] RW vpw 1
[15:0] RW hpw 1
DHDFIFOTHD
DHDFIFOTHD HD FIFO

0x0C18 DHDFIFOTHD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved aalmthd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:12] - reserved

[11:0] RW aalmthd
FIFO

02 (2010-01-19) 6-195

Hi3520
6
DHDVTTHD
DHDVTTHD HD

0x0C1C DHDVTTHD 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
thd_mode
reserved
Name reserved vtmgthd
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:17] - reserved

[16] RW thd_mode 0
1
[15:13] - reserved
HD
[12:0] RW vtmgthd

DHDCSCIDC
DHDCSCIDC HD

0x0C20 DHDCSCIDC 0x07C3_0180
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cscidc2 cscidc1 cscidc0
Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
[31:27] - reserved
[26:18] RW cscidc2 2 MSB

6-196 02 (2010-01-19)

Hi3520
6
DHDCSCODC
DHDCSCODC HD

0x0C24 DHDCSCODC 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cscodc2 cscodc1 cscodc0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:27] - reserved
[26:18] RW cscodc2 2 MSB
DHDCSCP0
DHDCSCP0 HD 0

0x0C28 DHDCSCP0 0x0000_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp01 cscp00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp01

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp00

02 (2010-01-19) 6-197

Hi3520
6
DHDCSCP1
DHDCSCP1 HD 1

0x0C2C DHDCSCP1 0x012A_01CB
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp10 cscp02
Reset 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp10

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp02

DHDCSCP2
DHDCSCP2 HD 2

0x0C30 DHDCSCP2 0x1F77_1FC9
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp12 cscp11
Reset 0 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp12

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp11

6-198 02 (2010-01-19)

Hi3520
6
DHDCSCP3
DHDCSCP3 HD 3

0x0C34 DHDCSCP3 0x021D_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp21 cscp20
Reset 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp21

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp20

DHDCSCP4
DHDCSCP4 HD 4

0x0C38 DHDCSCP4 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cscp22
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp22

02 (2010-01-19) 6-199

Hi3520
6
DHDCLIPL
DHDCLIPL HD

0x0C3C DHDCLIPL 0x0010_1010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name clipcl2 clipcl1 clipcl0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
[31:30] - reserved
[29:20] RW clipcl2 2 Y/R
[19:10] RW clipcl1 1 Cb/G
[9:0] RW clipcl0 0 Cr/B
DHDCLIPH
DHDCLIPH HD

0x0C40 DHDCLIPH 0x00EB_F0F0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name clipch2 clipch1 clipch0
Reset 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
[31:30] - reserved
[29:20] RW clipch2 2 Y/R
[19:10] RW clipch1 1 Cb/G
[9:0] RW clipch0 0 Cr/B

6-200 02 (2010-01-19)

Hi3520
6
DHDGMMTHD1
DHDGMMTHD1 HD Gamma 1

0x0C44 DHDGMMTHD1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name thd_med_low thd_high thd_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
[29:20] RW thd_med_low med_low
[19:10] RW thd_high high
[9:0] RW thd_low low
DHDGMMTHD2
DHDGMMTHD2 HD Gamma 2

0x0C48 DHDGMMTHD2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved gmm_multiple thd_med_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - reserved
[17:10] RW gmm_multiple Gamma
[9:0] RW thd_med_high med_high
DHDGMMLOWt
DHDGMMLOWt HD Gamma low

02 (2010-01-19) 6-201

Hi3520
6

0x0C50+t10x4 DHDGMMLOWt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
[29:0] RW table_datat Gamma t1
DHDGMMMEDt
DHDGMMMEDt HD Gamma med


0x0C60+t20x4 DHDGMMMEDt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DHDGMMHIGHt
DHDGMMHIGHt HD Gamma high

6-202 02 (2010-01-19)

Hi3520
6

0x0C70+t30x4 DHDGMMHIGHt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DHDGMMMLt
DHDGMMMLt HD Gamma middle_low


0x0C80+t40x4 DHDGMMMLt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DHDGMMMHt
DHDGMMMHt HD Gamma middle_high

02 (2010-01-19) 6-203

Hi3520
6

0x0CA0+t50x4 DHDGMMMHt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DHDGMM3LOW
DHDGMM3LOW HD Gamma

0x0CB0 DHDGMM3LOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt3_low
DHDGMM3MED
DHDGMM3MED HD Gamma

6-204 02 (2010-01-19)

Hi3520
6

0x0CB4 DHDGMM3MED 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_med
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt3_med
DHDGMM3HIGH
DHDGMM3HIGH HD Gamma

0x0CB8 DHDGMM3HIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt3_high
DHDGMM8MLOW
DHDGMM8MLOW HD Gamma 8


0x0CC0 DHDGMM8MLOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt8_med_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved

02 (2010-01-19) 6-205

Hi3520
6
[20:0] RO cnt8_med_low
DHDGMM8MHIGH
DHDGMM8MHIGH HD Gamma 8


0x0CC4 DHDGMM8MHIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt8_med_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt8_med_high
CCDIMGMOD
CCDIMGMOD

0x0CE0 CCDIMGMOD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
img_right
ccd_en
Name reserved img_mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:9] - reserved

[8] RW ccd_en 0
1

[7] RW img_right 0
1

6-206 02 (2010-01-19)

Hi3520
6

[6:0] RW img_mode 0x00 1
0x01 4
0x02 6
xxxx
DHDSTATE
DHDSTATE HD

0x0CF0 DHDSTATE 0x0000_0006
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bottom_field
vback_blank
vblank
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
[31:3] - reserved
DHD
[2] RO bottom_field 0
1
DHD
[1] RO vblank 0
1
DHD
[0] RO vback_blank 0
1
DADCTRL
DADCTRL AD

02 (2010-01-19) 6-207

Hi3520
6

0x0D00 DADCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
gmmmod
reserved
reserved
cbar_sel
gmmen
intf_en
clipen
cscen
synm
intfb
idv
iop
ihs
ivs
Name reserved intfdm
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0
[31] RW intf_en
1

[30] - reserved
Colorbar
0001YUV
[29:28] RW cbar_sel
10YUV
11RGB
[27:17] - reserved

[16] RW clipen 0
1

[15] RW cscen 0
1
Gamma
[14] RW gmmen 0
1
Gamma
[13] RW gmmmode 0Gamma
1Gamma
[12:11] - reserved

[10] RW idv 0
1

6-208 02 (2010-01-19)

Hi3520
6

[9] RW ihs 0
1

[8] RW ivs 0
1

[7] RW iop 0
1

1 LCD

00 1
[5:4] RW intfb 012 2
103 3
11

0x0YCbCr4:2:2
[3:0] RW intfdm
0xCRGB888/YCbCr444

DADVSYNC
DADVSYNC AD

0x0D04 DADVSYNC 0x0011_511F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1
[31:28] - reserved

[27:20] RW vfb

02 (2010-01-19) 6-209

Hi3520
6

[19:12] RW vbb

[11:0] RW vact
1
DADHSYNC1
DADHSYNC1 AD 1

0x0D08 DADHSYNC1 0x0107_02CF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name hbb hact
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1
[31:16] RW hbb
[15:0] RW hact
DADHSYNC2
DADHSYNC2 AD 2

0x0D0C DADHSYNC2 0x0000_0017
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hfb
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
[31:16] - reserved
[15:0] RW hfb

6-210 02 (2010-01-19)

Hi3520
6
DADVPLUS
DADVPLUS AD

0x0D10 DADVPLUS 0x0011_611F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1
[31:28] - reserved
[27:20] RW bvfb
[19:12] RW bvbb

[11:0] RW bvact
1
DADPWR
DADPWR AD

0x0D14 DADPWR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW vpw 1
[15:0] RW hpw 1
DADFIFOTHD
DADFIFOTHD AD FIFO

02 (2010-01-19) 6-211

Hi3520
6

0x0D18 DADFIFOTHD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:12] - reserved

[11:0] RW aalmthd
FIFO
DADVTTHD
DADVTTHD AD

0x0D1C DADVTTHD 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
thd_mode
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:17] - reserved

[16] RW thd_mode 0
1
[15:13] - reserved
AD
[12:0] RW vtmgthd

DADCSCIDC
DADCSCIDC AD

6-212 02 (2010-01-19)

Hi3520
6

0x0D20 DADCSCIDC 0x07C3_0180
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
[31:27] - reserved
DADCSCODC
DADCSCODC AD

0x0D24 DADCSCODC 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:27] - reserved
DADCSCP0
DADCSCP0 AD 0

02 (2010-01-19) 6-213

Hi3520
6

0x0D28 DADCSCP0 0x0000_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp01 cscp00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp01

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp00

DADCSCP1
DADCSCP1 AD 1

0x0D2C DADCSCP1 0x012A_01CB
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp10 cscp02
Reset 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp10

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp02

6-214 02 (2010-01-19)

Hi3520
6
DADCSCP2
DADCSCP2 AD 2

0x0D30 DADCSCP2 0x1F77_1FC9
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp12 cscp11
Reset 0 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp12

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp11

DADCSCP3
DADCSCP3 AD 3

0x0D34 DADCSCP3 0x021D_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp21 cscp20
Reset 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp21

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp20

02 (2010-01-19) 6-215

Hi3520
6
DADCSCP4
DADCSCP4 AD 4

0x0D38 DADCSCP4 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp22

DADCLIPL
DADCLIPL AD

0x0D3C DADCLIPL 0x0010_1010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
[31:30] - reserved
DADCLIPH
DADCLIPH AD

6-216 02 (2010-01-19)

Hi3520
6

0x0D40 DADCLIPH 0x00EB_F0F0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
[31:30] - reserved
DADGMMTHD1
DADGMMTHD1 AD Gamma 1

0x0D44 DADGMMTHD1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name thd_med_low thd_high thd_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
[29:20] RW thd_med_low med_low
[19:10] RW thd_high high
[9:0] RW thd_low low
DADGMMTHD2
DADGMMTHD2 AD Gamma 2

02 (2010-01-19) 6-217

Hi3520
6

0x0D48 DADGMMTHD2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved gmm_multiple thd_med_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - reserved
[17:10] RW gmm_multiple Gamma
[9:0] RW thd_med_high med_high
DADGMMLOWt
DADGMMLOWt AD Gamma low


0x0D50+t10x4 DADGMMLOWt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datan
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
[29:0] RW table_datan Gamma t1
DADGMMMEDt
DADGMMMEDt AD Gamma med

6-218 02 (2010-01-19)

Hi3520
6

0x0D60+t20x4 DADGMMMEDt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datan
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DADGMMHIGHt
DADGMMHIGHt AD Gamma high


0x0D70+t30x4 DADGMMHIGHt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datan
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DADGMMMLt
DADGMMMLt AD Gamma middle_low

02 (2010-01-19) 6-219

Hi3520
6

0x0D80+t40x4 DADGMMMLt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datan
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DADGMMMHt
DADGMMMHt AD Gamma middle_high


0x0DA0+t50x4 DADGMMMHt 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name table_datan
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:30] - reserved
DADGMM3LOW
DADGMM3LOW AD Gamma

6-220 02 (2010-01-19)

Hi3520
6

0x0DB0 DADGMM3LOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt3_low
DADGMM3MED
DADGMM3MED AD Gamma

0x0DB4 DADGMM3MED 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_med
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt3_med
DADGMM3HIGH
DADGMM3HIGH AD Gamma

0x0DB8 DADGMM3HIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt3_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved

02 (2010-01-19) 6-221

Hi3520
6
[20:0] RO cnt3_high
DADGMM8MLOW
DADGMM8MLOW AD GMMA 8


0x0DC0 DADGMM8MLOW 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt8_med_low
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt8_med_low
DADGMM8MHIGH
DADGMM8MHIGH AD Gamma 8


0x0DC4 DADGMM8MHIGH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt8_med_high
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:21] - reserved
[20:0] RO cnt8_med_high
DADSTATE
DADSTATE AD

6-222 02 (2010-01-19)

Hi3520
6

0x0DF0 DADSTATE 0x0000_0006
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bottom_field
vback_blank
vblank
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
[31:3] - reserved
DAD
[2] RW bottom_field 0
1
DAD
[1] RW vblank 0
1
DAD
[0] RW vback_blank 0
1
DSDCTRL
DSDCTRL SD

0x0E00 DSDCTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
cbar_sel
intf_en
clipen
cscen
synm
intfb
idv
iop
ihs
ivs
Name reserved reserved intfdm
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0
[31] RW intf_en
1

02 (2010-01-19) 6-223

Hi3520
6
[30] - reserved
Colorbar
0001YUV
[29:28] RW cbar_sel
10YUV
11RGB
[27:17] - reserved

[16] RW clipen 0
1

[15] RW cscen 0
1
[14:11] - reserved

0
[10] RW idv

[9] RW ihs 0
1

[8] RW ivs 0
1

[7] RW iop 0
1

1 LCD

00 1
[5:4] RW intfb 012 2
103 3
11

6-224 02 (2010-01-19)

Hi3520
6

0x0YCbCr4:2:2
[3:0] RW intfdm
OxCRGB888/YCbCr444

DSDVSYNC
DSDVSYNC SD

0x0E04 DSDVSYNC 0x0011_511F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1
[31:28] - reserved

[27:20] RW vfb

[19:12] RW vbb

[11:0] RW vact
1
DSDHSYNC1
DSDHSYNC1 SD 1

02 (2010-01-19) 6-225

Hi3520
6

0x0E08 DSDHSYNC1 0x0107_02CF
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name hbb hact
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1
[31:16] RW hbb
[15:0] RW hact
DSDHSYNC2
DSDHSYNC2 SD 2

0x0E0C DSDHSYNC2 0x0000_0017
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hfb
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
[31:16] - reserved
[15:0] RW hfb
DSDVPLUS
DSDVPLUS SD

0x0E10 DSDVPLUS 0x0011_611F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1
[31:28] - reserved

6-226 02 (2010-01-19)

Hi3520
6
[27:20] RW bvfb
[19:12] RW bvbb

[11:0] RW bvact
1
DSDPWR
DSDPWR SD

0x0E14 DSDPWR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
[23:16] RW vpw 1
[15:0] RW hpw 1
DSDFIFOTHD
DSDFIFOTHD SD FIFO

0x0E18 DSDFIFOTHD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:12] - reserved

[11:0] RW aalmthd
FIFO

02 (2010-01-19) 6-227

Hi3520
6
DSDVTTHD
DSDVTTHD SD

0x0E1C DSDVTTHD 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
thd_mode
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:17] - reserved

[16] RW thd_mode 0
1
[15:13] - reserved
SD
[12:0] RW vtmgthd

DSDCSCIDC
DSDCSCIDC SD

0x0E20 DSDCSCIDC 0x07C3_0180
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
[31:27] - reserved

6-228 02 (2010-01-19)

Hi3520
6
DSDCSCODC
DSDCSCODC SD

0x0E24 DSDCSCODC 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:27] - reserved
DSDCSCP0
DSDCSCP0 SD 0

0x0E28 DSDCSCP0 0x0000_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp01 cscp00
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp01

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp00

02 (2010-01-19) 6-229

Hi3520
6
DSDCSCP1
DSDCSCP1 SD 1

0x0E2C DSDCSCP1 0x012A_01CB
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp10 cscp02
Reset 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp10

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp02

DSDCSCP2
DSDCSCP2 SD 2

0x0E30 DSDCSCP2 0x1F77_1FC9
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp12 cscp11
Reset 0 0 0 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp12

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp11

6-230 02 (2010-01-19)

Hi3520
6
DSDCSCP3
DSDCSCP3 SD 3

0x0E34 DSDCSCP3 0x021D_012A
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
Name cscp21 cscp20
Reset 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0
[31:29] - reserved
5.8 1bit 4bit 8bit

[28:16] RW cscp21

[15:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp20

DSDCSCP4
DSDCSCP4 SD 4

0x0E38 DSDCSCP4 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:13] - reserved
5.8 1bit 4bit 8bit

[12:0] RW cscp22

02 (2010-01-19) 6-231

Hi3520
6
DSDCLIPL
DSDCLIPL SD

0x0E3C DSDCLIPL 0x0010_1010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
[31:30] - reserved
DSDCLIPH
DSDCLIPH SD

0x0E40 DSDCLIPH 0x00EB_F0F0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
[31:30] - reserved

6-232 02 (2010-01-19)

Hi3520
6
DSDSTATE
DSDSTATE SD

0x0EF0 DSDSTATE 0x0000_0006
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bottom_field
vback_blank
vblank
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
[31:3] - reserved
DSD
[2] RW bottom_field 0
1
DSD
[1] RW vblank 0
1
DSD
[0] RW vback_blank 0
1
CCDSPOSm
CCDSPOSm m

02 (2010-01-19) 6-233

Hi3520
6

0x0F00+m0x4 CCDSPOSm 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
img_valid
reserved
Name spos_y reserved spos_x
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
m
[31] RW img_valid 0
1
[30:28] - reserved

1
[27:16] RW spos_y

[15:12] - reserved

[11:0] RW spos_x 1

CCDFPOSm
CCDFPOSm m

0x0F80+m0x4 CCDFPOSm 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved fpos_y reserved fpos_x
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

6-234 02 (2010-01-19)

Hi3520
6

1
[27:16] RW fpos_y

[15:12] - reserved

[11:0] RW fpos_x 1

VHDHLCOEF
VHDHLCOEF VHD 18
4 0x00x40x8 0xC 4 8

0x10000x111C VHDHLCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hlcoefn2 reserved hlcoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 2
[25:16] RW hlcoefn2 bit[3:0] 0x4 4
bit[3:0] 0x8 6
bit[3:0] 0xC 8
[15:10] - reserved

bit[3:0] 0x0 1
[9:0] RW hlcoefn1 bit[3:0] 0x4 3
bit[3:0] 0x8 5
bit[3:0] 0xC 7

02 (2010-01-19) 6-235

Hi3520
6
VHDHCCOEF
VHDHCCOEF VHD 18
4 0x00x4 0x80xC 2 4

0x12000x128C VHDHCCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hccoefn2 reserved hccoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 0x8 2
[25:16] RW hccoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW hccoefn1
bit[3:0] 0x4 0xC 3

VHDVLCOEF
VHDVLCOEF VHD 18
4 0x00x4 0x80xC 2 4

0x13000x138C VHDVLCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vlcoefn2 reserved vlcoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

6-236 02 (2010-01-19)

Hi3520
6

bit[3:0] 0x0 0x8 2
[25:16] RW vlcoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW vlcoefn1
bit[3:0] 0x4 0xC 3

VHDVCCOEF
VHDVCCOEF VHD 18
4 0x00x4 0x80xC 2 4

0x14000x148C VHDVCCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vccoefn2 reserved vccoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 0x8 2
[25:16] RW vccoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW vccoefn1
bit[3:0] 0x4 0xC 3

02 (2010-01-19) 6-237

Hi3520
6
VADHLCOEF
VADHLCOEF VAD 18
4 0x00x40x8 0xC 4 8

0x15000x161C VADHLCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hlcoefn2 reserved hlcoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 2
[25:16] RW hlcoefn2 bit[3:0] 0x4 4
bit[3:0] 0x8 6
bit[3:0] 0xC 8
[15:10] - reserved

bit[3:0] 0x0 1
[9:0] RW hlcoefn1 bit[3:0] 0x4 3
bit[3:0] 0x8 5
bit[3:0] 0xC 7
VADHCCOEF
VADHCCOEF VAD 18
4 0x00x4 0x80xC 2 4

0x17000x178C VADHCCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved hccoefn2 reserved hccoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

6-238 02 (2010-01-19)

Hi3520
6

bit[3:0] 0x0 0x8 2
[25:16] RW hccoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW hccoefn1
bit[3:0] 0x4 0xC 3

VADVLCOEF
VADVLCOEF VAD 18
4 0x00x4 0x80xC 2 4

0x18000x188C VADVLCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vlcoefn2 reserved vlcoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 0x8 2
[25:16] RW vlcoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW vlcoefn1
bit[3:0] 0x4 0xC 3

02 (2010-01-19) 6-239

Hi3520
6
VADVCCOEF
VADVCCOEF VAD 18
4 0x00x4 0x80xC 2 4

0x19000x198C VADVCCOEF 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved vccoefn2 reserved vccoefn1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:26] - reserved

bit[3:0] 0x0 0x8 2
[25:16] RW vccoefn2
bit[3:0] 0x4 0xC 4

[15:10] - reserved

bit[3:0] 0x0 0x8 1
[9:0] RW vccoefn1
bit[3:0] 0x4 0xC 3

VHDMIMGSPOSp
VHDMIMGSPOSp VHD De-interlace p


0x23000x237C VHDMIMGSPOSp 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
die_mode
die_valid
reserved
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31] - reserved

6-240 02 (2010-01-19)

Hi3520
6
p de-interlace
[30] RW die_valid 0
1
p de-interlace
[29] RW die_mode 0 VHDDIECTRL
1
[28] - reserved

[27:16] RW spos_y

[15:12] - reserved

[11:0] RW spos_x

VHDMIMGFPOSp
VHDMIMGFPOSp VHD De-interlace p

0x23800x23FC VHDMIMGFPOSp 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] RW reserved

[27:16] RW fpos_y

[15:12] - reserved

[11:0] RW fpos_x

02 (2010-01-19) 6-241

Hi3520
6
VADMIMGSPOSp
VADMIMGSPOSp VAD De-interlace p


0x24000x247C VADMIMGSPOSp 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
die_mode
die_valid
reserved
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31] - reserved
p de-interlace
[30] RW die_valid 0
1
p de-interlace
[29] RW die_mode 0 VADDIECTR
1 2
[28] - reserved

[27:16] RW spos_y

[15:12] - reserved

[11:0] RW spos_x

VADMIMGFPOSp
VADMIMGFPOSp VAD De-interlace p

6-242 02 (2010-01-19)

Hi3520
6

0x24800x24FC VADMIMGFPOSp 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:28] - reserved

[27:16] RW fpos_y

[15:12] - reserved

[11:0] RW fpos_x

02 (2010-01-19) 6-243

Hi3520
7
7.1
SIOSonic Input/Output Audio CODEC
3 SIO0SIO1 SIO2SIO0
SIO1 SIO2 8/16
7.2
SIO PCMPulse Code Modulation I2S PCM
VOIP I2S AUDIO CODEC
SIO DMA
7.2.1 PCM
PCM
z
z 8bit 16bit PCM
z 2/4/8/16 8/16 bit
z
z PCM 1
2
z
z FIFO 16
7.2.2 I2S
I2S
z
z 16/18/20/24/32bit
z 2/4/8/16 8/16bit

02 (2010-01-19) 7-1

Hi3520
7
z 8K192K
z I2S FIFO
FIFO FIFO 16FIFO
z I2S
z I2S 16bit 32bit
FIFO 32bit
FIFO FIFO 2/4/8/16 8/16bit

7.3
SIO 3 SIO SIO0SIO1 SIO2 3 7-1

7-1 SIO
SIO0_DI I SIO0DI
SIO0_DO O SIO0DO
SIO0_XFS I/O I2S DAC SIO0XFS

PCM GPIO

SIO0_RFS I/O I2S ADC SIO0RFS

PCM
SIO0_XCK I/O I2S/PCM GPIO SIO0XCK

SIO0_RCK I/O I2S/PCM SIO0RCK
SIO_MCLK O I2S PCM CODEC ACKOUT

GPIO

SIO1_DI I SIO1DI

PCM
SIO2_DI I SIO2DI
SIO1_DO GPIO

7-2 02 (2010-01-19)

Hi3520
7

PCM
SIO1_XFS GPIO


SIO1_XCK GPIO

AUDIO CODEC
CODEC SIO0_RFS SIO0 XFS
SC_PERCTRL12[sio0_xfs]=0b1 RFS SIO0_XFS
GPIO SC_PERCTRL12[sio0_xck]SIO1
SC_PERCTRL12[sio1_xfs] SC_PERCTRL12[sio1_xck]
7.4
SIO0 I2S
AUDIO CODEC SIO_MCLK

02 (2010-01-19) 7-3

Hi3520
7
I2S 7-1
7-1 I2S
SIO0_RCK
SIO0_XCK
SIO0_XFS
AUDIO
SIO0 SIO0_RFS CODEC
SIO0_DO
SIO0_DI
SIO AUDIO CODEC

AUDIO CODEC SIO
I2S 7-2
7-2 I2S
SIO0_RCK
SIO0_XCK
SIO0_XFS AUDIO
SIO0 CODEC
SIO0_RFS
SIO0_DO
SIO0_DI
AUDIO CODEC
SIO_MCLK
SIO PCM 7-3 AUDIO CODEC

SIO_MCLK

SIO PCM I2S 7-1

7-4 02 (2010-01-19)

Hi3520
7
AUDIO CODEC PCM I2S

7-2
AUDIO CODEC AUDIO CODEC

SIO_MCLK
SIO1 SIO2 8/16 16bits SIO1

I2S/PCM 7-3 7-4
7-3 I2S/PCM
SIO1_RCK
AUDIO
SIO1 SIO1_RFS
CODEC
SIO1_DI
7-4 I2S/PCM
SIO1_RCK
AUDIO
SIO1 SIO1_RFS
CODEC
SIO1_DI
2/4/8/16 8/16bitsSIO2
SIO1 SIO1_RCKSIO1_RFS
SIO1_DI SIO2_RCKSIO2_RFSSIO2_DI SIO1_XCK
SIO1_XFSSIO1_DO

02 (2010-01-19) 7-5

Hi3520
7
SIO
I2S PCM AUDIO CODECAUDIO CODEC DADigital-
to-Analog I2S PCM SIO AUDIO
CODEC ADAnalog-to-Digital FIFO
CPU
I2S XFSRFS 7-
5 XCK/RCK MSB XFS/RFS
MSB LSB
I2S 7-5
7-5 I2S
XCK/RCK
XFS/RFS
Left Channel Right Channel
DO/DI MSB LSB MSB LSB
PCM XFS
MSBMSB XFS
MSB XFS

PCM 7-6
7-6 PCM
XCK
XFS
DI/DO MSB MSB
PCM 7-7

7-6 02 (2010-01-19)

Hi3520
7
7-7 PCM
XCK
XFS
DI/DO MSB MSB
I2S 2/4/8/16 8/16bit I2S

7-8
7-8 I2S 2/4/8/16
1/fs
ASYNR
ACLKR
16 0 1 2 3 4 5 6 7 8 9 A B C D E F
8 0 1 2 3 4 5 6 7
4 0 1 2 3
2 0 1
MSB LSB
8/16bit
PCM 7-9 PCM

SIO

02 (2010-01-19) 7-7

Hi3520
7
7-9 PCM 2/4/8/16
1/fs
ASYNR
ACLKR
16 0 1 2 3 4 5 6 7 8 9 A B C D E F
8 0 1 2 3 4 5 6 7
4 0 1 2 3
2 0 1
MSB LSB
8/16bit
7.5
IO Config reg65reg70 SIO

7-2
7-2
SIO0XFS GPIO0_2
SIO0XCK GPIO0_3
ACKOUT GPIO0_4
SIO2DI SIO1DO
SIO2RFS SIO1XFS
SIO2RCK SIO1XCK

7-8 02 (2010-01-19)

Hi3520
7
SIO0SIO1SIO2 SIO_CT_SET[rx_enable]
SIO_CT_SET[tx_enable] 0 SC_PERDIS 1
SIO 0
z SC_PERDIS[sio0_clkdis] 1 SIO0
SC_PEREN 1
0
z SC_PEREN[sio0clken] 1 SIO0
SIO SC_PERCLKEN 0
1
3 SIO
SIO0SIO1 SIO2
SC_PERIPHCTRL12[sio0_master]SC_PERIPHCTRL12[sio1_master]
SC_PERIPHCTRL12[sio2_master] 1
SC_PERIPHCTRL16SC_PERIPHCTRL13SC_PERIPHCTRL14

SC_PERIPHCTRL8[sio0_srst]SC_PERIPHCTRL8[sio1_srst]
SC_PERIPHCTRL8[sio2_srst] 1 SIO0SIO1 SIO2

1.
1 SIO_CT_SET/SIO_CT_CLR[rx_enable] SIO_CT_SET/SIO_CT_CLR[tx_enable]
0 SIO
2 SIO_MODE[sio_mode] I2S PCM PCM

SIO_MODE[pcm_mode] SIO_MODE[ext_rec_en]
SIO_MODE[chn_num] SIO_MODE[clk_edge]
3 SIO

02 (2010-01-19) 7-9

Hi3520
7
4 SIO_DATA_WIDTH_SET SIO_SIGNED_EXT

5 SIO_CT_SET[rx_fifo_threshold] SIO_CT_SET[tx_fifo_threshold]
FIFO FIFO
6 I2S FIFO SIO_I2S_POS_MERGE_EN

SIO_I2S_START_POS SIO_CT_SET[tx_data_merge_en]
SIO_CT_SET[rx_data_merge_en]
7 SIO SIO_INTMASK
SIO_CT_SET[intr_en]
8 AUDIO CODEC
----
2.
1 SIO_CT_SET[tx_fifo_disable] 1 0 FIFO

2 FIFO SIO_CT_SET[tx_enable] 1
3 SIO_TX_STA TX_FIFO
SIO_INTSTATUS[tx_intr] FIFO
FIFO 4
TX_FIFO
4 SIO_CT_SET[tx_enable] 0
----
3.
1 FIFO SIO_CT_SET[rx_fifo_disable] 1
0
2 SIO_CT_SET[rx_enable] 1
3 SIO_RX_STA RX_FIFO
FIFO FIFO
4 RX_FIFO

4 SIO_CT_SET[rx_enable] 0 FIFO
----

7-10 02 (2010-01-19)

Hi3520
7
DMA
1.
2.
1 SIO_INTMASK[tx_intr] 1
2 DMA
DMA
3 SIO_CT_SET[tx_fifo_disable] 1 0 FIFO

4 FIFO FIFO 0
DMA FIFO SIO
FIFO FIFO
5 SIO_CT_SET[tx_enable] 1
6 DMA
SIO_CT_SET[tx_enable] 0
----
3.
1 DMA
DMA
2 FIFO SIO_CT_SET[rx_fifo_disable] 1
0
----
7.6
3 SIO
z SIO00x1004_0000
z SIO10x1005_0000
z SIO20x1006_0000
7-3

02 (2010-01-19) 7-11

Hi3520
7
7-3 SIO
0x03C SIO_VERSION SIO 7-13
0x040 SIO_MODE SIO 7-13
0x044 SIO_INTSTATUS SIO 7-15
0x048 SIO_INTCLR SIO 7-17
0x04C SIO_I2S_LEFT_XD I2S 7-18
0x050 SIO_I2S_RIGHT_XD I2S 7-18
0x050 SIO_PCM_XD PCM 7-18
0x054 SIO_I2S_LEFT_RD I2S 7-19
0x058 SIO_I2S_RIGHT_RD I2S 7-19
0x058 SIO_PCM_RD PCM 7-20
0x05C SIO_CT_SET I2S/PCM 7-20
0x060 SIO_CT_CLR I2S/PCM 7-22
0x064 RESERVED -
0x068 SIO_RX_STA SIO 7-24
0x06C SIO_TX_STA SIO 7-25
0x0700x074 RESERVED -
0x078 SIO_DATA_WIDTH_SE I2S/PCM 7-25

T
0x07C SIO_I2S_START_POS I2S 7-26

0x080 I2S_POS_FLAG I2S 7-27

0x084 SIO_SIGNED_EXT 7-28
0x088 SIO_I2S_POS_MERGE_ I2S 7-28

EN
0x08C SIO_INTMASK SIO 7-29
0x0900x09C RESERVED -
0x0A0 SIO_I2S_DUAL_RX_C I2S 7-30

HN

7-12 02 (2010-01-19)

Hi3520
7
0x0C0 SIO_I2S_DUAL_TX_C I2S 7-31

HN
7.7
SIO_VERSION
SIO SIO
offset Address Register Name Total Reset Value

0x03C SIO_VERSION 0x0000_0013
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sio_loop
Name reserved version
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
[31:9] - reserved
SIO
0
[8] RW sio_loop 1SIO SIO
SIO SIO SIO

[7:0] RO vesion SIO
SIO_MODE
SIO
z CRG CODEC SIO
z CODEC SIO
I2S PCM SC_PERCTRL12

SC_PERCTRL12

02 (2010-01-19) 7-13

Hi3520
7

0x040 SIO_MODE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e
c x r
l t e
k _ s
pcm_mode
sio_mode
chn
_ r e
Name reserved _nu
e e r
m
d c v
g _ e
e e d
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:7] - reserved
PCM
[6] RW clk_edge 0
1

002 chn
[5:4] RW chn_num 014 chn
108 chn
1116 chn.
I2S
PCM
I2S PCM
[3] RW ext_rec_en 8bit 16bit
0 I2S PCM
1 I2S PCM
[2] - reserved 0
PCM
[1] RW pcm_mode 0
1
PCM/I2S
[0] RW sio_mode 0I2S
1PCM

7-14 02 (2010-01-19)

Hi3520
7
SIO_INTSTATUS
SIO
FIFO FIFO
CPU
CPU
1 SIO_CT_CLR[intr_en] 1
2 SIO_INTSTATUS
4 SIO_INTCLR 1
5 SIO_CT_SET[intr_en] 1
----

02 (2010-01-19) 7-15

Hi3520
7

0x044 SIO_INTSTATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tx_right_fifo_under
rx_right_fifo_over
tx_left_fifo_under
rx_left_fifo_over
rx_intr
tx_intr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] - reserved
I2S FIFO PCM

[5] RO tx_left_fifo_under
0
1
I2S FIFO PCM

PCM FIFO
[4] RO tx_right_fifo_under
0
1
I2S FIFO PCM

[3] RO rx_left_fifo_over
0
1
I2S FIFO PCM

PCM FIFO
[2] RO rx_right_fifo_over
0
1
FIFO
[1] RO tx_intr 0
1
FIFO
[0] RO rx_intr 0
1

7-16 02 (2010-01-19)

Hi3520
7
SIO_INTCLR


0x048 SIO_INTCLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tx_right_fifo_under
rx_right_fifo_over
tx_left_fifo_under
rx_left_fifo_over
rx_intr
tx_intr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] - reserved
I2S FIFO PCM

[5] WO tx_left_fifo_under
0
1
I2S FIFO PCM

PCM FIFO
[4] WO tx_right_fifo_under
0
1
I2S FIFO PCM

[3] WO rx_left_fifo_over
0
1
I2S FIFO PCM

PCM FIFO
[2] WO rx_right_fifo_over
0
1
FIFO
[1] WO tx_intr 0
1
FIFO
[0] WO rx_intr 0
1

02 (2010-01-19) 7-17

Hi3520
7
SIO_I2S_LEFT_XD
I2S
bit 8bit
bit[7:0]bit[31:8] 16bit bit[15:0]
bit[31:16] bit SIO 0

0x04C SIO_I2S_LEFT_XD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_left_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] WO tx_left_data
SIO_I2S_RIGHT_XD
I2S PCM I2S

bit 8bit
bit[7:0]bit[31:8] 16bit bit[15:0]

0x050 SIO_I2S_RIGHT_XD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_right_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] WO tx_right_data
SIO_PCM_XD
PCM PCM I2S

7-18 02 (2010-01-19)

Hi3520
7
bit 8bit
bit[7:0]bit[31:8]16bit bit[15:0]

0x050 SIO_PCM_XD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved tx__data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] WO tx_data PCM
SIO_I2S_LEFT_RD
I2S
SIO bit 8bit

bit[7:0]bit[31:8] 16bit bit[15:0]

0x054 SIO_I2S_LEFT_RD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_left_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO rx_left_data I2S

I2S FIFO FIFO FIFO
CPU FIFO
SIO_I2S_RIGHT_RD
I2S PCM I2S

SIO bit 8bit

bit[7:0]bit[31:8] 16bit bit[15:0]

02 (2010-01-19) 7-19

Hi3520
7

0x058 SIO_I2S_RIGHT_RD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_right_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO rx_right_data I2S

I2S FIFO FIFO FIFO
CPU FIFO
SIO_PCM_RD
PCM I2S
SIO bit 8bit

bit[7:0]bit[31:8] 16bit bit[15:0]

0x058 SIO_PCM_RD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved rx__data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] RO rx_data PCM
SIO_CT_SET
SIO SIO 0x05C
0x05C 1 1 0

7-20 02 (2010-01-19)

Hi3520
7

0x05C/0x060 SIO_CT_SET 0x0000_8000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rx_data_merge_en
tx_data_merge_en
rx_fifo_threshold
tx_fifo_threshold
rx_fifo_disable
tx_fifo_disable
rx_enable
tx_enable
intr_en
rst_n
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
I2S/PCM
[15] RW rst_n I2S/PCM FIFO

FIFO 0 CPU

[14] RW intr_en 0
1

[13] RW rx_enable 0
1

[12] RW tx_enable 0
1
FIFO
[11] RW rx_fifo_disable 0
1
FIFO
[10] RW tx_fifo_disable 0
1

02 (2010-01-19) 7-21

Hi3520
7
I2S 16bit

0
1
1 32bit FIFO
[9] RW rx_data_merge_en 16bit 16 16bit
16 FIFO

CPU FIFO
FIFO 32bit 16bit
32bit FIFO 32bit

I2S 16bit

0
1
1 32bit FIFO
[8] RW tx_data_merge_en 16bit 16 16bit
16 FIFO

CPU FIFO
FIFO 32bit 16bit
32bit FIFO 32bit

FIFO
[7:4] RW rx_fifo_threshold rx_right_depth(rx_fifo_threshold + 1)
DMA
FIFO
[3:0] RW tx_fifo_threshold tx_right_depth<(tx_fifo_threshold+1)
DMA
SIO_CT_CLR
SIO SIO 0x060
1 0

7-22 02 (2010-01-19)

Hi3520
7

0x05C/0x060 SIO_CT_SET 0x0000_8000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rx_data_merge_en
tx_data_merge_en
rx_fifo_threshold
tx_fifo_threshold
rx_fifo_disable
tx_fifo_disable
rx_enable
tx_enable
intr_en
rst_n
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
I2S/PCM
[15] RW rst_n I2S/PCM FIFO

FIFO 0 CPU

[14] RW intr_en 0
1

[13] RW rx_enable 0
1

[12] RW tx_enable 0
1
FIFO
[11] RW rx_fifo_disable 0
1
FIFO
[10] RW tx_fifo_disable 0
1

02 (2010-01-19) 7-23

Hi3520
7
I2S 16bit

0
1
1 32bit FIFO
[9] RW rx_data_merge_en 16bit 16 16bit
16 FIFO

CPU FIFO
FIFO 32bit 16bit
32bit FIFO 32bit

I2S 16bit

0
1
1 32bit FIFO
[8] RW tx_data_merge_en 16bit 16 16bit
16 FIFO

CPU FIFO
FIFO 32bit 16bit
32bit FIFO 32bit

FIFO
[7:4] RW rx_fifo_threshold rx_right_depth(rx_fifo_threshold+1)
DMA
FIFO
[3:0] RW tx_fifo_threshold tx_right_depth<(tx_fifo_threshold+1)
DMA
SIO_RX_STA
SIO

7-24 02 (2010-01-19)

Hi3520
7

0x068 SIO_RX_STA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rx_right_depth
Name reserved rx_left_depth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:10] - reserved
FIFO
[9:5] RO rx_left_depth
I2S
I2S FIFO
[4:0] RO rx_right_depth
PCM PCM FIFO
SIO_TX_STA
SIO

0x06C SIO_TX_STA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved tx_left_depth tx_right_depth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:10] RO reserved
FIFO
[9:5] RO tx_left_depth
I2S
I2S FIFO
[4:0] RO tx_right_depth
PCM PCM FIFO
SIO_DATA_WIDTH_SET
I2S/PCM

02 (2010-01-19) 7-25

Hi3520
7

0x078 SIO_DATA_WIDTH_SET 0x0000_0009
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name reserved rx_mode tx_mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
[31:6] - reserved

0008bit
00116bit
01018bit
01120bit
[5:3] RW rx_mode 10024bit
10132bit
110111
I2S 16/18/20/24/32bit
PCM 8/16bit
8/16bit

0008 bit
00116bit
01018bit
01120bit
[2:0] RW tx_mode
10024bit
10132bit
110111
I2S 16/18/20/24/32bit
PCM 8/16bit
SIO_I2S_START_POS
I2S
I2S

7-26 02 (2010-01-19)

Hi3520
7

0x07C SIO_I2S_START_POS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
start_pos_write
start_pos_read
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
FIFO
[1] RW start_pos_write 0
1
FIFO
[0] RW start_pos_read 0
1
I2S_POS_FLAG
I2S
I2S


0x080 I2S_POS_FLAG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
start_pos_write
start_pos_read
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] - reserved
[1] RO start_pos_write FIFO

02 (2010-01-19) 7-27

Hi3520
7
0
1
FIFO
[0] RO start_pos_read 0
1
SIO_SIGNED_EXT
PCM
I2S
8/16/18/20/24 bit
32bit 32bit bit
FIFO
16bit
if(data_rx[15]==1)
data_rx[31:16]=0xffff;
else
data_rx[31:16]=0x0000;

0x084 SIO_SIGNED_EXT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
signed_ext_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved

[0] RW signed_ext_en 0
1
SIO_I2S_POS_MERGE_EN
I2S

7-28 02 (2010-01-19)

Hi3520
7
I2S DMA SIO FIFO

CPU DMA CPU CPU

SIO_I2S_DUAL_RX_CHN
SIO_I2S_DUAL_TX_CHN

0x088 SIO_I2S_POS_MERGE_EN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
merge_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
I2S
[0] RW merge_en 0
1
SIO_INTMASK


0x08C SIO_INTMASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tx_right_fifo_under
rx_right_fifo_over
tx_left_fifo_under
rx_left_fifo_over
rx_intr
tx_intr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
[31:6] - reserved

02 (2010-01-19) 7-29

Hi3520
7
I2S FIFO PCM

[5] RW tx_left_fifo_under
0
1
I2S FIFO PCM

PCM FIFO
[4] RW tx_right_fifo_under
0
1
I2S FIFO PCM

[3] RW rx_left_fifo_over
0
1
I2S FIFO PCM

PCM FIFO
[2] RW rx_right_fifo_over
0
1
FIFO
[1] RW tx_intr 0
1
FIFO
[0] RW rx_intr 0
1
SIO_I2S_DUAL_RX_CHN
I2S

0x0A0 SIO_I2S_DUAL_RX_CHN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rx_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO rx_data

7-30 02 (2010-01-19)

Hi3520
7
SIO_I2S_DUAL_TX_CHN
I2S

0x0C0 SIO_I2S_DUAL_TX_CHN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name tx_data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] WO tx_data

02 (2010-01-19) 7-31

Hi3520
8 MMC/SD/SDIO
8 MMC/SD/SDIO
8.1
MMC/SD/SDIO MMC SD/MMC
SDIOSecure Digital Input/Output Blue
ToothWiFi MMC

z SD mem-version 2.00
z SDIO-version 1.10
z MMC-version 4.2
8.2
MMC
z DMA
z 2 FIFO 16%32bit
z FIFO DMA burst
z FIFO
z CRC
z
z MMC
z
z 1bit 4bit
z 1byte65535byte
z MMC
z 1bit 4bit SDIO
z SDIO suspend resume
z SDIO read wait

02 (2010-01-19) 8-1

Hi3520
8 MMC/SD/SDIO
8.3
MMC 8-1
8-1 MMC
SDIOCK O VO VO1CK
8.5.1

SDIOCMD I/O VO VO1DAT2

8.5.1
SDIODAT0 I/O 0 VO VO1DAT3

8.5.1

8.5.1

8.5.1

8.5.1
MMC_CCLKMMC_CMDMMC_DAT0MMC_DAT3 CLKCMD
DAT03
8.4
MMC 8-1

8-2 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
8-1 MMC
RDAT RCMD
CMD
DAT0-3
CLK
MMC
C1 C2 C3 91 2 3 4 5 678
8-1 GPIO
2
MMC 1 1 4

8-2
8-2
RDATRCMD 10k 100k
Cx - 40pF Cx = Cmmchost + Cbus + Ccard

Ccard 10pF
Cmmchost + Cbu s 30pF
- 16nH Fpp 20MHz
MMC 8-2

02 (2010-01-19) 8-3

Hi3520
8 MMC/SD/SDIO
8-2 MMC
MMC
cmd
reg cmd
resp path CMD
CPU
reg MMC/SD/
DAT0-3
BUS
cpu SDIO card
divider & clk cntrl CLK
if
DMA
txfifo
data
path
rxfifo
MMC

z

z

z

MMC

z
MMC CMD
z
DAT0-3

z

z

z
CIDCSD

8-4 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
MMC 8-3
8-6 8-7
8-3 MMC
from MMC from MMC from card

to card to card to MMC
CMD command command response
DAT
operation(no response) operation(long/short response)
48bit
CRC
48bit 136bit MMC 8-4 8-5

8-4 MMC
transmission bit command content:command and

'1'= mmc command address information or parameter,
protected by 7 bit CRC checksum
start bit end bit
always '0' always '1'
0 1 CONTENT CRC 1
total length = 48 bits
8-5
transmission bit response content:mirrored command and

'0'= card response status information(R1 response),OCR
register(R3 response) or RCA(R6),
protected by 7 bit CRC checksum
start bit end bit
always '0' always '1'
short response 0 0 CONTENT 1
long response 0 0 CONTENT=CID or CSD CRC 1

02 (2010-01-19) 8-5

Hi3520
8 MMC/SD/SDIO
MMC/SD/SDIO
z stream
MMC 1 DAT0 CRC
z single block

z multiple block
predefined block count

open ended

SD open
ended MMC
SDIO

SD/MMC
512 SDIO

8-6 8-7
8-6
from MMC from card data from stop command

to card to MMC card to MMC stops data transfer
CMD command response command response
DAT data block CRC data block CRC data block CRC
block read operation data stop operation

multiple block read operation
MMC
CRC
open ended

8-6 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
8-7
CRC ok response stop command

from MMC from card data from
and busy from stops data
to card to MMC MMC to card
card to mmc transfer
CMD command response command response
DAT data block CRC busy data block CRC busy

block write operation data stop operation
multiple block write operation
MMC
CRC CRC
CRC
open ended
flash
DAT0

1bit 4bit
1bit
4bit MMC_CTYPE
1bit 4bit
8-8 8-9
8-8 1bit
Start bit End bit
1st Byte 2nd Byte 3rd Byte nth Byte

DAT0 0 ... CRC 1
Data Data Data Data
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

02 (2010-01-19) 8-7

Hi3520
8 MMC/SD/SDIO
8-9 4bit
Start bit End bit
DAT3 0 b7 b3 b7 b3 b7 b3 ... b7 b3 CRC 1
DAT2 0 b6 b2 b6 b2 b6 b2 ... b6 b2 CRC 1
DAT1 0 b5 b1 b5 b1 b5 b1 ... b5 b1 CRC 1
DAT0 0 b4 b0 b4 b0 b4 b0 ... b4 b0 CRC 1
8.5
8.5.1
MMC GPIO MMC IO Config
MMC reg48reg52
8.5.2
MMC

1 MMC_STATUS
2 MMC_STATUS[7:4]MMC_STATUS[10] 0 MMC_CTRL 0
DMA 3 0
1
3 SC_PERDIS[mmc_clkdis] 1
4 SC_PEREN[mmc_clken] 1
----
8.5.3

SC_PERCTRL8[mmc_srst] 1
MMC_STATUS[data_fsm_busy]

8-8 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
8.5.4
MMC MMC
PLL PLL
FMMCCLK = FPLL/[(2%mmcclk_sel) + 8]
mmcclk_sel SC_PERCTRL9[mmcclk_sel]MMCCLK
FMMCCLK 50MHz
MMC

MMCCLK MMC_CCLK
FMMC_CCLK = FMMCCLK/2%clk_divider
clk_divider MMC_CLKDIV[clk_divider]
z MMC_CMD[start_cmd] MMC_CMD[update_clk_only] 1
MMC_CLKDIVMMC_CLKENA
MMC_CMD[start_cmd]
HLE(Hardware Locked Error) HLE
z
1 MMC_CLKENA 0x0000_0000
MMC_CMD[start_cmd]MMC_CMD[update_clk_regs_only]
MMC_CMD[wait_prvdata_complete] 1 MMC_CMD[start_cmd]

2 MMC_CLKDIV
MMC_CMD[start_cmd] MMC_CMD[update_clk_regs_only] 1
MMC_CMD[start_cmd]
3 MMC_CLKENA 0x0000_0001
MMC_CMD[start_cmd] MMC_CMD[update_clk_regs_only] 1
MMC_CMD[start_cmd]
----

02 (2010-01-19) 8-9

Hi3520
8 MMC/SD/SDIO
8.5.5
MMC
1 IO Config MMC 8.5.1

2 MMC 8.5.4
3 MMC 8.5.3

4 MMC_RINTSTS 1
5 MMC_INTMASK 1 DMA
/ FIFO
MMC_INTMASK[txdr_int_mask]MMC_INTMASK[rxdr_int_mask] 0
6 MMC_CTRL[int_enable] 1 DMA
MMC_CTRL[dma_enable] 1 DMA
7 MMC_TMOUT
8 FIFO MMC_FIFOTH DMA burstsize

rx_wmarktx_wmark
----
8.5.6
MMC
MMC_RINTSTS[cmd_done] MMC_RESP0
MMC_RESP0MMC_RESP3 MMC_RESP3[31]
MMC_RESP0[0]
MMC_RINTSTS
MMC_CMD[start_cmd] 1MMC_CMD[Update_clk_only] 0
MMC_BYTCNTMMC_BLKSIZMMC_CMDARGMMC_CMD
MMC_CMD[start_cmd]
HLE HLE
MMC_BYTCNTMMC_BLKSIZ
1 MMC_CMDARG

8-10 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
2 MMC_CMD 8-3
3 MMC MMC_CMD[start_cmd]

4 MMC_RINTSTS[hle_int_status] HLE
5 MMC
MMC_RINTSTS[cmd_done] 1
6 MMC_RINTSTS[rto_int_status]
MMC_RINTSTS[rcrc_int_status]MMC_RINTSTS[re_int_status]
CRC
----
8-3 MMC_CMD
start_cmd 1
update_clk_regs_only 0
data_expected 0
cmd_index Cmd index
send_initialization 0 1 CMD0
stop_abort_cmd 0 1 CMD12
rsponse_length 0 1
rsponse_expect 1 0CMD0CMD4
CMD15
wait_prvdata_complete 10
1

check_response_crc 10 CRC
8.5.7

1 MMC_CTRL[fifo_reset] 1 FIFO 0
2 MMC_BYTCNT
3 MMC_BLKSIZ

02 (2010-01-19) 8-11

Hi3520
8 MMC/SD/SDIO
4 MMC_CMDARG
5 8-4 MMC_CMD SD/MMC

CMD17/CMD18 / SDIO CMD53 /
MMC_CMD MMC
cmd_done
6 MMC_RINTSTS[rxdr_int_status] MMC_RINTSTS[hto_int_status]
1 1 MMC_DATA FIFO MMC
MMC_RINTSTS[7]
MMC_RINTSTS[9]MMC_RINTSTS[13] MMC_RINTSTS[15]

7 MMC_RINTSTS[dto_int_status] 1 MMC_DATA
FIFO
8 MMC_CMD[send_auto_stop] 1
8.5.11 Auto-stop
----
8-4 MMC_CMD
start_cmd 1
card_number 0 -
stop_abort_cmd 0 1 CMD12
send_auto_stop 0 or 1 8.5.11 Auto-stop
transfer_mode 0
read_write 0
rsponse_length 0
data_expected 1
rsponse_expect 1 0CMD0CMD4
CMD15
cmd_index Cmd index

8-12 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
1

8.5.8

1 MMC_CTRL[fifo_reset] 1 FIFO 0
2 MMC_BYTCNT
3 MMC_BLKSIZ
4 MMC_CMDARG
5 FIFO MMC_DATA FIFO
6 8-5 MMC_CMD SD/MMC CMD24/CMD25

/ SDIO CMD53 /
7 MMC_RINTSTS[txdr_int_status] MMC_RINTSTS[hto_int_status]
1 1 MMC_DATA FIFO
MMC_RINTSTS[7]MMC_RINTSTS[9]MMC_RINTSTS[13]
MMC_RINTSTS[15]
MMC_RINTSTS[dto_int_status] 1
8 MMC_CMD[send_auto_stop] 1
8.5.11 Auto-stop
9 MMC_STATUS[data_busy] 1 0
----
8-5 MMC_CMD
Default
start_cmd 1
card_number 0 -

02 (2010-01-19) 8-13

Hi3520
8 MMC/SD/SDIO
stop_abort_cmd 0 1
CMD12
send_auto_stop 0 or 1 8.5.11 Auto-stop
transfer_mode 0
read_write 1
rsponse_length 0
data_expected 1
rsponse_expect 1 0CMD0
CMD4CMD15
cmd_index Cmd index -


1

8.5.9
MMC_CMD[transfer_mode] 1
auto-stop
8.5.10 DMA
DMA MMC_CMD[dma_enable] 1
DMA MMC_INTMASK[txdr_int_mask]
MMC_INTMASK[txdr_int_mask] 0 Receive FIFO data request
Transmit FIFO data request
DMA
1 FIFO
2 MMC_BYTCNTMMC_BLKSIZMMC_CMDARGMMC_CMD

3 DMA DMAC_CX_SRC_ADDR
DMAC_CX_DEST_ADDRDMAC_CX_CONTROLDMAC_CX_CONFIG
DMA DMAC_CX_LLI

4 DMA

8-14 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
6 MMC_STATUS[data_busy]
----

z DMA DTOData Transfer Over
FIFO
Rx_wmark FIFO
DTO FIFO
z DMA FIFO DMA
DTO
z FIFO
15 16 FIFO DMA
DMA 16 MMC_BYTCNT
15 15 15
FIFO 16
8.5.11 Auto-stop

auto-stop auto-stop

MMC_CMD[send_auto_stop] 1

MMC_RINTSTS[auto_cmd_done] MMC_RESP1

Auto-stop
z SD
CMD18 CMD25
z MMC

open-ended CMD18 CMD25
predefined block count auto-stop
CMD18 CMD25 CMD23
z SDIO
auto-stop
8.5.12
MMC I/O
SDIO_IOONLY SDIO_COMBO
z

02 (2010-01-19) 8-15

Hi3520
8 MMC/SD/SDIO

MMC_CMD[5:0] CMD12 MMC_CMD[14]
1 MMC_CMD[13] 0
z
SDIO_IOONLY SDIO_COMBO
CMD52 SDIO CCCR[ASx]
8.5.13 Suspend Resume

SDIO 7 suspend
SD
resume

Suspend Resume SDIO CCCR

CCCR CMD52
Suspend
1 CCCR SBS SDIO suspend/resume
2 CCCR FSx BS
BS 1 FSx
3 CCCR BR 1
4 CCCR BSBus BRBus BS

1BR 1 BR
BS 0
5 suspend
MMC_CTRL[abort_read_data]
MMC_CTRL[abort_read_data]
6 MMC_TCBCNT
----
Resume
2 disconnect CMD7
CMD52/CMD53
3 CCCR RFx
RF=1
4 CMD52 CCCR FSx

CMD52 MMC_BLKSIZ
MMC_BYTCNT MMC_CMDARG
8-6 MMC_CMD

8-16 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
5 CMD52 DFResume Data Flag

1 0

6 DF 0

----
8-6 Resume MMC_CMDARG
MMC_CMDARG
bit[31] 0x1
bit[30:28] 0x0 CCCR
bit[27] 0x1
bit[26] - -
bit[25:9] 0x0D
bit[8] - -
bit[7:0]
8.5.14 Read wait

Read wait SDIO

1 read wait CCCR SRW 1

read wait CMD52
2 read wait MMC_CTRL[read_wait] 1
3 MMC_CTRL[read_wait]
----
8.6
MMC 8-7
8-7 MMC 0x1003_0000
0x000 MMC_CTRL 8-19

02 (2010-01-19) 8-17

Hi3520
8 MMC/SD/SDIO
0x004 RESERVED -
0x008 MMC_CLKDIV 8-20
0x00C RESERVED -
0x010 MMC_CLKENA 8-21
0x014 MMC_TMOUT 8-21
0x018 MMC_CTYPE 8-22
0x01C MMC_BLKSIZ 8-22
0x020 MMC_BYTCNT 8-23
0x024 MMC_INTMASK 8-23
0x028 MMC_CMDARG 8-25
0x02C MMC_CMD 8-26
0x030 MMC_RESP0 0 8-28
0x034 MMC_RESP1 1 8-28
0x038 MMC_RESP2 2 8-29
0x03C MMC_RESP3 3 8-29
0x040 MMC_MINTSTS 8-29
0x044 MMC_RINTSTS 8-31
0x048 MMC_STATUS 8-34
0x04C MMC_FIFOTH FIFO 8-35
0x05C MMC_TCBCNT 8-37
0x060 MMC_TBBCNT FIFO 8-37
0x0640xFF RESERVED -
0x100 MMC_DATA 8-38

8-18 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
8.7
MMC_CTRL
MMC_CTRL MMC
DMA

0x000 MMC_CTRL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
send_irq_response
abort_read_data
dma_enable
int_enable
dma_reset
read_wait
fifo_reset
reserved
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:9] - reserved 0 1

0
[8] RW abort_read_data 1 suspend
suspend
block IDLE
IDLE 0
0
1 IRQ
0
[7] RW send_irq_response
MMC CMD40
MMC
CMD40 IDLE

0
[6] RW read_wait 1
SDIO

02 (2010-01-19) 8-19

Hi3520
8 MMC/SD/SDIO
DMA
0
[5] RW dma_enable 1
DMA CPU FIFO
DMA CPU FIFO

0
[4] RW int_enable 1

[3] - reserved
DMA
0
[2] RW dma_reset
1
1 0
FIFO
0 FIFO
[1] RW fifo_reset
1 FIFO
1 0
[0] - reserved 0 1
MMC_CLKDIV
MMC_CLKDIV
MMCCLK MMC_CCLK
FMMC_CCLK=FMMCCLK/2%clk_divider MMC_CMD[start_cmd]
MMC_CMD[Update_clk_only] 1

0x008 MMC_CLKDIV 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved clk_divider
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved

8-20 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO

[7:0] RW clk_divider
0x0 0x1 2 0xFF 510
MMC_CLKENA
MMC_CLKENA MMC MMC_CMD[start_cmd]
MMC_CMD[Update_clk_only] 1

0x010 MMC_CLKENA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cclk_low_power
cclk_enable
Name reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] - reserved

0
[16] RW cclk_low_power 1 IDLE
MMCSD SDIO
SDIO
[15:1] - reserved

[0] RW cclk_enable 0
1
MMC_TMOUT
MMC_TMOUT

02 (2010-01-19) 8-21

Hi3520
8 MMC/SD/SDIO

0x014 MMC_TMOUT 0xFFFF_FF40
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name data_timeout response_timeout
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0
data starvation
[31:8] RW data_timeout
0xFF_FFFF
[7:0] RW response_timeout 0xFF
MMC_CTYPE
MMC_CTYPE 1bit 4bit


0x018 MMC_CTYPE 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
card_width
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved 16 1

[0] RW card_width 01bit
14bit
MMC_BLKSIZ
MMC_BLKSIZ SD/MMC 512 SDIO

8-22 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO

0x01C MMC_BLKSIZ 0x0000_0200
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved block_size
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] RW block_size 0x0200 512
MMC_BYTCNT
MMC_BYTCNT


0x020 MMC_BYTCNT 0x0000_0200
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name byte_count
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0x0200
[31:0] RW byte_count
512 block size
MMC_INTMASK
MMC_INTMASK MMC_RINTSTS

02 (2010-01-19) 8-23

Hi3520
8 MMC/SD/SDIO

0x024 MMC_INTMASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dcrc_int_mask
sdio_int_mask
frun_int_mask
rxdr_int_mask
drto_int_mask
txdr_int_mask
rcrc_int_mask
ebe_int_mask
acd_int_mask
sbe_int_mask
hto_int_mask
dto_int_mask
hle_int_mask
rto_int_mask
cd_int_mask
re_int_mask
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] - reserved
SDIO
[16] RW sdio_int_mask 0
1
EBEEnd-bit error
[15] RW ebe_int_mask 0
1
ACDAuto Command Done

[14] RW acd_int_mask 0
1
SBEStart-bit Error
[13] RW sbe_int_mask 0
1
HLEHardware Locked Write Error

[12] RW hle_int_mask 0
1
FRUNFIFO underrun/overrun error

[11] RW frun_int_mask 0
1
HTOData starvation-by-host timeout

[10] RW hto_int_mask 0
1
DRTOData Read Timeout

[9] RW drto_int_mask 0
1

8-24 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
RTOResponse Timeout
[8] RW rto_int_mask 0
1
DCRCData CRC error

[7] RW dcrc_int_mask 0
1
RCRCResponse CRC error

[6] RW rcrc_int_mask 0
1
RXDRReceive FIFO data request

[5] RW rxdr_int_mask 0
1
TXDRTransmit FIFO data request

[4] RW txdr_int_mask 0
1
DTOData Transfer Over

[3] RW dto_int_mask 0
1
CDCommand done
[2] RW cd_int_mask 0
1
REResponse error
[1] RW re_int_mask 0
1
[0] - reserved
MMC_CMDARG
MMC_CMDARG MMC_CMD[5:0]
cmd17 MMC_CMD[5:0]=17
SD/MMC/SDIO

02 (2010-01-19) 8-25

Hi3520
8 MMC/SD/SDIO

0x028 MMC_CMDARG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cmd_arg
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:0 RW cmd_arg
MMC_CMD
MMC_CMD


0x02C MMC_CMD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
wait_prvdata_complete
data_transfer_expected
update_clk_reg_only
check_repsonse_crc
send_initialization
response_expect
response_length
stop_abort_cmd
send_auto_stop
transfer_mode
read/write
start_cmd
Name reserved card_number cmd_index
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

update_clk_reg_only update_clk_reg_only
0 1 update_clk_reg_only
[31] RW start_cmd 1 1
0
1 CPU
hardware lock error
0
1
update_clk_reg_onl
[21] RW MMC_CLKDIVMMC_CLKENA
y

8-26 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
0
MMC_CMDMMC_CMDARGMMC_TMOUT
MMC_CTYPEMMC_BLKSIZMMC_BYTCNT

1 Command
Done
[20:16] RW card_number 0
0
180
[15] RW send_initialization
80

0
[14] RW stop_abort_cmd
1
1 IDLE
0
wait_prvdata_comp 1
[13] RW
lete 0

0
1

[12] RW send_auto_stop
predefined block count cmd53
open-ended

0
[11] RW transfer_mode 1

0
[10] RW read/write 1

data_transfer_expec 0
[9] RW
ted 1
0 CRC
[8] RW check_repsonse_crc 1 CRC
CRC CRC

02 (2010-01-19) 8-27

Hi3520
8 MMC/SD/SDIO
0
[7] RW response_length
1
0
[6] RW response_expect
1
[5:0] RW cmd_index
MMC_RESP0
MMC_RESP0 0

0x030 MMC_RESP0 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name response0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO response0 48bit bit[39:8] 136 bit[31:0]
MMC_RESP1
MMC_RESP1 1

0x034 MMC_RESP1 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name response1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit[63:32] auto-stop
auto-stop bit[39:8]
[31:0] RO response1 MMC_RESP0
Auto-stop

8-28 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
MMC_RESP2
MMC_RESP2 2

0x038 MMC_RESP2 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name response2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO response2 bit[95:64]
MMC_RESP3
MMC_RESP3 3

0x03C MMC_RESP3 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name response3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO response3 bit[127:96]
MMC_MINTSTS
MMC_MINTSTS MMC_MINTSTS = MMC_RINTSTS &
MMC_INTMASK MMC_RINTSTS MMC_INTMASK 1
MMC_CTRL[int_enable] 1

02 (2010-01-19) 8-29

Hi3520
8 MMC/SD/SDIO

0x040 MMC_MINTSTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
dcrc_int
sdio_int
frun_int
rxdr_int
drto_int
txdr_int
rcrc_int
ebe_int
acd_int
sbe_int
hto_int
dto_int
hle_int
rto_int
cd_int
re_int
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] - reserved
SDIO
[16] RO sdio_int 0
1
EBEEnd-bit error (read)/Write no CRC

[15] RO ebe_int 0
1

[14] RO acd_int 0
1
SBEStart-bit Error
[13] RO sbe_int 0
1

[12] RO hle_int 0
1

[11] RO frun_int 0
1
HTOData starvation-by-host timeout

[10] RO hto_int 0
1

[9] RO drto_int 0
1

8-30 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
RTOResponse Timeout
[8] RO rto_int 0
1
DCRCData CRC error

[7] RO dcrc_int 0
1

[6] RO rcrc_int 0
1

[5] RO rxdr_int 0
1

[4] RO txdr_int 0
1

[3] RO dto_int 0
1
CDCommand done
[2] RO cd_int 0
1
REResponse error
[1] RO re_int 0
1
[0] - reserved
MMC_RINTSTS
MMC_RINTSTS 1 0 0 1

02 (2010-01-19) 8-31

Hi3520
8 MMC/SD/SDIO

0x044 MMC_RINTSTS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rcrc_int_stattus
dcrc_int_status
sdio_int_status
frun_int_status
rxdr_int_status
drto_int_status
txdr_int_status
ebe_int_status
acd_int_status
sbe_int_status
hto_int_status
dto_int_status
hle_int_status
rto_int_status
cd_int_status
re_int_status
reserved
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] - reserved
SDIO
[16] RW sdio_int_status 0
1
EBEEnd-bit error (read)/Write no CRC

0
[15] RW ebe_int_status
1 end bit CRC
CRC

[14] RW acd_int_status 0
1 auto-stop
SBEStart-bit Error
0
[13] RW sbe_int_status
1 start bit 4bit
start bit

0
[12] RW hle_int_status
1


0
[11] RW frun_int_status
1 FIFO FIFO FIFO FIFO

Data starvation-by-host timeoutHTO
[10] RW hto_int_status 0
1 FIFO
FIFO

8-32 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
MMC_CCLKdata-starvation

FIFO FIFO
FIFO


[9] RW drto_int_status 0
1
RTOResponse Timeout
[8] RW rto_int_status 0
1
DCRCData CRC error

[7] RW dcrc_int_status 0
1 CRC

[6] RW rcrc_int_status 0
1 CRC

0
[5] RW rxdr_int_status 1 FIFO FIFO
rx_wmark DMA


0
[4] RW txdr_int_status 1FIFO FIFO
tx_wmark DMA


0
[3] RW dto_int_status
1 Start Bit ErrorCRC error
Read Data Timeout
CDCommand done
0
[2] RW cd_int_status 1 response
errorresponse CRC error response timeout

02 (2010-01-19) 8-33

Hi3520
8 MMC/SD/SDIO
REResponse error
[1] RW re_int_status 0
1
[0] - reserved
MMC_STATUS
MMC_STATUS MMC

0x048 MMC_STATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fifo_rx_watermark
fifo_tx_watermark
data_fsm_busy
data_3_status
fifo_empty
data_busy
dma_ack
dma_req
fifo_full
Name fifo_count resp_index cmd_fsm_state
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA
[31] RO dma_req 0 DMA
1 DMA
DMA
[30] RO dma_ack 0DMAC MMC
1DMAC MMC
[29:17] RO fifo_count FIFO word
[16:11] RO resp_index auto-stop
/
[10] RO data_fsm_busy 0/
1/
0
1
[9] RO data_busy data[0]
1 0

[8] RO data_3_status data[3]

8-34 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO

0x0Idle
0x1Send init sequence
0x2Tx cmd start bit
0x3Tx cmd tx bit
0x4Tx cmd index +arg
0x5Tx cmd crc7
0x6Tx cmd end bit
[7:4] RO cmd_fsm_state 0x7Rx resp start bit
0x8Rx resp IRQ response
0x9Rx resp tx bit
0xARx resp cmd idx
0xBRx resp data
0xCRx resp crc7
0xDRx resp end bit
0xECmd path wait NCC
0xFWaitCMD-to-response turnaround
FIFO
[3] RO fifo_full 0FIFO
1FIFO
FIFO
[2] RO fifo_empty 0FIFO
1FIFO
[1] RO fifo_tx_watermark FIFO tx_wmark
[0] RO fifo_rx_watermark FIFO rx_wmark
MMC_FIFOTH
MMC_FIFOTH MMC FIFO 0x2007_0008 DMA
DMA burst DMA

02 (2010-01-19) 8-35

Hi3520
8 MMC/SD/SDIO

0x04C MMC_FIFOTH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name burst_size rx_wmark resevered tx_wmark
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31] - reserved
DMA burst word

DMAC
0001
0014
0108

burst_size tx_wmark
Burst_size = 1Tx_wmark = 115
[30:28] RW burst_size
burst_size rx_wmark
Burst_size = 1Rx_wmark = 014
FIFO FIFO
DMA
DMA receive FIFO data requestRXDR
FIFO
[27:16] RW rx_wmark Data Transfer Over

DMA
DMA Data Transfer Over burst

8-36 02 (2010-01-19)

Hi3520
8 MMC/SD/SDIO
Tx_wmark FIFO_DEPTH 2
(FIFO_DEPTH/2) 1(FIFO_DEPTH / 2) 1)

[15:12] - resevered
FIFO FIFO
DMA
DMA transmit FIFO data requestTXDR

[11:0] RW tx_wmark
DMA burst
sizeDMA burst
Tx_wmark 1
FIFO_DEPTH/2 FIFO_DEPTH/2

MMC_TCBCNT
MMC_TCBCNT
0
0

0x05c MMC_TCBCNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name trans_card_byte_coun
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
trans_card_byte_co
[31: 0] RO
unt
MMC_TBBCNT
MMC_TBBCNT FIFO
CPU/DMA FIFO
0

02 (2010-01-19) 8-37

Hi3520
8 MMC/SD/SDIO

0x060 MMC_TBBCNT 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name trans_fifo_byte_count
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
trans_fifo_byte_co
[31: 0] RO CPU/DMA FIFO
unt
MMC_DATA
MMC_DATA FIFO FIFO
MMC_STATUS[fifo_count] FIFO
FIFO

0x100 MMC_DATA 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name fifo_entrance
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW fifo_entrance FIFO

8-38 02 (2010-01-19)

Hi3520
9 PCI
9 PCI
9.1
PCIPeripheral Component InterconnectLocal Bus
PCI
PCI/miniPCI SATAWiFiPCI-to-PCI Bridge
Hi3520 PCI PCI AHBAdvanced High-performance

Bus PCI2.3 miniPCI Hi3520 PCI
PCI Host PCI Device
z Host
Host PCI PCI

z Device
Device PCI Device PCI PCI
Host PCI PCI
9.2
Hi3520 PCI
z PCI2.3
z 32bit 66MHz
z PCI Host PCI Device
PCI Host
PCI_INTAPCI_INTB
memory read/writeconfiguration read/write
Type0 Type1
PCI Bus Abiter 5 PCI
PCI Device
PCI_INTA

02 (2010-01-19) 9-1

Hi3520
9 PCI
memory read/writeI/O read/writeconfiguration read/write

PCI AHB
z doorbell
z PCI
z memory prefetchable non-prefetchable
9.3
PCI 9-1
9-1 PCI
PCI
z PCI Host PCI
PCI_CLK
PCI
PCI
PCI_CLK I/O PCICLK
Host PCI
PCI
PCI_CLK
z PCI Device PCI_CLK

PCI
z PCI Host PCI_RST

PCI_RST I/O PCIRSTN
PCI_RST
z PCI Device PCI_RST

PCI_AD[31:0] I/O PCI / PCIAD31PCIAD0
PCICBE3
PCI_CBE[3:0] I/O PCI /
PCICBE0
PCI_FRAME I/O PCI frame PCIFRAMEN
PCI_IRDY I/O PCI initiator ready PCIIRDYN
PCI_TRDY I/O PCI target ready PCITRDYN
PCI_DEVSEL I/O PCI device select PCIDEVSELN
PCI_STOP I/O PCI stop PCISTOPN

9-2 02 (2010-01-19)

Hi3520
9 PCI
PCI initial device select

PCI_IDSEL I z PCI Device PCI_IDSEL PCIIDSEL
z PCI Host PCI_INTB
PCI_INTB I PCI INTB PCIIDSEL
PCI_PAR I/O PCI parity PCIPAR
PCI_SERR I/O PCI system error PCISERRN
PCI_PERR I/O PCI parity error PCIPERRN
PCI INTA
z PCI Host PCI_INTA
PCI_INTA I/O PCIINTAN
z PCI Device PCI_INTA

PCI bus request

z PCI Host PCI_REQ[4:0]

z PCI Device PCI_REQ[0]
PCI PCIREQ4N
PCI_REQ[4:0] I PCI_GNTPCI_REQ[4] PCIREQ0N
GPIO3_7

Hi3520 PCI Device
PCI_REQ[3:1]

PCI bus grant

z PCI Host PCI_GNT[4:0]

z PCI Device PCI_GNT[0]
PCI PCIGRANT4N
PCI_GNT[4:0] O PCI_REQPCI_GNT[4] PCIGRANT0N
GPIO7_1

Hi3520 PCI Device
PCI_REQ [3:1]

PCI PCI_FRAMEPCI_IRDYPCI_TRDYPCI_STOPPCI_DEVSEL
PCI_SERRPCI_PERRPCI_INTA PCI_INTB

02 (2010-01-19) 9-3

Hi3520
9 PCI
9.4
PCI 9-1
9-1 PCI
PCI Host
PCI Bus
PCI Device PCI Device ...... PCI Device
PCI PCI

Hi3520 PCI 9-2
9-2 Hi3520 PCI
DMA Channel
PCI Master
AHB-PCI window
AHB Interface
AHB Bus PCI Bus
Bridge/Configuration Reg.
PCI Target
PCI-AHB window
Hi3520 PCI DMACDMA DMA

ARM core AHB-PCI window PCI PCI PCI
PCI PCI-AHB window Hi3520

9-4 02 (2010-01-19)

Hi3520
9 PCI
PCI //
PCI memory I/O
9-3 9-5
9-3 PCI memoryI/O
1 2 3 4 5 6 7 8
CLK
AD[31:0] Addr data1 data2 data3
CBE[3:0] CMD Byte En.1 Byte En.2 BE3
RRAME
IRDY
TRDY
STOP
DEVSEL
9-4 PCI memoryI/O
1 2 3 4 5 6 7 8
CLK
AD[31:0] Addr data1 data2 data3 data4
CBE[3:0] CMD Byte En.1 BE2 BE3 BE4

RRAME
IRDY
TRDY
STOP
DEVSEL

02 (2010-01-19) 9-5

Hi3520
9 PCI
9-5 PCI
1 2 3 4 5
CLK
AD[31:0] Addr Cfg.Data
CBE[3:0] CFG CMD Byte Enable

IDSEL
RRAME
IRDY
TRDY
DEVSEL
9.5
9.5.1
PCI
z Hi3520 PCI Device
PCIREQ0N PCI PCIGRANT_SLAVEN
PCIGRANT0N PCI PCIREQ_SLAVEN
PCIREQ3NPCIREQ4NPCIGRANT3N PCIGRANT4N
GPIO3_6GPIO3_7GPIO7_0 GPIO7_1
z Hi3520 PCI Host PCIIDSEL PCI_INTB
z PCIREQ3NPCIREQ4NPCIGRANT3N PCIGRANT4N GPIO
IO_Config reg78reg81
GPIO PCI PCI HOST IO_Config
PCI PCIREQ3N PCIREQ4N
SC_PERCTRL11 bit[0] 1 PCI Host
z Hi3520 PCI Device PCIIDSELPCIREQ0N PCIGRANT0N

IO Config
z Hi3520 PCI Host PCIIDSEL IO Config
9.5.2
PCI PCI
z Hi3520 PCI Host PCI

9-6 02 (2010-01-19)

Hi3520
9 PCI
PCI Hi3520 Hi3520 PCI

PCI Hi3520 PCI
PCI
Hi3520 Hi3520 PCI

z Hi3520 PCI Device PCI PCI Hi3520
PCI PCI
Hi3520 PCI SC_PEREN bit[14] SC_PERDIS bit[14]

9.5.3
SC_PERCTRL11 bit[1] PCI Host
SC_PERCTRL11 bit[1] PCI

z SC_PERCTRL11 bit[1] 1 PCICLK PCI
PCICLK PCI
z SC_PERCTRL11 bit[1] 0 PCICLK PCI

PCI Device SC_PERCTRL11 bit[1] 0 PCI

Hi3520 PCI Host PCI Hi3520

SC_PERCTRL9 bit[24:23] PCI
SC_PERCTRL9 bit[24:23]
9.5.4
SC_PERCTRL8 bit[13] 1 PCI
PCI Host PCI Host
PCIRST PCI PCI Host
PCI Device
PCI Device SC_PERCTRL8 bit[13] 1

PCI PCI PCI
PCI Host PCI Device
Hi3520 PCI
SC_PERCTRL8 bit[13 1 PCI 4ms
SC_PERCTRL8 bit[13] 0
9.5.5

02 (2010-01-19) 9-7

Hi3520
9 PCI
PCIREQ PCIGRANT IO_CONFIG

PCI Hi3520 PCI Host
SC_PERCTRL11 bit[0] Hi3520 PCI Host

PCI Device
z SC_PERCTRL11 bit[0] 1 Hi3520 PCI Host
z SC_PERCTRL11 bit[0] 0 Hi3520 PCI Device
9.5.6 window
Hi3520 PCI Host AHB-PCI window PCI

window prefetchable non-prefetchable

Hi3520 AHB-PCI window ARM core PCI PCI

PCI PCI PCI-AHB window Hi3520
Hi3520 AHB-PCI window PCI

Hi3520 AHB-PCI window PCI
1 Hi3520 PCI Host PCI PCI
2 ARM core AHB AHB PCI

AHB-PCI window
----
Hi3520 PCI Master Memory WriteI/O WriteI/O Read Memory

Read Multiple

1 PCI Host PCI
2 PCI Hi3520 Hi3520 PCI Host PCI

Hi3520 AHB Hi3520
PCI Device PCI AHB

9-8 02 (2010-01-19)

Hi3520
9 PCI
----
Hi3520 PCI Target PCI Memory WriteMemory Read

Configuration Read with Type0/Type1Comfiguration Writer with Type0/Type1 Memory
Read Multiple
9.5.7 DMA
Hi3520 PCI DMAC PCI DMA ARM
core
z Hi3520 PCI Host DMA PCI

z Hi3520 PCI Device DMA PCI

Hi3520 PCI HOST PCI

DMA
Hi3520 PCI DMA 9-2
9-2 PCI
Read DMA 0010 I/O Read

0110 Memory Read
1010 Configuration Read
1100 Memory Read Multiple
Write DMA 0011 I/O Write
0111 Memory Write
1011 Configuration Write
9-2
Hi3520 PCI Host DMA
1 CPU_IMASK DMA Read/Write
2 RDMA_PCI_ADDR/WDMA_PCI_ADDR
3 RDMA_AHB_ADDR/WDMA_AHB_ADDR
4 DMA RDMA_CONTROL/WDMA_CONTROL
1. RDMA_CONTROL/WDMA_CONTROL[31:8] transfer size

2. RDMA_CONTROL/WDMA_CONTROL[7:4] command
3. RDMA_CONTROL/WDMA_CONTROL[3] pci_interrupt bit

02 (2010-01-19) 9-9

Hi3520
9 PCI
4. RDMA_CONTROL/WDMA_CONTROL[1] stop bit

5. RDMA_CONTROL/WDMA_CONTROL[0] start bit
----
Hi3520 PCI Device DMA
1 CPU_IMASK DMA Read/Write
2 RDMA_PCI_ADDR/WDMA_PCI_ADDR
3 RDMA_AHB_ADDR/WDMA_AHB_ADDR
4 DMA RDMA_CONTROL/WDMA_CONTROL
1. RDMA_CONTROL/WDMA_CONTROL[31:8] transfer size

2. RDMA_CONTROL/WDMA_CONTROL[7:4] command
3. RDMA_CONTROL/WDMA_CONTROL[3] pci_interrupt bit
4. RDMA_CONTROL/WDMA_CONTROL[1] stop bit
5. RDMA_CONTROL/WDMA_CONTROL[0] start bit
----
z Hi3520 PCI Host PCI Device DMA

CPU 1 CPU_IMASK

z Hi3520 PCI Host RDMA_CONTROL/WDMA_CONTROL[3] 0b0
9.6
Hi3520 PCI PCI V2.3 PCI AHB
CPU PCI
9.6.1 AHB
AHB 9-3
9-3 AHB 0xB000_0000
0x000 WDMA_PCI_ADDR DMA 9-13
0x004 WDMA_AHB_ADDR DMA 9-13
DMA transfer size 9-14

0x008 WDMA_CONTROL

9-10 02 (2010-01-19)

Hi3520
9 PCI
0x00C -
RESERVED
0x01C
0x020 RDMA_PCI_ADDR DMA 9-15
0x024 RDMA_AHB_ADDR DMA 9-15
DMA transfer size 9-15

0x028 RDMA_CONTROL

0x02C -
RESERVED
0x03C
0x040 CPU_IMASK 9-16
0x044 CPU_ISTATUS 9-19
0x048 CPU_ICMD 9-22
0x04C CPU_VERSION 9-22
0x050 -
RESERVED
0x06C
PCI-AHB 9-23
0x070 PCIAHB_ADDR_NP

PCI-AHB 9-24
0x074 PCIAHB_ADDR_PF

0x078 PCIAHB_TIMER PCI-AHB 9-24
0x07C AHBPCI_TIMER AHB-PCI 9-24
0x080 PCI_CONTROL PCI 9-25
0x084 PCI_DV PCI Vendor Vendor ID 9-26
PCI Subsystem Subsystem 9-26

0x088 PCI_SUB
Vendor ID
0x08C PCI_CREV PCI Class Code Revision ID 9-27
0x090 PCI_BROKEN PCI Master 9-27
0x094 PCIAHB_SIZE_NP PCI-AHB 9-28
0x098 PCIAHB_SIZE_PF PCI-AHB 9-28
0x09C -
RESERVED
0x3FC

02 (2010-01-19) 9-11

Hi3520
9 PCI
9.6.2 PCI
9-4 PCI
Vendor ID
0x000 9-29
Device ID
0x004 Command and Status 9-29
Revision ID and
0x008 9-30
Class Code
Cacheline Size
Cache PCI Master Latency
0x00C Master Latency Timer 9-31
Time
Head Typer
Base Address 0
0x010 0 -
BAR0
Base Address 1
0x014 1 -
BAR1
Base Address 2
0x018 2 -
BAR2
Base Address 3
0x01C 3 9-31
BAR3
Base Address 4
0x020 4 9-32
BAR4
Base Address 5
0x024 5 9-32
BAR5
0x028 Cardbus CIS Cardbus CIS 9-32
Subsystem Vendor ID
0x02C ID ID 9-33
Subsystem ID
0x030 RESERVED -
0x034 Capabilities Pointer 9-33
0x038 RESERVED -
Interrupt Line
Interrupt Pin
0x03C 9-34
Min_Gnt
Max_Lat

9-12 02 (2010-01-19)

Hi3520
9 PCI
0x040
RESERVED -
0x07C
0x080 PCI_IMASK PCI Device Only 9-34
0x084 PCI_ISTATUS PCI Device Only 9-35
0x088 PCI_ICMD PCI Device Only 9-36
0x08C PCI_VERSION PCI 9-37
0x090
RESERVED -
0x0FC
PCI_IMASKPCI_ISTATUSPCI_ICMD Hi3520 PCI Device
9.7
9.7.1 AHB
WDMA_PCI_ADDR
WDMA_PCI_ADDR DMA

0x000 WDMA_PCI_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdma pci addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW wdma pci addr DMA
WDMA_AHB_ADDR
WDMA_AHB_ADDR DMA

02 (2010-01-19) 9-13

Hi3520
9 PCI

0x004 WDMA_AHB_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name wdma ahb addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW wdma ahb addr DMA
WDMA_CONTROL
WDMA_CONTROL DMA transfer size

0x008 WDMA_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pci interrupt enable
start dma
stop dma
reserved
Name write DMA transfer size dma command
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
write DMA transfer DMA transfer size byte

[31:8] RW
size 16M 1Byte
[7:4] RW dma command DMA 9-2
PCI
0
1
[3] RW pci interrupt enable
DMA 1 DMA
PCI PCI_INTA PCI Host
Hi3520 PCI Device
Hi3520 PCI Host 0
[2] - reserved

9-14 02 (2010-01-19)

Hi3520
9 PCI
DMA
[1] RW stop dma 0DMA
1DMA
DMA
[0] RW start dma 0DMA
1 DMA
RDMA_PCI_ADDR
RDMA_PCI_ADDR DMA

0x020 RDMA_PCI_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rdma pci addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW rdma pci addr DMA
RDMA_AHB_ADDR
RDMA_AHB_ADDR DMA

0x024 RDMA_AHB_ADDR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name rdma ahb addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RW rdma ahb addr DMA
RDMA_CONTROL
RDMA_CONTROL DMA transfer size

02 (2010-01-19) 9-15

Hi3520
9 PCI

0x028 RDMA_CONTROL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
start dma
stop dma
reserved
pci int.
Name read DMA transfer size dma command
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
read dma transfer

[31:8] RW DMA transfer size byte 16MB
size
[7:4] RW dma command DMA 9-2
PCI
0
1
[3] RW pci int
DMA 1 DMA
PCI PCI_INTA PCI Host
Hi3520 PCI Device
Hi3520 PCI Host 0
[2] - reserved
DMA
[1] RW stop dma 0DMA
1DMA
DMA
[0] RW sart dma 0DMA
1 DMA
CPU_IMASK
CPU_IMASK

9-16 02 (2010-01-19)

Hi3520
9 PCI

0x040 CPU_IMASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
imask_pci_doorbell
parity_error
parity_error
fetch_error
fetch_error
imask_serr
dma_abort
dma_abort
post_error
post_error
ahb_error
ahb_error
dma_end
dma_end
reserved
reserved
discard
discard
Name reserved imask_pci_int. reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:29] - reserved
SERR
[28] RW imask_serr 0
1
PCI
[27:24] RW imask_pci_int. 0
1
[23:20] - reserved
PCI doorbell
[19:16] RW imask_pci_doorbell 0
1
[15] - reserved
AHB-PCI post
[14] RW imask_ahbpci_post 0
1
AHB-PCI fetch
imask_ahbpci_fetc
[13] RW 0
h
1
AHB-PCI discard
imask_ahbpci_disc
[12] RW 0
ard
1
DMA ahb_error
imask_rdma_ahb_e
[11] RW 0
rror
1

02 (2010-01-19) 9-17

Hi3520
9 PCI
DMA parity
[10] RW imask_rdma_parity 0
1
DMA abort
[9] RW imask_rdma_abort 0
1
DMA end
[8] RW imask_rdma_end 0
1
[7] - reserved
PCI-AHB post
[6] RW imask_pciahb_post 0
1
PCI-AHB fetch
imask_pciahb_fetc
[5] RW 0
h
1
PCI-AHB discard
imask_pciahb_disc
[4] RW 0
ard
1
DMA ahb_error
imask_wdma_ahb_
[3] RW 0
error
1
DMA parity
imask_wdma_parit
[2] RW 0
y
1
DMA abort
[1] RW imask_wdma_abort 0
1
DMA end
[0] RW imask_wdma_end 0
1

9-18 02 (2010-01-19)

Hi3520
9 PCI
CPU_ISTATUS
CPU_ISTATUS 1


0x044 CPU_ISTATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
istatus_pci_doorbell
parity_error
parity_error
istatus_serr
fetch_error
fetch_error
dma_abort
dma_abort
post_error
post_error
ahb_error
ahb_error
dma_end
dma_end
reserved
reserved
discard
discard
Name reserved istatus_pci_int. reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:29] - reserved
SERR
PCI Host istatus_serr PCI Host
PCI
[28] WC istatus_serr
PCI Device istatus_serr
0
1
PCI
0
1
[27:24] WC istatus_pci_int PCI Host istatus_pci_int
PCI_INTDPCI_INTCPCI_INTB PCI_INTA

PCI Device istatus_pci_int
[23:20] - reserved
PCI doorbell
0
1
PCI doorbell
istatus_pci_doorbel
[19:16] WC bit[19:16] PCI_ICMD[19:16] 4bit
l

PCI Device istatus_pci_doorbell

PCI Host istatus_pci_doorbell

02 (2010-01-19) 9-19

Hi3520
9 PCI
[15] - reserved
AHB-PCI post AHB

Master AHB Slave
PCI Master Abort
[14] WC istatus_ahbpci_post Target Abort
0
1
AHB-PCI fetch AHB

Master AHB Slave
istatus_ahbpci_fetc PCI Master Abort
[13] WC Target Abort
h
0
1
AHB-PCI discard AHB

AHB Master PCI Target
AHB Master Retry
istatus_ahbpci_disc
[12] WC
ard AHB Master
0
1
DMA ahb_error DMA

AHB Master AHB Slave Error
istatus_rdma_ahb_e Read DMA AHB error DMA
[11] WC RDMA_CONTROL 0bit 0
rror
0
1
DMA parity DMA

PCI
[10] WC istatus_rdma_parity
0
1
DMA abort DMA

PCI Master PCI Address
[9] WC istatus_rdma_abort PCI Device PCI Abort
0
1

9-20 02 (2010-01-19)

Hi3520
9 PCI
DMA end DMA

DMA DMA
Abort CPU DMA Abort
DMA End DMA Abort
[8] WC istatus_rdma_end RDMA_CONTROL0x28 0 bit

0
1
[7] - reserved
PCI-AHB post PCI Master

PCI-AHB AHB Slave
AHB Slave Error
[6] WC istatus_pciahb_post AHB Slave Error
0
1
PCI-AHB fetch PCI Master

PCI-AHB AHB Slave
istatus_pciahb_fetc AHB Slave Error
[5] WC AHB Slave Error
h
0
1
PCI-AHB discard PCI

PCI Master PCI Target
PCI Master Retry
istatus_pciahb_disc
[4] WC
ard PCI Master
0
1
DMA ahb_error DMA

AHB Master AHB Slave Error
istatus_wdma_ahb_ Write DMA AHB error DMA
[3] WC WDMA_CONTROL 0bit 0
error
0
1
DMA parity DMA

istatus_wdma_parit PCI
[2] WC
y 0
1

02 (2010-01-19) 9-21

Hi3520
9 PCI
DMA abort DMA

PCI Master PCI Address
istatus_wdma_abor PCI Device PCI Abort
[1] WC
t
0
1
DMA end DMA

DMA DMA
Abort CPU DMA Abort
DMA End DMA Abort
[0] WC istatus_wdma_end WDMA_CONTROL0x08 0 bit

0
1
CPU_ICMD
CPU_ICMD

0x048 CPU_ICMD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cpu_doorbell reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
CPU doorbell
CPU doorbell
[23:20] WO cpu doorbell bit[23:20]
PCI_INTA PCI Host CPU doorbell
Hi3520 PCI Device
[19:0] - reserved
CPU_VERSION
CPU_VERSION
z PCI Device 0x0000_1380

z PCI Host 0x0000_2380

9-22 02 (2010-01-19)

Hi3520
9 PCI

0x04C CPU_VERSION -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved device type device version
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[31:16] - reserved

[15:12] RO device type 0x1PCI Device
0x2PCI Host
[11:0] RO device version
PCIAHB_ADDR_NP
PCIAHB_ADDR_NP PCI-AHB
Hi3520 PCI Host PCIAHB_ADDR_NP[pciahb_addr_np]

PCIAHB_ADDR_PF[pciahb_addr_pf] PCI Base Address 3 Base
Address 4 PCI Device PCI Hi3520


0x070 PCIAHB_ADDR_NP 0xB000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
window_en
Name pciahb_addr_np reserved
Reset 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:8] RW pciahb_addr_np PCI-AHB AHB
[7:1] - reserved
PCI-AHB
[0] RW window_en 0
1

02 (2010-01-19) 9-23

Hi3520
9 PCI
PCIAHB_ADDR_PF
PCIAHB_ADDR_PF PCI-AHB

0x074 PCIAHB_ADDR_PF 0xB000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
window_en
Name pciahb_addr_pf reserved
Reset 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:8] RW pciahb_addr_pf PCI-AHB window AHB
[7:1] - reserved
PCI-AHB
[0] RW window_en 0
1
PCIAHB_TIMER
PCIAHB_TIMER PCI-AHB

0x078 PCIAHB_TIMER 0x0000_0100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved pciahb_discard
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
[31:12] - reserved
[11:0] RW pciahb_discard PCI-AHB window
AHBPCI_TIMER
AHBPCI_TIMER AHB-PCI

9-24 02 (2010-01-19)

Hi3520
9 PCI

0x07C AHBPCI_TIMER 0x0000_0100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved ahbpci_discard
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
[31:12] - reserved
[11:0] RW ahbpci_discard AHB-PCI window
PCI_CONTROL
PCI_CONTROL PCI


0x080 PCI_CONTROL -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
memory_en
master_en
pci_ready
Name reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[31:3] - reserved
PCI Master
[2] RW master_en 0
1
Memory
[1] RW memory_en 0
1
PCI
[0] RO pci_ready bit PCI 0 225 PCI

1CPU PCI

02 (2010-01-19) 9-25

Hi3520
9 PCI
z Hi3520 PCI Host PCI_CONTROL[master_en]PCI_CONTROL[memory_en]

PCI_CONTROL[pci_ready] PCI 1
z Hi3520 PCI Device PCI_CONTROL[master_en] PCI_CONTROL[memory_en]
PCI COMMAND_STATUS[1] COMMAND_STATUS[0]
PCI_CONTROL[master_en] PCI_CONTROL[memory_en] PCI
Host
PCI_DV
PCI_DV PCI Vendor Vendor ID

0x084 PCI_DV 0x3520_19E5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name device ID vendor ID
Reset 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1
[31:16] RO device ID ID
[16:15] RO vendor ID ID
PCI_SUB
PCI_SUB PCI Subsystem Subsystem Vendor ID

0x088 PCI_SUB 0x3520_19E5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name subsystem ID subsystem vendor ID
Reset 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1
[31:16] RO subsystem ID ID
subsystem vendor
[16:15] RO ID
ID

9-26 02 (2010-01-19)

Hi3520
9 PCI
PCI_CREV
PCI_CREV PCI Revision ID

0x8C PCI_CREV 0x0400_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name class_code revision
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
[31:8] RO class_code
[7:0] RO revision Revision ID
PCI_BROKEN
PCI_BROKEN PCI Master 1
PCI Master broken

0x090 PCI_BROKEN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved broken_status
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] - reserved
PCI Master broken bit PCI Host PCI

Master
[7] WC broken_status
0PCI Master OK
1PCI Master broken
PCI Master broken bit PCI_REQ[0]

PCI_GNT[0] PCI Device Master
[6] WC broken_status
0PCI Master OK
1PCI Master broken
[5:4] - reserved

02 (2010-01-19) 9-27

Hi3520
9 PCI
PCI Master broken PCI_BROKEN[3:0]

bridge_req[7:0] bridge_gnt[7:0]
[3:0] WC broken_status PCI Device Master
0PCI Master OK
1PCI Master broken
PCI PCI Master PCI 16 PCI PCI Host
PCI_BROKEN PCI Master 1PCI Master PCI PCI Host
Master CPU broken status
PCIAHB_SIZ_NP
PCIAHB_SIZ_NP PCI-AHB

0x094 PCIAHB_SIZ_NP 0xFFC0_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name pciahb_siz_np reserved
Reset 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] RW pciahb_siz_np PCI-AHB
[7:0] - reserved
PCIAHB_SIZ_PF
PCIAHB_SIZ_PF PCI-AHB

0x98 PCIAHB_SIZ_PF 0xFF80_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name pciahb_siz_pf reserved
Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] RW pciahb_siz_pf PCI-AHB
[7:0] - reserved

9-28 02 (2010-01-19)

Hi3520
9 PCI
9.7.2 PCI
Vendor ID and Device ID

Vendor ID and Device ID

0x000 Vendor ID and Device ID 0x3520_19E5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name device ID vendor ID
Reset 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1
[31:16] RO device ID ID
[16:15] RO vendor ID ID
Command and Status

Command and Status

0x004 Command &Status 0x04B0_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
devsel_timing
signal_abort
target_abort
parity_error
memory_en
fast_btb_en
special_cyc
master_abort
faste_btob
master_en
mem_w_i
66M_cap
int_ststus
perr_resp
VGA_en
maste_ perr
reserved
reserved
cap_list
serr_en
I/O_en
int.Ien
serr
Name reserved
Reset 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31] RW parity_error Device
[30] RW serr
[29] RW master_abort PCI master abort
[28] RW target_abort PCI target abort
[27] RW signal_abort abort
[26:25] RO devsel_timing
[24] RW master_perr Master

02 (2010-01-19) 9-29

Hi3520
9 PCI
[23] RO fast_btob
[22] - reserved
[21] RO 66M_cap 66MHz
[20] RO cap_list
[19] RO int_status
[18:11] - reserved
[10] RW int_en
[9] RO fast_btob
[8] RW serr_en SERR
[7] - reserved
[6] RW perr_resp
[5] RO VGA_en VGA
[4] RO mem_w_i_en
[3] RO special_cyc
[2] RW master_en
[1] RW memory_en
[0] RW I/O_en I/O
Revision ID and Class Code

Revision ID and Class Code

0x008 Revision ID and Class Code 0x0400_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name class code revision ID
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
[31:8] RO class code
[7:0] RO revision revision

9-30 02 (2010-01-19)

Hi3520
9 PCI
Cacheline Size and Master Latency Timer

Cacheline Size and Master Latency Timer Cache PCI Master Latency Time


0x00C Cacheline Size and Latency Timer 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Name bist head type master latency timer cacheline size
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - bist
[23:16] RO head type
master latency PCI master bit[9:8] 0b00

[15:8] RW
timer latency timer 8 PCI
cacheline
[7:0] RO cacheline size Hi3520 PCI Memory Cacheline
cacheline size 0x00
Base Address 3
Base Address 3 3

0x01C Base Address 3 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name base_address3 reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] RW base_address3 3
[7:0] - reserved

02 (2010-01-19) 9-31

Hi3520
9 PCI
Base Address 4
Base Address 4 4

0x020 Base Address 4 0x0000_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
prefet_flag
Name base address 4 reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
[31:0] RW base address 4 4
[7:4] - reserved
[3] RO prefet_flag
[2:0] - reserved
Base Address 5
Base Address 5 5

0x024 Base Address 5 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
prefet_flag
Name base address 5 reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
[31:4] RW base address 5 5
[3] RO prefet_flag
[2:0] - reserved
Cardbus CIS Pointer

Cardbus CIS Pointer Cardbus CIS

9-32 02 (2010-01-19)

Hi3520
9 PCI

0x028 Cardbus CIS Pointer 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name cardbus_cis_point
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO cardbus_cis_point Cardbus CIS
Subsystem Vendor ID and Subsystem ID

Subsystem Vendor ID and Subsystem ID ID ID

0x02C Subsystem Vendor ID and Subsystem ID 0x3511_19E5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name subsystem ID subsystem vendor ID
Reset 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1
[31:16] RO subsystem ID ID
subsystem vendor
[16:15] RO ID
ID
Capabilities Pointer
Capabilities Pointer
Hi3520 PCI PCI

02 (2010-01-19) 9-33

Hi3520
9 PCI

0x034 Capabilities Pointer 0x0000_0078
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved capabilities pointer
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0
[31:16] - reserved
[15:0] RO capabilities pointer
Interrupt Line Interrupt Pin MIN_GNT MAX_LAT

Interrupt Line Interrupt Pin MIN_GNT MAX_LAT
Register Name
Interrupt Line & Interrupt Pin &
0x03C 0x0000_0100
MIN_GNT & MAX_LAT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name max_lat min_lat interrupt pin interrupt line
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] RO max_lat MAX latency
[23:16] RO min_gnt MIN grant
[15:8] RO interrupt in
[7:0] RW interrupt line
PCI_IMASK
PCI_IMASK PCI Device Only

PCI_IMASKPCI_ISTATUSPCI_ICMD Hi3520 PCI Device

Hi3520 PCI PCI_INTA PCI Host

9-34 02 (2010-01-19)

Hi3520
9 PCI

0x080 PCI_IMASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
imask_cpu_doorbell
wdma_end
rdma_end
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
CPU Doorbell
imask_cpu_doorbel
[23:20] RW 0
l
1
[19:9] - reserved
DMA
[8] RW imask_rdma_end 0
1
[7:1] - reserved
DMA
[0] RW imask_wdma_end 0
1
PCI_ISTATUS
PCI_ISTATUS PCI Device Only
1

02 (2010-01-19) 9-35

Hi3520
9 PCI

0x084 PCI_ISTATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
istatus_cpu_doorbell
wdma_end
rdma_end
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:24] - reserved
CPU Doorbell
0
[23:20] WC cpu_doorbell 1
CPU_ICMD bit[23:20] CPU dooebell
Hi3520 PCI_INTA doorbell
bit[23:20] 4bit
[19:9] - reserved
DMA
[8] WC rdma_end 0
1
[7:1] - reserved
DMA
[0] WC wdma_end 0
1
PCI_ICMD
PCI_ICMD PCI Device Only

9-36 02 (2010-01-19)

Hi3520
9 PCI

0x088 PCI_ICMD 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
icmd_cpu_doorbell
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:20] - reserved
PCI Doorbell Interrupt PCI doorbell

PCI PCI Host
bit[19:16] bit
[19:16] RW icmd_pci_doorbell 4bit Hi3520 ARM CPU PCI Doorbell
Interrupt
PCI Doorbell Interrupt Hi3520 PCI Device

[15:0] - reserved
PCI_VERSION
PCI_VERSION PCI


0x04C CPU_VERSION -
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved device type device version
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
[31:16] - reserved
[15:12] RO device type
[11:0] RO device version

02 (2010-01-19) 9-37

Hi3520
10 USB 2.0 Host
10 USB 2.0 Host
10.1
USB 2.0 Host High-speed480Mbit/sFull-speed12Mbit/s Low-
speed1.5Mbit/sUSB 2.0 Host USB 2.0OHCI Rev
1.0a EHCI Rev 1.0 USB 2.0 Host Root HubUSB
Hub USB USB 2.0 Host

z
z
z USB
z
10.2
USB 2.0 Host

z USB 2.0
z OHCI Rev 1.0aEHCI Rev 1.0
z High-speedFull-speedLow-speed
z
z Control TransferBulk TransferIsochronous TransferInterrupt Transfer

z USB Hub 127
USB 10-1

02 (2010-01-19) 10-1

Hi3520
10 USB 2.0 Host
10-1 USB
USB2.0 EHCI Host Controller

CPU
AHB OHCI SOF DP0

Slave OR Gen DM0
AHB BUS Interface
AHB Root UTMI+

List Processor
Master Hub
AHB BUS
Serial Interface
Packet Buffer
PHY
DP1
Memory
USB1.1 OHCI Host DM1

Controller
USB2.0 Host Controller
UTMIUSB2.0 Transceiver Macrocell Interface

EHCIEnhanced Host Controller Interface
OHCIOpen Host Controller Interface
USB 2.0 Host 4

z Control Transfer
USB Host USB Device 0 USB

8byte16byte32byte 64byte
z Bulk Transfer

USB
Host USB Device
z Isochronous Transfer

z Interrupt Transfer

,

10-2 02 (2010-01-19)

Hi3520
10 USB 2.0 Host
10.3
10.3.1
USB PHY USB 2.0 Host 10-1
10-1 USB 2.0 Host
USBDP0 I/O USB 0 D+ USBDP0
USBDM0 I/O USB 0 D USBDM0
USBDP1 I/O USB 1 D+ USBDP1
USBDM1 I/O USB 1 D USBDM1
USBREXT I/O USBREXT

3.4K!1%
USBVDDA33T0_0 I/O 3.3V 3.3V!5% USBVDDA33T0_0
USBVSSA33T0_0 I/O USBVSSA33T0_0
USBVDDA33C I/O 3.3V 3.3V!5% USBVDDA33C
USBVSSA33C I/O USBVSSA33C
USBVDD0 I/O 1.0V 1.0V!5% USBVDD0
USBVSS0 I/O USBVSS0
USBVDD1 I/O 1.0V 1.0V!5% USBVDD1
USBVSS1 I/O USBVSS1

02 (2010-01-19) 10-3

Hi3520
10 USB 2.0 Host
10.3.2
PHY 10-2
PCB
z DP/DM 45
z ESD 1pF
z EN GPIO
10-2 USB 2.0 Host
IN 5V
OUT FLG
EN GPIO
DM
Standard USB 2.0
A Host
DP
REXT
3.4k
GND
GND
10.3.3
SC_PEREN[usb_clken] 1
SC_PERDIS[usb_clkdis] 1
10.3.4
USB 2.0 Host USB 2.0 Host
SC_PERCTRL8[usb_srst] 1 USB PHY
SC_PERCTRL8[usb_hrst] 1 USB
SC_PERCTRL12[usb_tune0]/ SC_PERCTRL12[usb_tune1]

10-4 02 (2010-01-19)

Hi3520
10 USB 2.0 Host
10.4
USB USB 2.0 Host EHCI OHCI

EHCI OHCI

USB 10-2
10-2 USB 0x100B_0000
0x90 INTNREG00 10-5
0x94 INTNREG01 FIFO OUT/IN 10-6
0x98 INTNREG02 FIFO 10-6
0x9C INTNREG03 Memory 10-7
0xA0 INTNREG04 DEBUG 10-7
0xA4 INTNREG05 10-8
0xA8 INTNREG06 AHB 10-9
0xAC INTNREG07 AHB 10-10
EHCI 0x100B_0000OHCI 0x100A_0000 10-2

EHCI
10.5
INTNREG00
INTNREG00

0x90 INTNREG00 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved val en
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:14] - reserved

02 (2010-01-19) 10-5

Hi3520
10 USB 2.0 Host

[13:1] RW val 125s

[0] RW en 0
1
INTNREG01
INTNREG01 FIFO OUT/IN

0x94 INTNREG01 0x0020_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name out_threshold in_threshold
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
FIFO
[31:16] RW out_threshold

FIFO
[15:0] RW in_threshold
FIFO
INTNREG02
INTNREG02 FIFO

0x98 INTNREG02 0x0000_0080
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved fifo_depth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
[31:12] - reserved
[11:0] RW fifo_depth FIFO 32bit

10-6 02 (2010-01-19)

Hi3520
10 USB 2.0 Host
INTNREG03
INTNREG03 Memory

0x9C INTNREG03 0x0000_0001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
brk_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:1] - reserved
Memory
[0] RO brk_en 0
1
INTNREG04
INTNREG04 DEBUG

0xA0 INTNREG04 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
scaledwn_enum_time
nak_reldfix_en
hccparam_en
hcsparam_en
reserved
auto_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] - reserved

0 run/stop hchalted
[5] RW auto_en
1 run/stop
0

02 (2010-01-19) 10-7

Hi3520
10 USB 2.0 Host
NAK
[4] RW nak_reldfix_en 0
1
[3] - reserved

scaledwn_enum_ti
[2] RW 0
me
1
HCCPARAMS
[1] RW hccparam_en 0
1
HCSPARAMS
[0] RW hcsparam_en 0
1
INTNREG05
INTNREG05 PHY
USB Host UTMI ULPI

UTMI

0xA4 INTNREG05 0x0000_1000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vcontrol_loadm
vbusy
Name reserved vport vcontrol vstatus
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
[31:18] - reserved
1
[17] RO vbusy

[16:13] RW vport

10-8 02 (2010-01-19)

Hi3520
10 USB 2.0 Host

[12] RW vcontrol_loadm 0
1
[11:8] RW vcontrol
[7:0] RO vstatus
ULPI

0xA4 INTNREG05 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
vendor control
reserved
Name vport access immidiate address extend address value
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1
[31] R/W vendor control

[30:28] - reserved
[27:24] RW vport

0001
[23:22] RW access
10
11
[21:16] RW immidiate address
[15:8] RW extend address

[7:0] RW value
vendor control

INTNREG06
INTNREG06 AHB

02 (2010-01-19) 10-9

Hi3520
10 USB 2.0 Host

0xA8 INTNREG06 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
err_capture
hbusrt_err
Name reserved num_beat_err num_beat_ok
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31] RW err_capture AHB
[30:12] - reserved
[11:9] RO hbusrt_err AHB hburst
AHB burst 16
[8:4] RO num_beat_err 0x000x10
0x110x1F
[3:0] RO num_beat_ok AHB burst
INTNREG07
INTNREG07 AHB

0xAC INTNREG07 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name err_addr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO err_addr AHB

10-10 02 (2010-01-19)

Hi3520
11
11
11.1 I2C
11.1.1
I2CThe Inter-Integrated Circuit I2C Master Slave Philips
I2C Master I2C Slave
Slave Master
A/DD/A I2C
11.1.2
I2C
z I2C
z Master Slave
z 7bit 10bit
z
z DMADirectory Memory Access
z
11.1.3
I2C 11-1
I2C SDA SCL OD I2C

02 (2010-01-19) 11-1

Hi3520
11
11-1 I2C
I2C_SDA I/O I2C GPIO SDA

11.1.5
I2C_SCL I/O I2C GPIO SDL

11.1.5
11.1.4
I2C 1-1
11-1 I2C
+VDD
Rp Rp (Pull-up resistors)
SDA
SCL
SDA SCL SDA SCL SDA SCL

I2 C I2 C I2C
Hi3520 SLAVE1 SLAVE2
I2C
I2C

I2C
11-2 11-3
11-2 I2C
Start Stop
SDA Slave Address + W(R) ACK MSB DATA LSB ACK
SCL 1 2 3 4 5 8 9 1 2 3 4 8 9

11-2 02 (2010-01-19)

Hi3520
11
11-3 I2C
-
Master-Transmitter protcol
For 7bit Slave Address
Slave ..
S R/W A DATA A . DATA A/NA P
Address
0(Write)
Slave Address Slave Address ..
S R/W A A DATA A . DATA A/ NA P
First 7bit Second Byte
11110 xx 0( Write)
Master-Receiver protcol
Slave ..
S R/W A DATA A . DATA NA P
Address
1'(Read)
Slave Address Slave Address .. ..

S R/W A A Sr Slave Address
. R/W A DATA A . DATA NA P
First 7bit Second Byte First 7bit
11110xx 0( Write) 1(Read)
From Master to Slave From Slave to Master
AAcknowledge(SDA low)
NANo Acknowledge(SDA high)
SStart Condition
Srrepeated Start Condition
PStop Condition
Start I2C Master Slave

Slave Address+W/R Master

7 10bit 10bit
1 / Slave
Slave 9
SCL SDASerial Data Master ACK

DATA Master
SDA SCL
SCL 1
ACK

02 (2010-01-19) 11-3

Hi3520
11
Stop Master
I2C Master
Slave
11.1.5
I2C SDA GPIO0_0 IO Config reg63 bit[0]

SDA
I2C SCL GPIO0_1 IO Config reg64 bit[0]

SCL
I2C Master I2C_SS_SCL_HCNTI2C_SS_SCL_LCNT

I2C_FS_SCL_HCNTI2C_FS_SCL_LCNT
I2C SCL I2C
* _ HCNT = Tscl _ h FI 2 C 8 * _ LCNT = Tscl _ l FI 2 C 1
z Tscl_h SCL cycle

z Tscl_l SCL s
z FI2C I2C MHz
z I2C Slave I2C_SS_SCL_HCNTI2C_SS_SCL_LCNTI2C_FS_SCL_HCNT
I2C_FS_SCL_LCNT
I2C_SS_SCL_HCNTI2C_SS_SCL_LCNTI2C_FS_SCL_HCNT
I2C_FS_SCL_LCNT 1-2 1-5
11-2 I2C_SS_SCL_HCNT
I2C I2C SCL I2C_SS_SCL_HCNT

kbit/s MHz s cycle
100 100 4 400
11-3 I2C_SS_SCL_LCNT
I2C I2C SCL I2C_SS_SCL_LCNT

kbit/s MHz s cycle
100 100 4.7 470

11-4 02 (2010-01-19)

Hi3520
11
11-4 I2C_FS_SCL_HCNT
I2C I2C SCL I2C_FS_SCL_HCNT

kbit/s MHz s cycle
400 100 0.6 60
11-5 I2C_FS_SCL_LCNT
I2C I2C SCL I2C_FS_SCL_LCNT

kbit/s MHz s cycle
400 100 1.3 130
SC_PERCTRL8[i2c_srst] I2C

Master
1 I2C_STATUS[activity] I2C 1
I2C_STATUS[activity] 0
I2C_ENABLE[enable] 0 I2C
2 I2C_CON
3 Slave I2C_TAR[i2c_tar]
4 I2C_SS_SCL_HCNTI2C_SS_SCL_LCNT I2C
5 I2C_RX_TLI2C_TX_TL TX_FIFO RX_FIFO
6 I2C_INTR_MASK

7 I2C_ENABLE[enable] 1 I2C
----
Slave
2 I2C_CON

02 (2010-01-19) 11-5

Hi3520
11
3 Slave I2C_SAR[i2c_sar]
4 I2C_RX_TLI2C_TX_TL TX_FIFO RX_FIFO
5 I2C_INTR_MASK

----
Master
1 I2C_DATA_CMD
2 I2C_STATUS I2C_TXFLR
TX_FIFO
TX_FIFO TX_FIFO
I2C
3 I2C_STATUS[tfe] 1 1 I2C
0 I2C 1
----
Slave
1 I2C Master I2C_SAR

I2C I2C_RAW_INTR_STAT[r_rd_req]
2 I2C_RAW_INTR_STAT[r_rd_req]
I2C_DATA_CMD
RD_REQ I2C_DATA_CMD
3 I2C_STATUS[tfe] 1 1 I2C 0
I2C 1
----
Master
1 0x0100 I2C_DATA_CMD
2 0x0100
I2C_DATA_CMD 3 3 I2C_DATA_CMD
TX_FIFO 0x100
TX_FIFO I2C
RX_FIFO
RX_FIFO
3 I2C_STATUS[activity] 0 0 I2C
1 I2C 0
----

11-6 02 (2010-01-19)

Hi3520
11
Slave
1 I2C Master I2C_SAR

2 I2C RX_FIFO RX_FIFO

RX_FIFO
3 I2C_RAW_INTR_STAT[r_rx_done] 1 1 I2C
0 I2C
1
----
DMA

2 I2C_CON
3 Master Slave I2C_TAR[i2c_tar]
4 I2C_SS_SCL_HCNTI2C_SS_SCL_LCNT I2C
5 I2C_DMA_TDLRI2C_DMA_RDLR DMA TX_FIFO RX_FIFO

----
1 DMA

2 I2C_DMA_CR 0x2 I2C DMA
3 DMA I2C DMA

----
I2C
RX_FIFO
4 DMA 0x100

5 I2C_DMA_CR 0x0003 I2C DMA

0x100 I2C_DATA_CMD DMA

02 (2010-01-19) 11-7

Hi3520
11
6 DMA I2C DMA

----
11.1.6
11-6 I2C 0x200D_0000
0x0000 I2C_CON I2C 11-9
0x0004 I2C_TAR I2C Slave 11-10
0x0008 I2C_SAR I2C Slave 11-11
0x0010 I2C_DATA_CMD I2C 11-12
0x0014 I2C_SS_SCL_HCNT SCL 11-12

0x0018 I2C_SS_SCL_LCNT SCL 11-13

0x001C I2C_FS_SCL_HCNT SCL 11-13

0x0020 I2C_FS_SCL_LCNT SCL 11-14

0x002C I2C_INTR_STAT 11-14
0x0030 I2C_INTR_MASK 11-16
0x0034 I2C_RAW_INTR_STAT 11-18
0x0038 I2C_RX_TL RX_FIFO 11-19
0x003C I2C_TX_TL TX_FIFO 11-20
0x0040 I2C_CLR_INTR 11-20
0x0044 I2C_CLR_RX_UNDER RX_UNDER 11-20
0x0048 I2C_CLR_RX_OVER RX_OVER 11-21
0x004C I2C_CLR_TX_OVER TX_OVER 11-21
0x0054 I2C_CLR_TX_ABRT ABRT 11-22
0x005C I2C_CLR_ACTIVITY ACTIVITY 11-22
0x0060 I2C_CLR_STOP_DET STOP_DET 11-23
0x0064 I2C_CLR_START_DET START_DET 11-23

11-8 02 (2010-01-19)

Hi3520
11
0x0068 I2C_CLR_GEN_CALL GEN_CALL 11-24
0x006C I2C_ENABLE I2C 11-24
0x0070 I2C_STATUS I2C 11-25
0x0074 I2C_TXFLR TX_FIFO 11-26
0x0078 I2C_RXFLR RX_FIFO 11-26
0x0080 I2C_TX_ABRT_SOUR TX_ABRT 11-27

CE
0x0088 I2C_DMA_CR I2C DMA 11-28
0x008C I2C_DMA_TDLR TX_FIFO DMA 11-29

0x0090 I2C_DMA_RDLR RX_FIFO DMA 11-29

11.1.7
I2C_CON
I2C_CON I2C
I2C_CON I2C I2C_ENABLE[enable] 0

0x0000 I2C_CON 0x0075
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i2c_10bitaddr_master
i2c_restart_en
master_mode
reserved
reserved
Name reserved speed
Reset 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1
[15:7] - reserved

02 (2010-01-19) 11-9

Hi3520
11
[6] RW reserved 1
Master
0
[5] RW i2c_restart_en

1
7bit /10bit
i2c_10bitaddr_ma
[4] RW 07bit
ster
110bit
[3] - reserved
I2C
00
01100kbit/s
[2:1] RW speed 10400kbit/s
11
00 11
10
Master
[0] RW master_mode 0
1
I2C_TAR
I2C_TAR I2C Slave
I2C_TAR I2C I2C_ENABLE[enable] 0

11-10 02 (2010-01-19)

Hi3520
11

0x0004 I2C_TAR 0x009C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
gc_or_start
special
Name reserved i2c_tar
Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0
[15:12] - reserved
general call start byte

[11] RW special 0
1
bit[11] 1 general call

start byte
[10] RW gc_or_start
0general call
1start byte
[9:0] RW i2c_tar I2C Master Slave
I2C_SAR
I2C_SAR I2C Slave
I2C_SAR I2C I2C_ENABLE[enable] 0

0x0008 I2C_SAR 0x0055
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved i2c_sar
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
[15:10] - reserved
[9:0] RW i2c_sar I2C Slave

02 (2010-01-19) 11-11

Hi3520
11
I2C_DATA_CMD
I2C_DATA_CMD I2C

0x0010 I2C_DATA_CMD 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cmd dat
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:9] - reserved
/
0 I2C I2C
8 DAT I2C
[8] RW cmd
I2C
1 I2C I2C

I2C /
[7:0] RW dat 8bit I2C

8bit I2C

I2C_SS_SCL_HCNT
I2C_SS_SCL_HCNT SCL
I2C_SS_SCL_HCNT I2C I2C_ENABLE[enable] 0

11-12 02 (2010-01-19)

Hi3520
11

0x0014 I2C_SS_SCL_HCNT 0x007A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name i2c_ss_scl_hcnt
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0
SCL
11.1.5
[15:0] RW i2c_ss_scl_hcnt
6 6
6
I2C_SS_SCL_LCNT
I2C_SS_SCL_LCNT SCL
I2C_SS_SCL_LCNT I2C I2C_ENABLE[enable] 0

0x0018 I2C_SS_SCL_LCNT 0x008F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name i2c_ss_scl_lcnt
Reset 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1
SCL
11.1.5
[15:0] RW i2c_ss_scl_lcnt
8 8
8
I2C_FS_SCL_HCNT
I2C_FS_SCL_HCNT SCL

02 (2010-01-19) 11-13

Hi3520
11
I2C_FS_SCL_HCNT I2C I2C_ENABLE[enable] 0

0x001C I2C_FS_SCL_HCNT 0x0013
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name i2c_fs_scl_hcnt
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
SCL
11.1.5
[15:0] RW i2c_fs_scl_hcnt
6 6
6
I2C_FS_SCL_LCNT
I2C_FS_SCL_LCNT SCL
I2C_FS_SCL_LCNT I2C I2C_ENABLE[enable] 0

0x0020 I2C_FS_SCL_LCNT 0x0028
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name i2c_fs_scl_lcnt
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
SCL
11.1.5
[15:0] RW i2c_fs_scl_lcnt
8 8
8
I2C_INTR_STAT
I2C_INTR_STAT

11-14 02 (2010-01-19)

Hi3520
11

0x002C I2C_INTR_STAT 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tx_empty
rx_under
gen_call
stop_det
rx_done
rx_over
tx_over
tart_det
activity
tx_abrt
rx_full
rd_req
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] - reserved
GEN_CALL general call

[11] RO gen_call 0
1
I2C RX Buffer
START_DET I2C

[10] RO start_det
0
1
STOP_DET I2C

[9] RO stop_det
0
1
ACTIVITY I2C Activity

[8] RO activity 0
1
RX_DONE I2C Slave

[7] RO rx_done
0
1
TX_ABRT
[6] RO tx_abrt
I2C_TX_ABRT_SOURCE
RD_REQ I2C Slave

Master
[5] RO rd_req
0
1

02 (2010-01-19) 11-15

Hi3520
11
TX_EMPTY TX_FIFO

[4] RO tx_empty
0
1
TX_OVER TX_FIFO
[3] RO tx_over 0
1
RX_FULL RX_FIFO

[2] RO rx_full
0
1
RX_OVER RX_FIFO
[1] RO rx_over 0
1
RX_UNDER FIFO
I2C_DATA_CMD

[0] RO rx_under
0
1RX_FIFO CPU
I2C_DATA_CMD
I2C_INTR_MASK
I2C_INTR_MASK

0x0030 I2C_INTR_MASK 0x08FF
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
m_tx_empty
m_rx_under
m_start_det
m_gen_call
m_stop_det
m_rx_done
m_rx_over
m_tx_over
m_activity
m_tx_abrt
m_rx_full
m_rd_req
Name reserved
Reset 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1
[15:12] - reserved

11-16 02 (2010-01-19)

Hi3520
11
GEN_CALL
[11] RW m_gen_call 0
1
START_DET
[10] RW m_start_det 0
1
STOP_DET
[9] RW m_stop_det 0
1
ACTIVITY
[8] RW m_activity 0
1
RX_DONE
[7] RW m_rx_done 0
1
TX_ABRT
[6] RW m_tx_abrt 0
1
RD_REQ
[5] RW m_rd_req 0
1
TX_EMPTY
[4] RW m_tx_empty 0
1
TX_OVER
[3] RW m_tx_over 0
1
RX_FULL
[2] RW m_rx_full 0
1
RX_OVER
[1] RW m_rx_over 0
1

02 (2010-01-19) 11-17

Hi3520
11
RX_UNDER
[0] RW m_rx_under 0
1
I2C_RAW_INTR_STAT
I2C_RAW_INTR_STAT

0x0034 I2C_RAW_INTR_STAT 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r_tx_empty
r_rx_under
r_start_det
r_gen_call
r_stop_det
r_rx_done
r_rx_over
r_tx_over
r_activity
r_tx_abrt
r_rx_full
r_rd_req
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] - reserved
GEN_CALL
[11] RO r_gen_call 0
1
START_DET
[10] RO r_start_det 0
1
STOP_DET
[9] RO r_stop_det 0
1
ACTIVITY
[8] RO r_activity 0
1
RX_DONE
[7] RO r_rx_done 0
1

[6] RO r_tx_abrt 0
1

11-18 02 (2010-01-19)

Hi3520
11
RD_REQ
[5] RO r_rd_req 0
1
R_TX_EMPTY
[4] RO r_tx_empty 0
1
TX_OVER
[3] RO r_tx_over 0
1
RX_FULL
[2] RO r_rx_full 0
1
RX_OVER
[1] RO r_rx_over 0
1
RX_UNDER
[0] RO r_rx_under 0
1
I2C_RX_TL
I2C_RX_TL RX_FIFO

0x0038 I2C_RX_TL 0x0003
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved rx_tl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
[15:8] - reserved
RX_FIFO
1
[7:0] RW rx_tl
FIFO 8
8

02 (2010-01-19) 11-19

Hi3520
11
I2C_TX_TL
I2C_TX_TL TX_FIFO

0x003C I2C_TX_TL 0x0003
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved tx_tl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
[15:8] RW reserved
TX_FIFO
[7:0] RW tx_tl FIFO 8
8
I2C_CLR_INTR
I2C_CLR_INTR

0x0040 I2C_CLR_INTR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_intr
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved

I2C_TX_ABRT_SOURCE
[0] RO clr_intr
I2C_TX_ABRT_SOURCE[abrt_sbyte_norstrt]

I2C_CLR_RX_UNDER
I2C_CLR_RX_UNDER RX_UNDER

11-20 02 (2010-01-19)

Hi3520
11

0x0044 I2C_CLR_RX_UNDER 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_rx_under
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_rx_under RX_UNDER
I2C_CLR_RX_OVER
I2C_CLR_RX_OVER RX_OVER

0x0048 I2C_CLR_RX_OVER 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_rx_over
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_rx_over RX_OVER
I2C_CLR_TX_OVER
I2C_CLR_TX_OVER TX_OVER

02 (2010-01-19) 11-21

Hi3520
11

0x004C I2C_CLR_TX_OVER 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_tx_over
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_tx_over TX_OVER
I2C_CLR_TX_ABRT
I2C_CLR_TX_ABRT ABRT

0x0054 I2C_CLR_TX_ABRT 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_tx_abrt
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
TX_ABRT
[0] RO clr_tx_abrt
I2C_TX_ABRT_SOURCE
I2C_CLR_ACTIVITY
I2C_CLR_ACTIVITY ACTIVITY

11-22 02 (2010-01-19)

Hi3520
11

0x005C I2C_CLR_ACTIVITY 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_activity
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
ACTIVITY
[0] RO clr_activity
0
I2C_CLR_STOP_DET
I2C_CLR_STOP_DET STOP_DET

0x0060 I2C_CLR_STOP_DET 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_stop_det
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_stop_det STOP_DET
I2C_CLR_START_DET
I2C_CLR_START_DET START_DET

02 (2010-01-19) 11-23

Hi3520
11

0x0064 I2C_CLR_START_DET 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_start_det
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_start_det START_DET
I2C_CLR_GEN_CALL
I2C_CLR_GEN_CALL GEN_CALL

0x0068 I2C_CLR_GEN_CALL 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
clr_gen_call
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
[0] RO clr_gen_call GEN_CALL
I2C_ENABLE
I2C_ENABLE I2C I2C
I2C I2C_STATUS[activity] 1I2C

z I2C I2C
TX_FIFO
z I2C I2C
NACK

11-24 02 (2010-01-19)

Hi3520
11

0x006C I2C_ENABLE 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
enable
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:1] - reserved
I2C
[0] RW enable 0
1
I2C_STATUS
I2C_STATUS I2C

0x0070 I2C_STATUS 0x0006
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
activity
Name reserved rff rfne tfe tfnf
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
[15:5] - reserved
RX_FIFO
[4] RO rff 0
1
RX_FIFO
[3] RO rfne 0
1
TX_FIFO
[2] RO tfe 0
1

02 (2010-01-19) 11-25

Hi3520
11
TX_FIFO
[1] RO tfnf 0
1
I2C
[0] RO activity 0
1
I2C_TXFLR
I2C_TXFLR TX_FIFO

0x0074 I2C_TXFLR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved txflr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] - reserved
[3:0] RO txflr TX_FIFO
I2C_RXFLR
I2C_RXFLR RX_FIFO

0x0078 I2C_RXFLR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved rxflr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] - reserved
[3:0] RO rxflr RX_FIFO

11-26 02 (2010-01-19)

Hi3520
11
I2C_TX_ABRT_SOURCE
I2C_TX_ABRT_SOURCE TX_ABRT

0x0080 I2C_TX_ABRT_SOURCE 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
abrt_10addr2_noack
abrt_10addr1_noack
abrt_7b_addr_noack
abrt_10b_rd_norstrt
abrt_txdata_noack
abrt_sbyte_norstrt
abrt_sbyte_ackdet
abrt_gcall_noack
abrt_gcall_read
arb_master_dis
abrt_hs_ackdet
abrt_hs_norstrt
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] - reserved
Master
Master
[11] RO arb_master_dis
0
1
restart Master
abrt_10b_rd_norst 10bit Slave
[10] RO
rt 0
1
restart Master
start byte
[9] RO abrt_sbyte_norstrt
0
1
restart Master

[8] RO abrt_hs_norstrt
0
1
Master start byte

[7] RO abrt_sbyte_ackdet
0
1

02 (2010-01-19) 11-27

Hi3520
11
Master

[6] RO abrt_hs_ackdet
0
1
Master general call

CPU I2C
[5] RO abrt_gcall_read
0
1
Master general call

[4] RO abrt_gcall_noack
0
1
Master
Slave
[3] RO abrt_txdata_noack
0
1
Master 10bit
abrt_10addr2_noa 2
[2] RO
ck 0
1
Master 10bit
abrt_10addr1_noa 1
[1] RO
ck 0
1
Master 7bit
abrt_7b_addr_noa
[0] RO
ck 0
1
I2C_DMA_CR
I2C_DMA_CR I2C DMA

11-28 02 (2010-01-19)

Hi3520
11

0x0088 I2C_DMA_CR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rdmae
Name reserved tdmae
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:2] - reserved
TX_FIFO DMA
[1] RW tdmae 0
1
RX_FIFO DMA
[0] RW rdmae 0
1
I2C_DMA_TDLR
I2C_DMA_TDLR TX_FIFO DMA

0x008C I2C_DMA_TDLR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved dmatdl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:3] - reserved
[2:0] RW dmatdl TX_FIFO DMA
I2C_DMA_RDLR
I2C_DMA_RDLR RX_FIFO DMA

02 (2010-01-19) 11-29

Hi3520
11

0x0090 I2C_DMA_RDLR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved dmardl
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:3] - reserved
[2:0] RW dmardl RX_FIFO DMA

1
11.2 UART
11.2.1
UARTUniversal Asynchronous Receiver Transmitter

UART
UART
Hi3520 4 UART
z UART0

z UART1
RS-485
z UART2UART3
MCUMicro Controller Unit
11.2.2
UART
z 16 8bit FIFO 16 12bit FIFO
z 5/6/7/8
1 2
z
z
z FIFO FIFO
z

11-30 02 (2010-01-19)

Hi3520
11
z UART UART /
z UART
z UART0UART1 UART2 DMA UART3
11.2.3
UART0 11-7
11-7 UART0
UART0_RXD I UART0 URXD0
UART0_TXD O UART0 UTXD0
UART1 11-8
11-8 UART1
UART1_RXD I UART1 URXD1
UART1_TXD O UART1 UTXD1
UART1_RTS O UART1 URTSN1
UART1_CTS I UART1 UCTSN1
UART2 11-9
11-9 UART2
UART2_RXD I UART2 VI GPIO VI0HS

11.2.5

UART2_TXD O UART2 VI GPIO VI0VS

11.2.5

UART3 11-9

02 (2010-01-19) 11-31

Hi3520
11
11-10 UART3
UART3_RXD I UART3 VI GPIO VI2HS

11.2.5

UART3_TXD O UART3 VI GPIO VI2VS

11.2.5

11.2.4
UART 11-4 11-5
11-4 UART
TXD1 TXD2
RXD1 RXD2
UART UART
GND
UART
UART0UART1UART2UART3
RTS UART_CR RTS

11-32 02 (2010-01-19)

Hi3520
11
11-5 UART
TXD1 TXD2
RXD1 RXD2
UART UART
RTS1 RTS2
CTS1 CTS2
RTS CTS RTS CTS

UART1 RS-485 RTS CTS

RTS 11-6
11-6 RTS
rts_mode
RTS1
UART 1
RTS UART_CR RTS

SC_PERCTRL11[uart1_rtsmode] RTS
UART 11-7
UART TXD UART RXD

02 (2010-01-19) 11-33

Hi3520
11
11-7 UART
Idle Start Data Data Data Data Data Data Data Data Parity Stop Stop Idle
State Bit <0> <1> <2> <3> <4> <5> <6> <7> Bit Bit1 Bit2 State
TXD or RXD

z start bit
UART TXD
UART
z data bit
5/6/7/8
z parity bit
1 UART
UART_LCR_H
z stop bit
1 2
TXD
11.2.5
UART2 VI GPIO UART2

reg0reg1
UART3 VI GPIO UART3

reg18reg19
UART
UART_FR bit[3] 0 UART
1 UART_FR
2 UART_FR bit[3] 0 UART_CR[uarten]=0 3 UART_FR bit[3]

1 1
3 SC_PERDIS[7:4]=0xF UART
----

11-34 02 (2010-01-19)

Hi3520
11
UART_IBRD UART_FBRD UART

=UART /16%
UART_IBRD UART_FBRD
60MHz UART_IBRD 0x1EUART_FBRD

0x00 60/(16%30)=0.125Mbit/s
UART 9,600bit/s14,400bit/s19,200bit/s38,400bit/s
57,600bit/s76,800bit/s115,200bit/s230,400bit/s460,800bit/s
230400bit/s UARTCLK 100MHz

(100%106)/(16%230400)=27.1267 IBRD 27FBRD
0.1267
6bit UART_FBRD m=integer(FBRD%2n+0.5)

n=UART_FBRD m=integer(0.1267%26+0.5)=8
UART_IBRD 0x001BUART_FBRD 0x08
8 27+8/64=27.125
100%106/16%27.125=230414.75230414.75230400
/230400%100=0.006%
6bit UART_FBRD 1/64%100=1.56% m=1

64
UART
z SC_PERCTRL8 bit[6] 1 UART0




1 UART_CR bit[0] 0 UART
2 UART_IBRDUART_FBRD

02 (2010-01-19) 11-35

Hi3520
11
3 UART_CRUART_LCR_H UART
4 UART_IFLS FIFO
5 UART_IMSC

----
7 UART_DR
8 UART_FR bit[5] TX_FIFO

TX_FIFO TX_FIFO
TX_FIFO
9 UART_FR bit[7] 1 UART
----

z UART_FR bit[4] RX_FIFO
RX_FIFO RX_FIFO
z RX_FIFO
DMA
UART0UART1 UART2 DMA UART3 DMA
2 UART_IBRDUART_FBRD
3 UART_CRUART_LCR_H UART
4 UART_IFLS FIFO
5 UART_IMSC

----

11-36 02 (2010-01-19)

Hi3520
11
1 DMA
3.5
2 UART_DMACR 0x2 UART DMA
3 DMA UART DMA

----
1 DMA

2 UART_DMACR 0x1 UART DMA
3 DMA UART DMA

----
11.2.6
Hi3520 4 UART UART0UART1UART2 UART3

z UART0 0x2009_0000
z UART1 0x200A_0000
z UART2 0x200B_0000
z UART3 0x200C_0000
UART 11-11
11-11 UART
0x000 UART_DR 11-38
0x004 UART_RSR / 11-39
0x018 UART_FR 11-40
0x01C0x020 RESERVED -
0x024 UART_IBRD 11-41
0x028 UART_FBRD 11-41

02 (2010-01-19) 11-37

Hi3520
11
0x02C UART_LCR_H 11-42
0x030 UART_CR 11-44
0x034 UART_IFLS FIFO 11-45
0x038 UART_IMSC 11-46
0x03C UART_RIS 11-47
0x040 UART_MIS 11-48
0x044 UART_ICR 11-49
0x048 UART_DMACR DMA 11-50
11.2.7
UART_DR
UART_DR UART


0x000 UART_DR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oe be pe fe data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] - reserved

0
[11] RO oe
1 FIFO

Break
0 break
[10] RO be 1 break
startdata
paritystop bit
[9] RO pe

11-38 02 (2010-01-19)

Hi3520
11
0
1

[8] RO fe 0
1
[7:0] RW data
UART_RSR
UART_RSR /
z
z
UART_DR UART_DR breakframeparity

UART_RSR UART_DR
UART_RSR
UART_RSR UART_RSR

0x004 UART_RSR 0x00
Bit 7 6 5 4 3 2 1 0
Name reserved oe be pe fe
Reset 0 0 0 0 0 0 0 0
[7:4] - reserved

0
1
[3] RW oe
FIFO FIFO
FIFO
CPU
FIFO

02 (2010-01-19) 11-39

Hi3520
11
Break
0 break
[2] RW be 1break
Break
startdata
paritystop bit

0
[1] RW pe 1
FIFO FIFO

0
[0] RW fe
1
1
UART_FR
UART_FR UART

0x018 UART_FR 0x0012
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved txfe rxff txff rxfe busy reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
[15:8] - reserved
UART_LCR_H[fen]
UART_LCR_H[fen] 0 holding
[7] RO txfe register 1
UART_LCR_H[fen] 1 FIFO
1
UART_LCR_H[FEN]
[6] RO rxff register 1
1

11-40 02 (2010-01-19)

Hi3520
11
UART_LCR_H[FEN]
[5] RO txff register 1
1
UART_LCR_H[FEN]
[4] RO rxfe register bit 1
1
UART
0UART
1UART
[3] RO busy

FIFO UART

[2:0] - reserved
UART_IBRD
UART_IBRD

0x024 UART_IBRD 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name baud divint
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:0] RW baud divint 0
UART_FBRD
UART_FBRD

02 (2010-01-19) 11-41

Hi3520
11
z

z 1 655352161 UART_IBRD=0
UART_FBRD UART_IBRD=655350xFFFF
UART_FBRD 0 0
z UART_FBRD=0x1EUART_IBRD=0x01
30 0.015625 30.015625
z UART =/(16%)=/(16%30.015625)

0x028 UART_FBRD 0x00
Bit 7 6 5 4 3 2 1 0
Name reserved baud divfrac
Reset 0 0 0 0 0 0 0 0
[7:6] - reserved
[5:0] RW band divfrac 0
UART_LCR_H
UART_LCR_H UART_LCR_HUART_IBRDUART_FBRD
30bit UART_IBRD UART_FBRD
UART_LCR_H

0x02C UART_LCR_H 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved sps wlen fen stp2 eps pen brk
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:8] - reserved

11-42 02 (2010-01-19)

Hi3520
11

bit[1]bit[2]bit[7]
0
[7] RW sps bit[1]bit[7]bit[2] 0
1
bit[1]bit[2]bit[7] 0 stick parity

005bit
[6:5] RW wlen 016bit
107bit
118bit
FIFO
[4] RW fen 0 FIFO
1 FIFO
2bit
0 2bit
[3] RW stp2
1 2bit
2bit

0

[2] RW eps
1

UART_LCR_H[fen] 0

[1] RW pen 0
1
break
0
1UTXD
[0] RW brk
break 1
2
0

02 (2010-01-19) 11-43

Hi3520
11
UART_CR
UART_CR UART
UART_CR
1 UART_CR[0] 0 UART
3 UART_LCR_H[fen] 0
4 UART_CR
5 UART_CR[0] 1 UART
----

0x030 UART_CR 0x0300
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
uarten
Name ctsen rtsen reserved rts dtr rxe txe lbe reserved
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
CTS
0 CTS
[15] RW ctsen
1 CTS nUARTCTS

RTS
0 RTS
[14] RW rtsen
1 RTS FIFO

[13:12] - reserved

bit UART modem
[11] RW rts nUARTRTS
0
1 bit 1 0

11-44 02 (2010-01-19)

Hi3520
11

bit UART modem
[10] RW dtr nUARTDTR
0
1 bit 1 0
UART
0
[9] RW rxe 1
UART

UART
0
[8] RW txe 1
UART

[7] RW lbe 0
1UARTTXD UARTRXD
[6:1] - reserved
UART
0
[0] RW uarten 1
UART

UART_IFLS
UART_IFLS FIFO FIFO UART_TXINTR
UART_RXINTR

02 (2010-01-19) 11-45

Hi3520
11

0x034 UART_IFLS 0x0012
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved rxiflsel txiflsel
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
[15:6] - reserved
FIFO

000 FIFO1/8full
001 FIFO1/4full
[5:3] RW rxiflsel
010 FIFO1/2full
011 FIFO3/4full
100 FIFO7/8full
101111
FIFO

000 FIFO1/8full
001 FIFO1/4full
[2:0] RW txiflsel
011 FIFO3/4full
010 FIFO1/2full
100 FIFO7/8full
101111
UART_IMSC
UART_IMSC

0x038 UART_IMSC 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oeim beim peim feim rtim txim rxim reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:11] - reserved

11-46 02 (2010-01-19)

Hi3520
11

[10] RW oeim 0
1
break
[9] RW beim 0
1

[8] RW peim 0
1

[7] RW feim 0
1

[6] RW rtim 0
1

[5] RW txim 0
1

[4] RW rxim 0
1
[3:0] - reserved
UART_RIS
UART_RIS

0x03C UART_RIS 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oeris beris peris feris rtris txris rxris reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:11] - reserved

02 (2010-01-19) 11-47

Hi3520
11

[10] RO oeris 0
1
break
[9] RO beris 0
1

[8] RO peris 0
1

[7] RO feris 0
1

[6] RO rtris 0
1

[5] RO txris 0
1

[4] RO rxris 0
1
[3:0] - reserved
UART_MIS
UART_MIS


0x040 UART_MIS 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oemis bemis pemis femis rtmis txmis rxmis reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:11] - reserved

11-48 02 (2010-01-19)

Hi3520
11

[10] RO oemis 0
1
break
[9] RO bemis 0
1

[8] RO pemis 0
1

[7] RO femis 0
1

[6] RO rtmis 0
1

[5] RO txmis 0
1

[4] RO rxmis 0
1
[3:0] - reserved
UART_ICR
UART_ICR 1 0

0x044 UART_ICR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved oeic beic peic feic rtic txic rxic reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:11] - reserved

02 (2010-01-19) 11-49

Hi3520
11

[10] WO oeic 0
1
break
[9] WO beic 0
1

[8] WO peic 0
1

[7] WO feic 0
1

[6] WO rtic 0
1

[5] WO txic 0
1

[4] WO rxic 0
1
[3:0] - reserved
UART_DMACR
UART_DMACR DMA FIFO FIFO DMA

11-50 02 (2010-01-19)

Hi3520
11

0x048 UART_DMACR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dmaonerr
rxdmae
txdmae
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:3] - reserved
UART UARTEINTR
DMA
0 UART UARTEINTR
DMA UARTRXDMASREQ
[2] RW dmaonerr
UARRTXDMABREQ
1 UART UARTEINTR
DMA UARTRXDMASREQ
UARRTXDMABREQ
FIFO DMA
[1] RW txdmae 0
1
FIFO DMA
[0] RW rxdmae 0
1
11.3 SPI
11.3.1
SPISynchronous Peripheral Interface master slave

z A Motorola SPISynchronous Peripheral Interface-compatible interface
z A Texas Instruments synchronous serial interface
z A National Semiconductor Microwire interface
SPI SD WiFi

02 (2010-01-19) 11-51

Hi3520
11
11.3.2
SPI
z 2 slave
z
z
z / 16bit 8 FIFO FIFO FIFO
z SPIMicrowireTI synchronous serial
z 4bit16bit
z
z DMA
11.3.3
SPI 11-12
11-12 SPI
SPICK I/O SPI VO VO1DAT8

SPIDI I SPI VO VO1DAT9

SPIDO O SPI VO VO1DAT10

SPICSN0 I/O SPI SPI Microwire VO1DAT11

/SPICSN1 SPI TI /VO1DAT12

11.3.4
SPI slave 11-8 SPI slave SPI

SPICSN0

11-52 02 (2010-01-19)

Hi3520
11
11-8 SPI slave
master slave
SPICK XXX_CLK
SPICSN XXX_CS
SPIDI XXX_DOUT
SPIDO XXX_DIN
Hi3520
SPI slave 11-9 SPI 2 slave SPI

SC_PERCTRL11[spi_port]
SPICSN0 SPICSN1
SC_PERCTRL11[spi_port]] 0 SPICS0N SC_PERCTRL11[spi_port]
1 SPICS1N
11-9 SPI slave
MASTER SLAVE_0
SPICK XXX_DCLK
SPICSN XXX_CS
MUX
SPIDI XXX_DOUT
SPIDO XXX_DIN
SLAVE_1
XXX_DCLK
XXX_CS
XXX_DOUT
Hi3520 XXX_DIN
SPI slave 11-10 Master SPICSN0

SPICSN1
SC_PERCTRL11[spi_port] Master SPI
SPI SPICSN0

02 (2010-01-19) 11-53

Hi3520
11
11-10 SPI slave
slave master
SPICK XXX_DCLK
SPICSN XXX_CS
SPIDI XXX_DOUT
SPIDO XXX_DIN
SPICSN0/SPICSN1
Hi3520
spo SPICLKOUT sph SPICLKOUT

11-11 11-22
z MSBMost Significant Bit
z LSBLeast Significant Bit
z QAn undefined signal
spo=0sph=0 Motorola SPI 11-11
11-11 Motorola SPI spo=0sph=0
SPICK
SPICSN
4 to 16bits
SPIDI/SPIDO MSB LSB Q

11-54 02 (2010-01-19)

Hi3520
11
SPI_CK
SPI_CSN
4 to 16bits
SPI_DI/
SPI_DO LSB MSB LSB Q MSB
SPI
z SPICK
z SPICSN
z SPIDO
SPI FIFO SPICSN

slave master SPIDI
SPICK master SPIDO master slave
SPICK SPICK
SPICK
word 1 bitSPICSN 1 SPICK

SPICSN 2 word SPICK

sph 0 salve
2 word SPICSN
SPICSN 1 bit 1 SPICK

SPICK
SPICSN
4 to 16bits
SPIDI/SPIDO
MSB LSB Q

02 (2010-01-19) 11-55

Hi3520
11
SPICK
SPICSN
4 to 16bits 4 to 16bits
SPIDI/SPIDO MSB LSB MSB LSB Q
SPI
z SPICK
z SPICSN
z SPIDO
SPI FIFO SPICSN

SPICK master slave
SPICK SPICK


word SPICSN SPICSN

1 bit 1 SPICK
SPICK
SPICSN
4 to 16bits
SPIDI/SPIDO MSB LSB Q
SPI_CK
SPI_CSN
SPI_DI/ 4 to 16bits
SPI_DO LSB MSB LSB Q MSB

11-56 02 (2010-01-19)

Hi3520
11
SPI
z SPICK
z SPICSN
z SPIDO
SPI FIFO SPICSN

slave master SPIDI
SPICK master SPIDO SPI_CK
SPICK master pin SPICK
SPICK

SPICSN 2 word sph

0 salve SPICSN
1 bit 1 SPICK
SPICK
SPICSN
SPIDI/ 4 to 16bits
SPIDO MSB LSB Q
SPICK
SPICSN
4 to 16bits 4 to 16bits
SPIDI/
SPIDO MSB LSB MSB LSB Q
SPI
z SPICK
z SPICSN
z SPIDO

02 (2010-01-19) 11-57

Hi3520
11
SPI FIFO SPICSN master

SPICK master slave
SPICK SPICK

word SPICSN 1 bit SPICK

SPICSN SPICSN
bit SPICK
SPICSN

TI 11-19
11-19 TI
SPICK
SPICSN
4 to 16bits
SPIDI/
SPIDO MSB LSB
TI 11-20
11-20 TI
SPICK
SPICSN
4 to 16bits
SPIDI/
SPIDO LSB MSB LSB MSB
SPI
z SPICK
z SPICSN
z SPIDO
FIFO SPICSN SPICK

FIFO SPICK
4bit16bit MSB SPIDO slave
MSB SPIDI
SPI SPICK
LSB SPICK FIFO

11-58 02 (2010-01-19)

Hi3520
11
National Semiconductor Microwire 11-21
11-21 National Semiconductor Microwire
SPICK
SPICSN
4 to 16 bits
SPIDI 0 MSB LSB Q
8 bit control
SPIDO MSB LSB
National Semiconductor Microwire 11-22
11-22 National Semiconductor Microwire
SPICK
SPICSN
4 to 16 bits 4 to 16 bits
SPIDI 0 MSB LSB MSB LSB
8 bit control
SPIDO LSB MSB LSB
Microwire SPI master-slave

SPI Microwire SPI
8bit SPI
8bit slave
4bit16bit 13bit
25bit
SPI
z SPICK
z SPICSN
z SPIDO
FIFO SPICSN
FIFO 8bit MSB
SPIDOSPICSN SPIDI

SPICK
1 bit 1
SPI 1 bit SPICK
SPIDI SPICSN 1

02 (2010-01-19) 11-59

Hi3520
11
bit 1
FIFO

SPICSN
LSB LSB SPI
SPICK
11.3.5
SPI VO SPI SPI

IO Congfig reg54reg58
SPI
SPI_SR[bsy] 0

1 SPI_SR
2 SPI_SR[bsy] 0 SPI_CR1[sse]=0 3 SPI_SR[bsy] 1

1
3 SC_PERDIS[spi_clkdis] SPI
----
z SPI
SPI (min)2%FSPICK(max)
SPI 2 SPI
z SPI
SPI (max)254%256%FSPICK(min)
SPI 254%256 SPI
z SPICK
FSPICK=SPI /(CPSDVSR%(1 + SCR))
CPSDVSR SCR SPI

SPI_CR0SPI_CPSR
11-13 SPI

11-60 02 (2010-01-19)

Hi3520
11
11-13
SPI (MHz) CPSDVSR SCR SPICK(MHz)
100 2 1 25
100 2 4 10
24 2 1 6
24 2 4 2.4
SPI
SC_PERCTRL10[spi_srst] 1 SPI

1 SPI_CR1[sse] 0 SPI
2 SPI_CR0
3 SPI_CPSR
4 SPI_INTMASK

----
1 SPI_CPSR cpsdvsr
2 SPI_CR0SPITIMW dss
3 SPI_CR1[see] 1 SPI
4 SPI_SR FIFO SPI_SR[tnf] 1 FIFO

SPI_DR 4
5 SPI_SR FIFO
----

02 (2010-01-19) 11-61

Hi3520
11
1 SPI_CPSR[cpsdvsr]
2 SPI_CR0 SPITIMW
4 SPI_SR FIFO FIFO SPI_DR

half word 4
5 SPI_SR
----
DMA

2 SPI_CR0
3 SPI_CPSR
4 SPI_INTMASK
5 SPI_DMACR SPI DMA
----
1 DMAC
2 DMAC
3 DMAC SPI FIFO DMA
5 DMAC DMAC 2
burst burst SPI DMA burst
single DMAC burst
burst SPI single
6 DMA SPI DMA

----
1 DMAC

11-62 02 (2010-01-19)

Hi3520
11
2 DMAC
3 DMAC SPI FIFO DMA
5 DMAC DMAC 2
burst burst SPI DMA
burst single DMAC burst
burst SPI single
6 DMA SPI DMA

----
11.3.6
SPI 11-14
11-14 SPI 0x200E_0000
0x000 SPI_CR0 0 11-63
0x004 SPI_CR1 1 11-65
0x008 SPI_DR FIFO FIFO 11-66
0x00C SPI_SR 11-66
0x010 SPI_CPSR 11-67
0x014 SPI_INTMASK 11-68
0x018 SPI_RINTSTATUS 11-69
0x01C SPI_MINTSTATUS 11-70
0x020 SPI_INTCLR 11-70
0x024 SPI_DMACR DMA 11-71
11.3.7
SPI_CR0
SPI_CR0 0 SPI

02 (2010-01-19) 11-63

Hi3520
11

0x000 SPI_CR0 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name scr sph spo frf dss
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCRSystem Clock
Reference SPI

FSSPCLK
[15:8] RW scr
CPSDVSR (1+ SCR )
SPICPSR[CPSDVSR] 2254
SCR 0255

SPICK Motorola SPI

[7] RW sph
0 1
1 2
SPICK Motorola SPI

[6] RW spo 0 SPICK
1 SPICK

11-64 02 (2010-01-19)

Hi3520
11

00Motorola SPI
[5:4] RW frf 01TI
10National Microwire
11

00000010
00114bit
01005bit
01016bit
01107bit
01118bit
[3:0] RW dss 10009bit
100110bit
101011bit
101112bit
110013bit
110114bit
111015bit
111116bit
SPI_CR1
SPI_CR1 1 SPI

0x004 SPI_CR1 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved sod ms sse lbm
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] - reserved
slave bit slave

(ms=1) slave
[3] RW sod SPI master
slave slave
slave

02 (2010-01-19) 11-65

Hi3520
11
SPI_SPIDI
slave SPI_SPIDO
sod bit
0SPI slave SPITXD

1SPI slave SPITXD

Master slave
SPI
[2] RW ms
0 master
1 slave

[1] RW sse 0
1

0
[0] RW lbm
1

SPI_DR
SPI_DR SPI FIFO
SPI FIFO Microwire FIFO
8bit SPI_CR1[sse] 0 FIFO
0 SPI FIFO

0x008 SPI_DR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name data
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:0] RW data FIFO FIFO
SPI_SR
SPI_SR FIFO

11-66 02 (2010-01-19)

Hi3520
11

0x00C SPI_SR 0x0003
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved bsy rff rne tnf tfe
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
[15:5] - reserved
SPI
[4] RO bsy 0
1
FIFO
[3] RO rff 0
1
FIFO
[2] RO rne 0
1
FIFO
[1] RO tnf 0
1
FIFO
[0] RO tfe 0
1
SPI_CPSR
SPI_CPSR SPI
SPICK 2254 1bit
1bit

02 (2010-01-19) 11-67

Hi3520
11

0x010 SPI_CPSR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cpsdvsr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:8] - reserved
2254
SPI_CR0[scr]
[7:0] RW cpsdvsr
SPICLK CPSDVSR
0
SPI_INTMASK
SPI_INTMASK

0x014 SPI_ INTMASK 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rorim
rxim
txim
rtim
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] - reserved
FIFO
[3] RW txim 0
1
FIFO
[2] RW rxim 0
1
FIFO
FIFO
[1] RW rtim
0
1

11-68 02 (2010-01-19)

Hi3520
11
FIFO

[0] RW rorim
0
1
SPI_RINTSTATUS
SPI_RINTSTATUS


0x018 SPI_RINTSTATUS 0x0008
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rorris
rxris
txris
ptris
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
[15:4] - reserved
SPITXINTR

[3] RO txris
0
1
SPIRXINTR

[2] RO rxris
0
1
SPIRTXINTR

[1] RO rtris
0
1
SPIRORXINTR

[0] RO rorris
0
1

02 (2010-01-19) 11-69

Hi3520
11
SPI_MINTSTATUS
SPI_MINTSTATUS

0x01C SPI_MINTSTATUS 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rormis
rxmis
txmis
rtmis
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:4] - reserved
FIFO
SPITXINTR
[3] RO txmis
0
1
FIFO
SPIRXINTR
[2] RO rxmis
0
1

SPIRTINTR
[1] RO rtmis
0
1

SPIRORINTR
[0] RO rormis
0
1
SPI_INTCLR
SPI_INTCLR 1 0

11-70 02 (2010-01-19)

Hi3520
11

0x020 SPI_INTCLR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
roric
Name reserved rtic
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:2] - reserved
SPIRTINTR
[1] WO rtic 0
1
SPIRORINTR
[0] WO roric 0
1
SPI_DMACR
SPI_DMACR DMA SPI DMA

0x024 SPI_DMACR 0x0000
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rxdmae
txdmae
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:2] - reserved
FIFO DMA
[1] RW txdmae 0
1
FIFO DMA
[0] RW rxdmae 0
1

02 (2010-01-19) 11-71

Hi3520
11
11.4 IR
11.4.1
IRInfrared Remoter NEC
with simple repeat codeNEC with full repeat codeSONY TC9012

11.4.2
IR
z
z

z
z
z
z 1MHz128MHz
1MHz
11.4.3
IR 11-15
11-15 IR
IR_RCV I a IRRCV
aIRRCV
11.4.4
IR ARM
ARM IR
ARM APB CPU
IR INT INT
CRG ARM
IR 11-23

11-72 02 (2010-01-19)

Hi3520
11
11-23 IR
CRG SC INT
interrupt
signal
ARM AHB2APB IR
GPIO
AHB APB

0 1
NEC with simple repeat code NEC with
full repeat code TC9012 SONY
11-16 11-18
11-16 NEC with simple repeat code
NEC with simple repeat code
uPD6121G D6121/BU5777/D1913 LC7461M-C13 AEHA
10s LEAD_S 900 900 900 337.6

LEAD_E 450 450 450 168.8
bit010s B0_L 56 56 56 42.2

B0_H 56 56 56 42.2
bit110s B1_L 56 56 56 42.2

B1_H 169 169 169 126.6
simple repeat code SLEAD_S 900 900 900 337.6
10s SLEAD_E 225 225 225 337.6
burst10s 55 55 55 42.2
10s 10800 10800 10800 8777.6

12828.8
32 32 42 48

02 (2010-01-19) 11-73

Hi3520
11
11-17 NEC with full repeat code
NEC with full repeat code
uPD6121G LC7461 MN602 MN6014 MATNEW MN6030 PANA

M-C13 4-C5D6 -C6D6 SONIC
LEAD_S 900 900 337.6 349.2 348.8 349 352

10s LEAD_E 450 450 337.6 349.2 374.4 349 352
bit0 B0_L 56 56 84.4 87.3 43.6 87.3 88
10s B0_H 56 56 84.4 87.3 43.6 87.3 88
bit1 B1_L 56 56 84.4 87.3 43.6 87.3 88
10s B1_H 169 169 253.2 174.6 130.8 261.9 264
simple SLEAD_S
repeat
code
SLEAD_E
10s
burst10s 55 55 84.4 87.3 43.6 87.3 88
10s 12413.6
10800 10800 10130 10470 10500 10400
16594.4
32 42 22 24 48 22 22
11-18 TC9012 SONY
TC9012 SONY
TC9012F/9243 SONY-D7C5 SONY-D7C6 SONY-D7C8 SONY-D7C13
LEAD_S 450 240 240 240 240

10s LEAD_E 450 60 60 60 60
bit0 B0_L 56 60 60 60 60
10s B0_H 56 60 60 60 60
bit1 B1_L 56 120 120 120 120
10s B1_H 169 60 60 60 60
simple SLEAD_S
repeat
code SLEAD_
E
10s
burst10s 56

11-74 02 (2010-01-19)

Hi3520
11
TC9012 SONY
TC9012F/9243 SONY-D7C5 SONY-D7C6 SONY-D7C8 SONY-D7C13
10s 10800 4500 4500 4500 4500
32 12 13 15 20
11.4.4.2 NEC with simple repeat code
NEC with simple repeat code START burst

START
LSB first
burst
NEC with simple repeat code 11-24
LSB MSB
START
burst

burst
NEC with simple repeat code 11-25

NEC with simple repeat code bit0 bit1 11-26

02 (2010-01-19) 11-75

Hi3520
11
11-26 NEC with simple repeat code bit0 bit1
bit0 bit1
b0_L b0_H b1_L b1_H
NEC simple repeat code 11-27 11-28
LEAD_S LEAD_E
burst
SLEAD_S SLEAD_E burst
1 11-16 11-18
2 160ms
11.4.4.3 NEC with full repeat code
NEC with full repeat code START burst

START
LSB first burst
NEC with full repeat code 11-29

LSB MSB
START
burst

11-76 02 (2010-01-19)

Hi3520
11

11-28 11-30 NEC with simple repeat code NEC with full repeat
code NEC with simple repeat code
NEC with full repeat code
NEC with full repeat code bit0 bit1 11-31
11-31 NEC with full repeat code bit0 bit1
bit0 bit1
b0_L b0_H b1_L b1_H
LEAD_S LEAD_E
burst
11-16 11-18
11.4.4.4 TC9012

02 (2010-01-19) 11-77

Hi3520
11
TC9012 1 0

TC9012 START burst START

LSB first burst
TC9012 11-33
11-33 TC9012
LSB MSB
START
C0
burst

burst
C0
TC9012 11-34
11-34 TC9012
TC9012 bit0 bit1 11-35
11-35 TC9012 bit0 bit1
bit0 bit1
b0_L b0_H b1_L b1_H
TC9012 11-36

11-78 02 (2010-01-19)

Hi3520
11
11-36 TC9012
LEAD_S LEAD_E
burst
C0=1 TC9012 11-37
11-37 TC9012 C01
LEAD_S LEAD_E
C01
bit0 burst
C0=0 TC9012 11-38
11-38 TC9012 C00
LEAD_S LEAD_E
C00
bit1 burst
11-16 11-18
160ms
11.4.4.5 SONY
SONY START START

LSB first SONY
11-39
11-39 SONY
START

02 (2010-01-19) 11-79

Hi3520
11

SONY 11-40
11-40 SONY
SONY bit0 bit1 11-41
11-41 bit0 bit1
bit0 bit1
b0_L b0_H b1_L b1_H
11-16 11-18
11.4.5
IR EBI IR IO Config IR
reg74
SC_PEREN bit[11] 1 IR pclk

SC_PERDIS bit[11] 1 IR pclk
SC_PERCTRL8 bit[10] 1 IR

IR 11-42

11-80 02 (2010-01-19)

Hi3520
11
11-42 IR
IR
2 IR IR
3 IR_EN[0] 1 IR
4 IR_BUSY IR
z 1 IR IR_BUSY
IR
z 0 IR 5
5 IR_CFGIR_LEADSIR_LEADEIR_SLEADEIR_B0IR_B1
IR_INT_MASK

6 IR_START IR
IR_STARTIR

----

02 (2010-01-19) 11-81

Hi3520
11
11-43
,IR
IR_DATAH
IR_DATAL
1 IR
2
z CPU IR
IR_INT_STATUS[intms_rcv] 1 IR
3 0 2
z IR_INT_STATUS[intrs_rcv]
1 IR 3
0 IR 2
3 IR_DATAH 32

4 IR_DATAL
----
11.4.6 IR
IR 11-19

11-82 02 (2010-01-19)

Hi3520
11
11-19 IR 0x2007_0000
0x000 IR_EN IR 11-83
0x004 IR_CFG IR 11-84
0x008 IR_LEADS 11-85
0x00C IR_LEADE 11-86
0x010 IR_SLEADE 11-87
0x014 IR_B0 0 11-88
0x018 IR_B1 1 11-89
0x01C IR_BUSY 11-90
0x020 IR_DATAH IR 16 11-91
0x024 IR_DATAL IR 32 11-91
0x028 IR_INT_MASK IR 11-91
0x02C IR_INT_STATUS IR 11-93
0x030 IR_INT_CLR IR 11-94
0x034 IR_START IR 11-95
11.4.7 IR
IR_EN
IR_EN IR
IR_EN[0]=0b1
IR_EN[0]=0b0

02 (2010-01-19) 11-83

Hi3520
11

0x000 IR_EN 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ir_en
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
IR
[0] RW ir_en 0 IR
1 IR
IR_CFG
IR_CFG IR
IR_BUSY[0]=0b0 IR_EN[0]=0b1

IR 1MHz128MHz ir_freq
z 1MHz ir_freq 0x00
z 128MHz ir_freq 0x7F
IR 1MHz128MHz
12.1MHz 0x0B
12.8MHz 0x0C
f Df ratio=Df/f
Dcnt ss Dcnt = 0.1 s ratio

[min+Dcnt, max+Dcnt] min max
[min-Dcnt, max-Dcnt]
100MHz 0.1MHz ratio=0.1/100=0.001 s=9000s
Dcnt = 0.1 9000 0.001 = 1 ir_leads [0x033D0x3CD]

11-84 02 (2010-01-19)

Hi3520
11

0x004 IR_CFG 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ir_format
reserved
Name reserved ir_bits ir_freq
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved

00NEC with simple repeat code
01TC9012
[15:14] RW ir_format
10NEC with full repeat code
11SONY
11-16 11-18

0x000x2F 148
[13:8] RW ir_bits 0x300x3F
0x300x3F
ir_bits
[7] - reserved

[6:0] RW ir_freq
0x000x7F 1128
IR_LEADS
IR_LEADS
IR_BUSY[0]=0b0 IR_EN[0]=0b1

11-16 11-18 LEAD_S

02 (2010-01-19) 11-85

Hi3520
11
z 400 10s
8%D6121 LEAD_S 900
cnt_leads_min=90092%8280x33Ccnt_leads_max=900108%=972=0x3CC
z 400 10s
20%SONY-D7C5 LEAD_S 240
cnt_leads_min=24080%1920xC0cnt_leads_max=240120%=288=0x120
cnt_leads_max cnt_leads_min cnt_leads_min

cnt0_b_max cnt1_b_max

0x008 IR_LEADS 0x033C_03CC
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt_leads_min reserved cnt_leads_max
Reset 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0
[31:26] - reserved

[25:16] RW cnt_leads_min
0x0000x007
[15:10] - reserved

[9:0] RW cnt_leads_max
0x0000x007
IR_LEADE
IR_LEADE
z IR_BUSY[0]=0b0 IR_EN[0]=0b1

z NEC with simple repeat code cnt_sleade cnt_leade

8% 11-16 11-18 LEAD_E

11-86 02 (2010-01-19)

Hi3520
11
z 400 10s 8
D6121 LEAD_E 450
cnt_leade_min=45092%4140x19Ecnt_leade_max=450108%=486=0x1E6
z 400 10s
20%SONY-D7C5 LEAD_E 60
cnt_leade_min=6080%480x030cnt_leade_max=60120%=72=0x048
cnt_leade_max cnt_leade_min

0x00C IR_LEADE 0x019E_01E6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt_leade_min reserved cnt_leade_max
Reset 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0
[31:25] - reserved

[24:16] RW cnt_leade_min
0x0000x007
[15:9] - reserved

[8:0] RW cnt_leade_max
0x0000x007
IR_SLEADE
IR_SLEADE

z NEC with simple repeat code cnt_sleade cnt_leade

z NEC with simple repeat code

11-16 11-18 SLEAD_E

02 (2010-01-19) 11-87

Hi3520
11
z 225 10s
8%D6121 SLEAD_E 225
cnt_sleade_min=22592%2070xCFcnt_sleade_max=225108%=243=0xF3
z 225 10s
20% SLEAD_E 60
cnt_sleade_min=6080%480x30cnt_sleade_max=60120%=72=0x48
cnt_sleade_max cnt_sleade_min

0x010 IR_SLEADE 0x00CF_00F3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt_sleade_min reserved cnt_sleade_max
Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1
[31:25] - reserved

[24:16] RW cnt_sleade_min
0x0000x007
[15:9] - reserved

[8:0] RW cnt_sleade_max
0x0000x007
IR_B0
IR_B0 0

z bit0 bit1
bit1 bit0
bit0
20
z NEC with simple repeat codeNEC with simple repeat code TC9012
11-16 11-18 B0_H
D6121 B0_H 56 10s
cnt0_b_min=5680%450x2Dcnt0_b_max=56120%=67=0x43

11-88 02 (2010-01-19)

Hi3520
11
z SONY 11-16 11-18

B0_L SONY-D7C5 B0_L 60
10s cnt0_b_min=6080%480x30
cnt0_b_max=60120%=72=0x48
cnt0_b_max cnt0_b_min

0x014 IR_B0 0x002D_0043
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt0_b_min reserved cnt0_b_max
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1
[31:23] - reserved
bit0
[22:16] RW cnt0_b_min
0x000x07
[15:7] - reserved
bit0
[6:0] RW cnt0_b_max
0x000x07
IR_B1
IR_B1 1

z bit0 bit1
bit1 bit0
bit1
20
z NEC with simple repeat codeNEC with simple repeat code TC9012
11-16 11-18 B1_H
D6121 B1_H 169 10s
cnt1_b_min=16980%1350x87cnt1_b_max=169120%=203=0xCB
z SONY 11-16 11-18
B1_L SONY-D7C5 B1_L 120

02 (2010-01-19) 11-89

Hi3520
11
10s cnt1_b_min=12080%=96=0x60
cnt1_b_max=120120%=144=0x90
cnt1_b_max cnt1_b_min

0x018 IR_B1 0x0087_00CB
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved cnt1_b_min reserved cnt1_b_max
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1
[31:25] - reserved
bit1
[24:16] RW cnt1_b_min
0x0000x007
[15:9] - reserved
bit1
[8:0] RW cnt1_b_max
0x0000x007
IR_BUSY
IR_BUSY

0x01C IR_BUSY 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ir_busy
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved

[0] RO ir_busy 0
1

11-90 02 (2010-01-19)

Hi3520
11
IR_DATAH
IR_DATAH IR 16
IR_DATAH 16 IR_DATAL 32
11-
16 11-18
IR_DATAH IR_DATAL MSB

LSB IR_DATAL IR_DATAH
IR_DATAH IR_DATAL

0x020 IR_DATAH 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name reserved ir_datah
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:16] - reserved
[15:0] RO ir_datah 16
IR_DATAL
IR_DATAL IR 32

0x024 IR_DATAL 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name ir_datal
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] RO ir_datal 32
IR_INT_MASK
IR_INT_MASK IR

02 (2010-01-19) 11-91

Hi3520
11
IR_EN[0]=0b1

z
CPU

z

z

z
NEC with simple repeat code TC9012
160ms
NEC
with full repeat code SONY

0x028 IR_INT_MASK 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
intm_overflow 1 0
intm_framerr
intm_release
intm_rcv
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:4] - reserved

[3] RW intm_release 0
1

11-92 02 (2010-01-19)

Hi3520
11

[2] RW intm_overflow 0
1

[1] RW intm_framerr 0
1

[0] RW intm_rcv 0
1
IR_INT_STATUS
IR_INT_STATUS IR

0x02C IR_INT_STATUS 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
intms_overflow
intrs_overflow
intms_framerr
intms_release
intrs_framerr
intrs_release
intms_rcv
intrs_rcv
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:20] - reserved

[19] RO intms_release 0
1

[18] RO intms_overflow 0
1

[17] RO intms_framerr 0
1

02 (2010-01-19) 11-93

Hi3520
11

[16] RO intms_rcv 0
1
[15:4] - reserved

[3] RO intrs_release 0
1

[2] RO intrs_overflow 0
1

[1] RO intrs_framerr 0
1

[0] RO intrs_rcv 0
1
IR_INT_CLR
IR_INT_CLR IR

0x030 IR_INT_CLR 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
intc_overflow
intc_framerr
intc_release
intc_rcv
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:4] - reserved

[3] WO intc_release 0
1

11-94 02 (2010-01-19)

Hi3520
11

[2] WO intc_overflow 0
1

[1] WO intc_framerr 0
1

0
[0] WO intc_rcv 1
IR_DATAL
1
IR_START
IR_START IR
IR


0x034 IR_START 0x0000_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ir_start
Name reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:1] - reserved
[0] WO ir_start IR
11.5 GPIO
11.5.1
Hi3520 8 GPIOGeneral Purpose Input/Output GPIO 8

GPIO

02 (2010-01-19) 11-95

Hi3520
11
GPIO 0 1 GPIO
2.2 2.5
11.5.2
GPIO
z GPIO
GPIO
GPIO 0 1
z GPIO GPIO_IS 7
GPIO 3.4 INT
GPIO
3-4 VIC0 3-5 VIC1
GPIO_ISGPIO_IBEGPIO_IEV

GPIO_RIS GPIO_MIS
GPIO_IE GPIO_IC

11.5.3
GPIO 11-20 11.5.5

11-20 GPIO
GPIO0_0 I/O GPIO I2C SDA
GPIO0_1 I/O GPIO I2C SCL
GPIO0_2 I/O GPIO SIO0 I2S SIO0XFS

GPIO0_3 I/O GPIO SIO0 SIO0XCK

GPIO0_4 I/O GPIO SIO0 ACKOUT

GPIO0_5 I/O GPIO SIO2 SIO2DI

GPIO0_6 I/O GPIO SIO2 I2S SIO2RFS

GPIO0_7 I/O GPIO SIO2 SIO2RCK

11-96 02 (2010-01-19)

Hi3520
11
GPIO1_0 I/O GPIO GMAC GTCLKOU

T
GPIO1_1 I/O GPIO GMAC GCOL

GPIO1_2 I/O GPIO GMAC GCRS

GPIO1_3 I/O GPIO VI0 VI0HS

GPIO1_4 I/O GPIO VI0 VI0VS

GPIO1_5 I/O GPIO VO0 VO0CK

GPIO1_6 I/O GPIO VO1 VO1DAT7

DAT7

DAT15

DAT0

DAT1

DAT2

DAT3

DAT4

DAT5

DAT6

DAT7
GPIO3_0 I/O GPIO VOBDAT7 GPIO3_0

VO RGB blue DAT7
GPIO3_1 I/O GPIO Nand Flash NFRB

02 (2010-01-19) 11-97

Hi3520
11
GPIO3_2 I/O GPIO SMI 1 SMICS1N
GPIO3_3 I/O GPIO Nand Flash 1 NFCS1N

GPIO3_4 I/O GPIO VI2 VI2HS

GPIO3_5 I/O GPIO VI2 VI2VS

GPIO3_6 I/O GPIO PCI 3 PCIREQ3N

GPIO3_7 I/O GPIO PCI 4 PCIREQ4N

GPIO4_0 I/O GPIO VI1 0 VI1DAT0

11-98 02 (2010-01-19)

Hi3520
11
GPIO7_0 I/O GPIO PCI 3 PCIGRANT

3N
GPIO7_1 I/O GPIO PCI 4 PCIGRANT

4N
GPIO7_2 I/O GPIO V01 VO1CK

GPIO7_3 I/O GPIO VO RGB VORGBDV

GPIO7_4 I/O GPIO VIO1 VO1DAT13

DAT13
GPIO7_5 I/O GPIO VIO1 VO1DAT14

DAT14
GPIO7_6 I/O -
GPIO7_7 I/O -
11.5.4
GPIO 8

GPIO GPIOINTRGeneral Purpose Input

Output Interrupt
11.5.5
GPIO GPIO IO Config

GPIO 11-21

02 (2010-01-19) 11-99

Hi3520
11
11-21
GPIO0_0 reg63 I2C SDA
GPIO0_1 reg64 I2C SCL
GPIO0_2 reg65 SIO0 I2S
GPIO0_3 reg66 SIO0
GPIO0_4 reg67 SIO0
GPIO0_5 reg68 SIO2 SIO1DO
GPIO0_6 reg69 SIO2 I2S

SIO1XFS
GPIO0_7 reg70 SIO2 SIO1XCK

GPIO1_0 reg75 GMAC
GPIO1_1 reg76 GMAC
GPIO1_2 reg77 GMAC
GPIO1_3 reg0 VI0 URXD2

GPIO1_4 reg1 VI0 UTXD2

GPIO1_5 reg36 VO0 VORDAT0

GPIO1_6 reg53 VO1 DAT7 VOGDAT6

GPIO1_7 reg61 VO1 DAT15

VORDAT1

VORDAT2

VORDAT3

VORDAT4

VORDAT5

11-100 02 (2010-01-19)

Hi3520
11

VORDAT6

VORDAT7

VOGDAT0
GPIO3_0 reg62 VOBDAT7 VO RGB

blue DAT7
GPIO3_1 reg73 Nand Flash
GPIO3_2 reg71 SMI 1
GPIO3_3 reg72 Nand Flash 1


GPIO3_6 reg78 PCI 3
GPIO3_7 reg79 PCI 4
GPIO4_0 reg10 VI1 0 VOUDAT8
GPIO5_0 reg20 VI2 0
GPIO5_1 reg21 VI2 1
GPIO5_2 reg22 VI2 2
GPIO5_3 reg23 VI2 3
GPIO5_4 reg24 VI2 4
GPIO5_5 reg25 VI2 5

02 (2010-01-19) 11-101

Hi3520
11
GPIO5_6 reg26 VI2 6
GPIO5_7 reg27 VI2 7
GPIO6_0 reg28 VI3 0
GPIO6_1 reg29 VI3 1
GPIO6_2 reg30 VI3 2
GPIO6_3 reg31 VI3 3
GPIO6_4 reg32 VI3 4
GPIO6_5 reg33 VI3 5
GPIO6_6 reg34 VI3 6
GPIO6_7 reg35 VI3 7
GPIO7_0 reg80 PCI 3
GPIO7_1 reg81 PCI 4
GPIO7_2 reg45 V01

SDIOCK
GPIO7_3 reg82 VO RGB
GPIO7_4 reg59 VIO1 DAT13

VOBDAT4VGA0HS
GPIO7_5 reg60 VIO1 DAT14

VOBDAT5VGA0VS
GPIO7_6 -
GPIO7_7 -
GPIO
z GPIO_IE
z 0
z
z 0
z

11-102 02 (2010-01-19)

Hi3520
11
1 11-21 IO Config GPIO
2 GPIO_DIR GPIO
z GPIO GPIO GPIO_DATA
GPIO

z GPIO GPIO_DATA GPIO
GPIO

----
1 GPIO_IS
2 GPIO_IEV//
3 GPIO_IBE
4 GPIO
5 GPIO_IC 0xFF
6 GPIO_IE 1
----
GPIO 7 GPIO

z
z
11.5.6
8 GPIO 11-22
11-22 8 GPIO
GPIO0 0x2015_0000
GPIO1 0x2016_0000
GPIO2 0x2017_0000

02 (2010-01-19) 11-103

Hi3520
11
GPIO3 0x2018_0000
GPIO4 0x2019_0000
GPIO5 0x201A_0000
GPIO6 0x201B_0000
GPIO7 0x201C_0000
11-23 GPIO GPIO0GPIO7

GPIOn GPIOn +
11-23 GPIO
0x000 GPIO_DATA GPIO 11-104

0x3FC
0x400 GPIO_DIR GPIO 11-105
0x404 GPIO_IS GPIO 11-106
0x408 GPIO_IBE GPIO 11-106
0x40C GPIO_IEV GPIO 11-106
0x410 GPIO_IE GPIO 11-107
0x414 GPIO_RIS GPIO 11-107
0x418 GPIO_MIS GPIO 11-108
0x41C GPIO_IC GPIO 11-108
0x420 GPIO_RESERVED GPIO 11-109
11.5.7
GPIO_DATA
GPIO_DATA GPIO
GPIO_DIR GPIO_DATA

11-104 02 (2010-01-19)

Hi3520
11
GPIO_DIR

GPIO_DATA PADDR[9:2]
256 PADDR[9:2] GPIO_DATA[7:0] bit
bit
z 0x3FC0b11_1111_1100 GPIO_DATA[7:0] 8bit

z 0x2000b10_0000_0000 GPIO_DATA[7]
0x0000x3FC GPIO_DATA 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_data
Reset 0 0 0 0 0 0 0 0
GPIO GPIO
[7:0] RW gpio_data GPIO
GPIO_DIR
GPIO_DIR
GPIO_DIR GPIO GPIO

0x400 GPIO_DIR 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_dir
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RW gpio_dir
0
1

02 (2010-01-19) 11-105

Hi3520
11
GPIO_IS
GPIO_IS GPIO GPIO

0x404 GPIO_IS 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_is
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RW gpio_is
0
1
GPIO_IBE
GPIO_IBE GPIO GPIO

0x408 GPIO_IBE 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_ibe
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RW gpio_ibe 0
GPIO_IEV
1
GPIO_IEV
GPIO_IEV GPIO GPIO

11-106 02 (2010-01-19)

Hi3520
11

0x40C GPIO_IEV 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_iev
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RW gpio_iev
0
1
GPIO_IE
GPIO_IE GPIO GPIO

0x410 GPIO_IE 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_ie
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RW gpio_ie
0
1
GPIO_RIS
GPIO_RIS GPIO GPIO

02 (2010-01-19) 11-107

Hi3520
11

0x414 GPIO_RIS 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_ris
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RO gpio_ris GPIO_IE
0
1
GPIO_MIS
GPIO_MIS GPIO GPIO

0x418 GPIO_MIS 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_mis
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] RO gpio_mis GPIO_IE
0
1
GPIO_IC
GPIO_IC GPIO GPIO
GPIO_RIS GPIO_MIS

11-108 02 (2010-01-19)

Hi3520
11

0x41C GPIO_IC 0x00
Bit 7 6 5 4 3 2 1 0
Name gpio_ic
Reset 0 0 0 0 0 0 0 0
GPIO bit[7:0]
GPIO_DATA[7:0]
[7:0] WC gpio_ic
0
1
GPIO_RESERVED
GPIO_RESERVED GPIO

0x420 GPIO_RESERVED 0x00
Bit 7 6 5 4 3 2 1 0
Name reserved
Reset 0 0 0 0 0 0 0 0
[7:0] RW reserved 0x00

02 (2010-01-19) 11-109

Hi3520
12
12
12.1
Hi3520 JTAG IEEEInstitute of Electrical and Electronics Engineers
1149.1 ARM
12.2
Hi3520 2 TESTMODE 2
Hi3520 12-1
12-1 Hi3520
TESTMODE
0 Hi3520 JTAG ARM
1 Hi3520 DFTDesign For Test

12.3 JTAG
12.3.1
Hi3520 JTAG JTAG Hi3520 JTAG
12-2
12-2 Hi3520 JTAG
TCK JTAG

02 (2010-01-19) 12-1

Hi3520
12
TDI JTAG
TMS JTAG
TRSTN JTAG
JTAG Realview-ICE
TDO JTAG
12.3.2
ARM
JTAG ICE RealView-ICE
JTAG 2 ARM 12-1
12-1 ARM
RealView-ICE
Embeded Embeded
ICE ICE
ARM926EJ-S ARM1176ZJF-S
Hi3520
JTAG ARM RealView-ICE

TESTMODE 0
EBIADR21 EBIADR22 ARM926

ARM1176 ARM926 ARM1176 12-3

12-2 02 (2010-01-19)

Hi3520
12
z ARM JTAG EBIADR21 EBIADR22

z EBIADR21 EBIADR22

12-3 ARM9 ARM11
EBIADR21 EBIADR22
ARM1176ZJF-S
ARM926EJ-S
ARM1176ZJF-S ARM926EJ-
S
Hi3520 JTAG
Hi3520 JTAG
TESTMODE 1

02 (2010-01-19) 12-3

Hi3520
13
13
13.1
13.1.1
H.264JPEG/MJPEG
ARM Video Codec Firmware

13.1.2

z H.264 Main Profile@Level 4.0
8 D1 /PALD1@200fps
NTSCD1@240fps 2 720p30 /
4 D1+CIF4 D1 720p30

z JPEG/MJPEG Baseline
JPEG 300
20fps
JPEG
z
H.264/H.264H.264/JPEGJPEG/H.264JPEG/JPEG

1:12:14:1
CIF
z de-interlace
de-interlace /
z

02 (2010-01-19) 13-1

Hi3520
13

z OSD
4 OSD
OSD
129 alpha
OSD
z
SADSum Of Absolute Difference
MV
z H264 CBR/VBR/ABR 16kbit/s20Mbit/s
z

z
13.2 TDE
13.2.1
2D TDETwo Dimensional Engine
CPU TDE AHB Master

AHB Slave CPU
1 2
z 1
z 2
1 2 ROP

13.2.2
TDE
z 1 RGB444RGB555RGB565RGB888ARGB4444
ARGB1555ARGB8565ARGB8888CLUT1CLUT2CLUT4CLUT8
ACLUT44ACLUT88A1A8YCbCr888AYCbCr8888YCbCr422byte
halfwordYCbCr400MB YCbCr422MBHYCbCr422MBVYCbCr420MB
YCbCr444MB 2 RGB444RGB555RGB565RGB888
ARGB4444ARGB1555ARGB8565ARGB8888CLUT1CLUT2CLUT4
CLUT8ACLUT44ACLUT88A1A8YCbCr888AYCbCr8888
YCbCr422YCbCr400MB YCbCr422MBHYCbCr422MBVYCbCr420MB
YCbCr444MB

13-2 02 (2010-01-19)

Hi3520
13
z RGB444RGB555RGB565RGB888ARGB4444
ARGB1555ARGB8565ARGB8888CLUT1CLUT2CLUT4CLUT8
ACLUT44ACLUT88A1A8YCbCr888AYCbCr8888YCbCr422byte
halfwordYCbCr400MB YCbCr422MBHYCbCr422MBVYCbCr420MB
YCbCr444MB
z
z 1 2
z Gamma
z CLUT
z RGB YCbCr
z
z
z 2D-resize
z
z clip
z alpha blending
z ROP
z colorkey
z
z clip mask
z /
z

02 (2010-01-19) 13-3

Hi3520
A
ACD Auto Command Done
AES Advanced Encryption Standard

AHB Advanced High-performance Bus -
AMBA Advanced Microcontroller Bus Architecture

ARM ARM ARM RISC Core
BVACT Bottom Vertical Active Area
BVBB Bottom Vertical Back Blank
BVFB Bottom Vertical Front Blank
CBC Cipher Block Chaining
CD Command Done
CFB Cipher Feedback
CL CAS Latency
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CRG Clock Reset Generation
CTR Counter

02 (2010-01-19) A-1

Hi3520
A
DCRC Data CRC Error CRC
DDR Double Data-Rate
DES Data Encryption Standard
DFT Design For Test
DLL Delay Locked Loop
DMA Direct Memory Access
DMAC Direct Memory Access Controller
DQS Data Strobe
DRTO Data Read Timeout
DTO Data Transfer Over
DVR Digital Video Recorder
EBE End-bit error
EBI External Bus Interface
ECB Electronic Codebook
EOF End Of Frame
EOP End Of Packet
ETH Ethernet MAC
FIFO First In First Out
FIQ Fast Interrupt Request
FRUN FIFO Underrun/Overrun Error FIFO
GPIO General Purpose Input/Output /
HACT Horizontal Active Area

A-2 02 (2010-01-19)

Hi3520
A
HCCA Host Controller Communication Area
HFB Horizontal Front Blank
HLE Hardware Locked Error
HPW Horizontal Pulse Width
HTO Data starvation-by-host timeout
HBB Horizontal Back Blank
I2C Inter-Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
I2S Inter-IC Sound I2S
IR Infrared Remoter
IRQ Interrupt Request
ISR Interrupt Service Routine
ITCM Instruction TCM
IV Initialization Vector
JTAG Joint Test Action Group
LSB Least Significant Bit bit
MAC Media Access Control
MCU Micro Controller Unit
MDIO Management Data Input/Output
MII Media Independent Interface
MMC Multi-media Card
MSB Most Significant Bit bit

02 (2010-01-19) A-3

Hi3520
A
NTSC National Television Systems Committee
OFB Output Feedback
OHCI Open Host Controller Interface
OSD On Screen Display

OTG On-The-Go -
PAL Phase Alternating Line
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
PCM Pulse Code Modulation
PID Packet ID
PSRAM Pseudo Static Random Access Memory
Q
QXGA Quantum Extended Graphics Array

RAM Random-Access Memory
RCRC Response CRC error CRC
RE Response error
ROM Read Only Memory
ROP Raster Operation
RTO Response Timeout
RXDR Receive FIFO data request FIFO
SAD Sum Of Absolute Difference

A-4 02 (2010-01-19)

Hi3520
A
SBE Start-bit Error
SCL Serial Clock
SCR System Clock Reference
SD Secure Digital
SDA Serial Data
SDIO secure digital Input/Output

SDRAM Synchronous Dynamic Random Access
Memory
SFD Start of Frame Delimiter
SI Specific Information
SIO Sonic Input/Output
SMI Static Memory Interface
SOF Start Of Frame
SPI Synchronous Peripheral Interface
SRAM Static Random Access Memory
SSP Synchronous Serial Port
TCM Tightly-Coupled Memory
TDE Two Dimension Engine 2D
TVACT Top Vertical Active Area
TVBB Top Vertical Back Blank
TVFB Top Vertical Front Blank
TXDR Transmit FIFO Data Request FIFO
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
VACT Vertical Active Area
VBB Vertical Back Blank

02 (2010-01-19) A-5

Hi3520
A
VBI Vertical Blanking Interval
VEDU Video Encoding Decoding Unit
VFB Vertical Front Blank
VIU Video Input Unit
VOU Video Output Unit
VPW Vertical Pulse Width

A-6 02 (2010-01-19)

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About This Document.....................................................................................................................1

2.1.12 JTAG Pins .....................................................................................................................................2-44

3.1 Reset ............................................................................................................................................................3-1

3.8.4 Function Description .....................................................................................................................3-108

4 Memory Controller ....................................................................................................................4-1

4.3.2 Features ...........................................................................................................................................4-52

6 Video Interface ...........................................................................................................................6-1

7.2 Features .......................................................................................................................................................7-1

8 MMC/SD/SDIO Controller ......................................................................................................8-1

10 USB 2.0 Host............................................................................................................................10-1

10.3 Function Description ...............................................................................................................................10-1

11 Other Peripheral Interfaces..................................................................................................11-1

11.2.1 Overview ..................................................................................................................................... 11-31

11.5 GPIO...................................................................................................................................................... 11-98

13 Video Processing Module.....................................................................................................13-1

A Acronyms and Abbreviations............................................................................................... A-1

Figure 1-1 Logic block diagram of the Hi3520 ................................................................................................1-1

Figure 1-3 Block diagram of the Hi3520 in a 4-channel D1 DVR ...................................................................1-8

Figure 2-5 DDR2 SDRAM output timing .................................................................................................... 2-113

Figure 2-11 Transmit timing of the RGMII interface ................................................................................... 2-116

Figure 2-23 SSP_SPICK clock timing of the SSP interface .........................................................................2-123

Figure 2-36 Schematic colors in each pinout diagram..................................................................................2-132

Figure 2-39 Hi3520 pinout (rows UAM, columns 116) ...........................................................................2-135

Figure 3-2 Functional block diagram of the clock management module..........................................................3-4

Figure 3-11 Diagram of updating channel registers through LLI ...................................................................3-42

Figure 3-16 ECB mode of the 3DES algorithm..............................................................................................3-70

Figure 4-2 Diagram of connecting the DDRC to two DDR2 SDRAMs...........................................................4-6

Figure 4-8 Block diagram of NANDC interfaces ...........................................................................................4-54

Figure 5-2 Ethernet II frame format .................................................................................................................5-4

Figure 5-4 Data storage format in the downlink configuration FIFO...............................................................5-6

Figure 6-10 NTSC vertical sync timings ........................................................................................................6-10

Figure 6-13 DC vertical pulse timing .............................................................................................................6-12

Figure 6-28 Software configuration process...................................................................................................6-23

Figure 6-30 Parameter diagram of the captured image...................................................................................6-36

Figure 7-5 Timing diagram of the I2S interface ...............................................................................................7-6

Figure 8-2 Functional block diagram of the MMC...........................................................................................8-4

Figure 9-2 Architecture of the Hi3520 PCI module..........................................................................................9-5

Figure 10-2 Reference design of the USB 2.0 host ........................................................................................10-4

Figure 11-5 Typical application block diagram 2 of the UART.................................................................... 11-34

Figure 11-19 TI synchronous serial single frame format .............................................................................. 11-59

Table 2-1 I/O type of pins .................................................................................................................................2-1

Table 2-3 SIO pins ..........................................................................................................................................2-22

Table 2-6 DDRB pins .....................................................................................................................................2-30

Table 2-9 VO pins...........................................................................................................................................2-38

Table 2-12 I2C pins.........................................................................................................................................2-44

Table 2-15 USB pins.......................................................................................................................................2-45

Table 2-18 Software multiplexing signals of the VI interface ........................................................................2-50

Table 2-24 Software multiplexing signals of the SIO interface ......................................................................2-56

Table 2-27 Software multiplexing pins of the GMAC interface .....................................................................2-58

Table 2-40 Memory device parameters......................................................................................................... 2-113

Table 2-43 Timing parameters of the RGMII interface................................................................................. 2-117

Table 2-46 Timing parameters of the VI interface ........................................................................................ 2-119

Table 2-55 Timing parameters of the I2S interface .......................................................................................2-127

Table 2-58 Statistics on the Hi3520 pins.......................................................................................................2-131

Table 3-1 Types of reset signals ........................................................................................................................3-2

Table 3-14 Clock frequency configuration of the VI module .........................................................................3-13

Table 3-17 Selection of the boot mode ...........................................................................................................3-17

Table 3-20 Interrupt mapping of VIC0 ...........................................................................................................3-32

Table 3-29 Summary of CIPHER register (base address: 0x100C_0000) ......................................................3-80

Table 4-15 K9F2G08U0M addresses..............................................................................................................4-58

Table 4-18 Summary of NANDC registers (base address: 0x1000_0000) .....................................................4-65

Table 6-5 ITU-R BT.656 error-correcting codes...............................................................................................6-6