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KTS - Cac BT Giai San Ve VHDL 2011 PDF
KTS - Cac BT Giai San Ve VHDL 2011 PDF
Mn hc: K thut s
GVPT: H Trung M
Bi tp gii sn v VHDL (AY1112-S1)
(Cc m VHDL c chy th trn Altera MaxplusII v10.2)
Phn u dng th vin IEEE v khai bo entity th ging nhau cho cc cch:
TD: Vi khai bo ca cch 1:
library ieee;
use ieee.std_logic_1164.all;
entity ONES_CNT_EX1 is
Ch :
C cch gii khc trong th d ca MaxplusII:
-- MAX+plus II VHDL Example
-- Combinatorial Process Statement
-- Copyright (c) 1994 Altera Corporation
ENTITY proc IS
PORT
(
d : IN BIT_VECTOR (2 DOWNTO 0);
q : OUT INTEGER RANGE 0 TO 3
);
END proc;
q <= num_bits;
END PROCESS;
END maxpld;
c) Lnh case-when
Process(A) -- Sensitivity List Contains only Vector A
begin
CASE A is
WHEN "000" => C <= "00";
WHEN "001" => C <= "01";
WHEN "010" => C <= "01";
WHEN "011" => C <= "10";
WHEN "100" => C <= "01";
WHEN "101" => C <= "10";
WHEN "110" => C <= "10";
entity ONES_CNT_EX4 is
port ( A : in STD_LOGIC_VECTOR(2 downto 0);
C : out STD_LOGIC_VECTOR(1 downto 0));
end ONES_CNT_EX4;
architecture Structural of ONES_CNT_EX4 is
COMPONENT MAJ3
PORT( X: in STD_LOGIC_VECTOR(2 downto 0);
Z: out STD_LOGIC);
END COMPONENT;
COMPONENT OPAR3
PORT( X: in STD_LOGIC_VECTOR(2 downto 0);
Z: out STD_LOGIC);
END COMPONENT;
--
begin
-- Instantiate Components
--
c1: MAJ3 PORT MAP (A, C(1));
c2: OPAR3 PORT MAP (A, C(0));
end Structural;
Ch :
Ta c th s dng lun cc component c sn ca Altera MaxplusII. Tuy nhin lu phi khai
bo component ng vi khai bo ca Altera MaxplusII!
Cc cng logic ca Maxplus II c cc khai bo sau:
1) Cng NOT vi tn l A_NOT c khai bo sau:
COMPONENT a_not
PORT( a_in: in STD_LOGIC;
a_out: out STD_LOGIC);
END COMPONENT;
Cc BT gii sn v VHDL 2011 trang 7
2) Cng AND c th c n ng vo (ANDn) vi n=2, 3, 4, 6, 8 v 12.
TD: Khai bo sau cho cng AND c 2 ng vo:
COMPONENT and2
PORT( IN1, IN2: in STD_LOGIC;
a_out: out STD_LOGIC);
END COMPONENT;
3) Cng OR c th c n ng vo (ORn) vi n=2, 3, 4, 6, 8 v 12.
TD: Khai bo sau cho cng OR c 2 ng vo:
COMPONENT or3
PORT(IN1, IN2, IN3: in STD_LOGIC;
a_out: out STD_LOGIC);
END COMPONENT;
4) Cng NAND c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12.
5) Cng NOR c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12.
6) Cng XOR 2 ng vo c tn l a_XOR vi khai bo sau:
COMPONENT a_xor
PORT(IN1, IN2: in STD_LOGIC;
a_out: out STD_LOGIC);
END COMPONENT;
7) Cng XNOR 2 ng vo c tn l a_XNOR
Nh vy ta c li gii khc ngn hn nu s dng cc component c sn ca Maxplus II:
----- Use built-in components of MaxplusII
----------------- Majority of 3 bit number----------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity MAJ3 is
PORT( X: in STD_LOGIC_VECTOR(2 downto 0);
Z: out STD_LOGIC);
end MAJ3;
architecture Structural_M of MAJ3 is
COMPONENT and2
PORT( IN1, IN2: in STD_LOGIC; -- Declare Components
a_out: out STD_LOGIC); -- To Be Instantiated
END COMPONENT;
COMPONENT or3
PORT(IN1, IN2, IN3: in STD_LOGIC;
a_out: out STD_LOGIC);
END COMPONENT;
--
SIGNAL A1,A2,A3: STD_LOGIC; -- Declare Maj3 Local Signals
begin
-- Instantiate Gates
g1: and2 PORT MAP (X(0), X(1), A1);
g2: and2 PORT MAP (X(0), X(2), A2); -- Wiring of
g3: and2 PORT MAP (X(1), X(2), A3); -- Maj3
entity ONES_CNT_EX4B is
port ( A : in STD_LOGIC_VECTOR(2 downto 0);
C : out STD_LOGIC_VECTOR(1 downto 0));
end ONES_CNT_EX4B;
architecture Structural of ONES_CNT_EX4B is
2. Vi mch t hp sau:
architecture bg of blackbox is
signal s0, s1, s2, s3, s4 : std_logic;
--signal command : std_logic_vector(1 downto 0);
begin
s0 <= a and s4;
s1 <= a or s4;
s2 <= a xor s4;
s3 <= a xor s4 xor cin;
cout <= (a and s4) or ( s4 and cin) or (a and cin);
U1: process(inst)
begin
case(inst(2 downto 1)) is
when "00" => F <= s0;
when "01" => F <= s1;
when "10" => F <= s2;
when others => F <= s3;
end case;
end process;
U2: process(inst)
begin
if (inst(0) = '0') then
s4 <= b;
else
s4 <= not b;
end if;
end process;
end bg;
Bi gii.
Ta thy 2 php gn sau :
s3 <= a xor s4 xor cin;
cout <= (a and s4) or ( s4 and cin) or (a and cin);
nhm thc hin mch FA, do c th dng khi ny trong mch logic.
Process U1 chnh l MUX 4 sang 1 vi ng chn l inst(2:1).
Process U2 chnh l MUX 2 sang 1 vi ng chn l inst(0).
T ta c mch logic ca m VHDL trn l: (ALU 1 bit)
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is port(
J, K, CLK, PR, CLR: in std_logic;
Q, Q_n: out std_logic);
end JK_FF;
architecture bg of Q07_2 is
signal Q_int: std_logic;
signal JK: std_logic_vector(1 downto 0);
begin
JK <= J & K;
process(CLK, PR, CLR)
begin
if (CLR = '1') then
Q_int <= '0';
elsif (PR = '1') then
Q_int <= '1';
elsif rising_edge(CLK) then
case JK is
when "01" => Q_int <= '0'; -- Reset
when "10" => Q_int <= '1'; -- Set
when "11" => Q_int <= not Q_int;-- Toggle
when others => null;
end case;
end if;
end process;
Q <= Q_int;
Q_n <= not Q_int;
end bg;
c) Ta ch cn vit li nh sau :
8. Thit k mch cng song song 2 s nh phn N bit (dng pht biu generic thit k tng
qut, mc nhin N =4) l A v B. Tng l Sum v s nh/mn l C_out.
a) M t VHDL cho mch ny.
b) Thm vo tn hiu iu khin cho php cng/tr vi tn l Add_Sub (0: cng v 1:tr)
th phi chnh sa nh th no?
Bi gii.
a) Khi s dng ton t cng/tr th ta phi dng gi ieee.std_logic_unsigned.all :
-- Parallel Adder
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Q08_1 is
generic (N: integer := 4);
port(
A, B: in std_logic_vector(N-1 downto 0);
C_out: out std_logic;
Sum: out std_logic_vector(N-1 downto 0));
end Q08_1;
architecture bg of Q08_1 is
signal Sum_int: std_logic_vector(Num downto 0);
begin
Sum_int <= ('0' & A) + ('0' & B);
Sum <= Sum_int(N-1 downto 0);
C_out <= Sum_int(N);
end bg;
Ch :
C 1 cch gii khc l tn dng ton t + (trong ieee.std_logic_unsigned.all) tm C v S :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
. . .
-- Thay dng: variable S, C_in: std_logic; bng dng sau:
variable CS: std_logic_vector(1 downto 0); -- Carry v Sum
. . .
-- M mi phn tnh full adder nh sau:
if (FIN = '0') then
CS := ('0' & CS(1)) + ('0' & A) + ('0' & B) ;
Sum_int := CS(0) & Sum_int(Num_bits-1 downto 1);
N := N - 1;
if N = 0 then
FIN := '1';
Finished <= '1';
Sum <= Sum_int;
C_out <= CS(1);
end if;
end if;
Cc BT gii sn v VHDL 2011 trang 22
10. Cho trc h tun t ng b sau:
Ch :
C nhiu cch vit khc m t FSM, th d sau y l 1 cch vit khc:
library ieee;
use ieee.std_logic_1164.all;
entity Q10_2 is
port(
X, CLK, reset_n: in std_logic;
Z: out std_logic);
end Q10_2;
architecture bg of Q10_2 is
signal Present_state: std_logic_vector( 1 downto 0); --
PS
signal Next_state: std_logic_vector( 1 downto 0); --
NS
begin
Z <= '0' when Present_state = "01" else '1';
State_transition:
process(CLK, reset_n)
begin
if (reset_n = '0') then
Present_state <= "00";
elsif rising_edge(CLK) then
Present_state <= Next_state ;
end if;
end process;
Cc BT gii sn v VHDL 2011 trang 24
Find_Next_state:
process(Present_state)
begin
case Present_state is
when "00" => if X = '0' then
Next_state <= "10";
else
Next_state <= "01";
end if;
when "01" => Next_state <= "10";
when "11" => if X = '0' then
Next_state <= "00";
else
Next_state <= "10";
end if;
when "10" => if X = '0' then
Next_state <= "00";
else
Next_state <= "01";
end if;
when others => null;
end case;
end process;
end bg;
11. Thit k mch pht hin chui bit vo ni tip c tr l "101". Vit m VHDL vi:
a) Dng FSM loi Mealy vi m t FSM.
b) FSM loi Mealy dng thanh ghi dch cha 3 bit lin tip v so snh vi "101".
Bi gii.
a) FSM loi Mealy
Ta c c gin trng thi v bng chuyn trng thi nh sau (kt qu ly t bi
ging thit k h tun t ng b)
12. Thit k mch gii m 3 sang 8 v mch m ha u tin 8 sang 3 (u tin ng vo c trng
s thp nht khi c nhiu bit vo l 1).
Mch gii m c cc ng vo l C, B, v A (LSB) v ra l Y.
Mch m ha c ng vo 8 bit D_in v ng ra 3 bit D_out.
Bi gii.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- Dung cho ham conv_std_logic_vector(integer, number of bits)
use ieee.std_logic_unsigned.all;
-- Dung cho ham conv_integer(std_logic_vector)
entity Q12_1 is
port( C, B, A: in std_logic; -- A: LSB
Y: out std_logic_vector(0 to 7);
D_in: in std_logic_vector(0 to 7);
D_out: out std_logic_vector(0 to 2));
end Q12_1;
architecture bg of Q13_1 is
COMPONENT DFF
PORT (d : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC );
END COMPONENT;
-- Inputs | Output
--prn clrn CLK D | Q
-- L H X X | H
-- H L X X | L
-- L L X X | Illegal
-- H H L | L
-- H H H | H
-- H H L X | Qo*
-- H H H X | Qo
-- * Qo = level of Q before Clock pulse
-- All flipflops are positive-edge-triggered.
signal D0, D1, D2, prn: std_logic;
signal Q2_int, Q1_int, Q0_int: std_logic;
begin
U1: DFF port map(D0, CLK, reset_n, prn, Q0_int);
U2: DFF port map(D1, D0, reset_n, prn, Q1_int);
U3: DFF port map(D2, D1, reset_n, prn, Q2_int);
prn <= '1';
D0 <= not Q0_int; D1 <= not Q1_int; D2 <= not Q2_int;
Q0 <= Q0_int; Q1 <= Q1_int; Q2 <= Q2_int;
end bg;
architecture bg of Q14_1 is
COMPONENT JKFF
PORT (j : IN STD_LOGIC;
k : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;
-- Inputs | Output
-- PRN CLRN CLK J K | Q
-- L H X X X | H
-- H L X X X | L
-- L L X X X | Illegal
-- H H L X X | Qo*
-- H H L L | Qo*
-- H H H L | H
-- H H L H | L
-- H H H H | Toggle
-- * Qo = level of Q before Clock pulse
-- All flipflops are positive-edge-triggered.
signal J0, J1, J2, prn: std_logic;
begin
U1: JKFF port map(J0, J0, CLK, reset_n, prn, Q0);
U2: JKFF port map(J1, J1, CLK, reset_n, prn, Q1);
U3: JKFF port map(J2, J2, CLK, reset_n, prn, Q2);
prn <= '1'; J0 <= '1'; J1 <= Q0; J2 <= Q1 and Q0;
end bg;
Cc BT gii sn v VHDL 2011 trang 31
b) Cc lnh tun t:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; -- De tinh cong so nhi phan
voi so nguyen
entity Q14_2 is
port( CLK, reset_n: in std_logic;
Q2, Q1, Q0: out std_logic); -- Q0: LSB
end Q14_2;
architecture bg of Q14_2 is
signal Q: std_logic_vector(2 downto 0);
begin
process(CLK)
begin
if reset_n ='0' then
Q <= "000";
elsif rising_edge(CLK) then
Q <= Q + 1;
end if;
end process;
Q2 <= Q(2); Q1 <= Q(1); Q0 <= Q(0);
end bg;
c) Vi dy m 1, 3, 5, 7, 1, . .
Ch cn sa li trong phn process ca b) nh sau:
if reset_n ='0' then
Q <= "001";
elsif rising_edge(CLK) then
if Q = "111" then
Q <= "001";
else
Q <= Q + 2;
end if;
end if;