An Improved PSO Approach for Optimal Tuning of

PI Controller for Shunt Active Power Filter using

FPGA with Hardware Co-Simulation
Abhishek Awasthi
Dept. of Electrical Engg,
MNNIT Allahabad,
abhishekawasthi761993@gmail.com
Dinesh Chandra Rajasekar S
Dept. of Electrical Engg, Smart Energy Division,
MNNIT Allahabad, NEC Laboratories Singapore
dinuchandra@rediffmail.com rajasekar6387@gmail.com

Asheesh K. Singh P. Karuppanan Ajay-D-Vimal Raj

Dept. of Electrical Engg, Dept. of Electronics & Communication Dept. of Electrical Engg
MNNIT Allahabad, Engineering Pondicherry Engg. College,
asheeshks@gmail.com MNNIT Allahabad, ajayvimal@pec.edu
karuppanan1982@gmail.com

Abstract The present paper deals with the development and
dynamic performance of non-model based dc link voltage
proportional integral (PI) controller for a three phase shunt
active power filter (SAPF) implemented using hardware co-
simulation. PI controller parameters are tuned using
conventional Particle Swarm Optimization (PSO) and Improved
Particle Swarm Optimization (IPSO), proposed approach shows
the systems performance enhancement as IPSO negates
premature convergence and simplifies computational complexity
by neglecting each particles best position in the algorithm. The
integral time absolute error (ITAE) is taken as the objective
function, which is to be minimized. The dynamic performance of
PSO-PI and IPSO-PI controller is tested for different dynamic
conditions such as step change in reference voltage and load
transients. Extensive simulation studies performed with
nonlinear loads in MATLAB/SIMULINK validate the
superiority and better overall performance of the proposed IPSO
tuned PI controller.
Keywords Field Programmable Gate Array (FPGA);
hardware co-simulation; improved particle swarm optimization
(PSO); PI controller, servo performance.
I. INTRODUCTION
With the advent of power electronics devices, electronic
based domestic appliances have substantially added to the ever
increasing harmonic pollution of the ac mains. Rapid
proliferation and penetration of thyristor/diode rectifiers with
inductive and capacitive loads, non- linear in nature introduces
current harmonics and reactive power in the distribution grid.
Incessant flow of harmonic current through elements of the
protection network and feeders generates [1]. Reactive power
(due to fluorescent lights, elevator motors, and refrigerators)
and higher order harmonic levels at the end users leads to
torque pulsations in motors, poor power factor, disturbances to
the domestic electronic gadgets and is detrimental to other
various loads fed from the same point of common coupling
978-1-4673-8888-7/16/$31.00 2016 IEEE.
[2].
Shunt Active Power Filter (SAPF) is a viable alternative to
comprehensively boost harmonic injection at point of common
coupling so that the spatial-temporal coherence (phase
difference) between the line voltages and corresponding
currents is achieved [3]-[5].Many approaches have been
conceptualized to design an effective current controller to
generate switching sequence for the inverter. Some previous
works focused on sliding mode control in [6], repetitive
control [7], and resonant control [8]. FPGA based control
schemes have been implemented in [9] which enhances
controller performance by introducing parallel processing
architecture.
This paper deals with servo, regulatory and compensation
performance of a shunt APF system with FPGA based dc link
voltage PI controller tuned using IPSO and PSO using
hardware co-simulation. The performance of the system is
assessed under different operating conditions thereby
evaluating the performance of IPSO and PSO tuned controller
parameters. These parameters are evaluated using the
objective function offline. Section II is dedicated to the design
of mathematical framework of the SAPF. Design of the APF
control system is also discussed in this section. Section III
encapsulates the simulation studies for an actual APF system.
II. DESIGN OF SHUNT ACTIVE POWER FILTER
A. Mathematical Framework for Reference Current
Extraction
Instantaneous source voltage and current of the shunt
active power filter system can be represented by:
vs (t ) = Vmax sin t (1)
is (t ) = iL (t ) ic (t ) (2)
Using the same methodology as in [5], the real power (due
to fundamental component) absorbed is given by:
 p f (t ) = Vmax I1 sin 2 t * cos 1 = vs (t ) * is (t ) (3) algorithm, we obtain kp=8.2 and ki=12.5.The transfer function
of the PI controller is framed as:
Ideally, the source current is (t ) should have a perfect k
sinusoidal waveform to be in the same phase as the source CPI ( s) = k p + i (11)
s
voltage. The compensated three phase source current is
expressed as TABLE I
*
p f (t ) Algorithm: Pseudo code of Improved PSO algorithm
isa (t ) = = I1 cos 1 sin t = I max sin t (4) 1: initialize Swarm
v s (t )
2: locate Leader
The other two phase currents can be expressed as:
3: generation=0
*
isb = I max sin(t 120 ) (5) 4: while generation < max Generations do
*
isc = I max sin(t + 120 ) (6) 5: for each particle do
6: update Position //flight (Formula 9 )
The value of I max i.e. the reference current is calculated by 7: evaluation
the proper regulation of DC link capacitor voltage by 8: end for
employing either a PI or PID controller. 9: update Leader
B. DC Link Voltage Regulation 10: generation ++
11: end while
Stringent regulation of the DC link capacitor voltage is an
essential requirement of the APF system. In steady state
operation of a non-linear loaded system, the utility supplies TABLE II
the systems loss and the fundamental component of load PSO PARAMETERS
current. The harmonic load current components are provided Parameter Value
by APF. Due to load disturbances, the DC link voltage No. of particles 50
fluctuates due to its charging/discharging to provide the No. of trials (Nt) 100
Maximum inertia
necessary load requirements. The DC link voltage is weight (wmax)
0.9
maintained at the desired level when the filter losses are made Minimum inertia
equal to the controlled active power flowing inside the filter 0.2
weight (wmin)
system. Learning factor (=) 2
In order to regulate DC link voltage and eventually The block diagram for the Hardware Co-Simulation based
calculate the reference current, an improved PSO based PI FPGA implementation of the APF system has been shown in
controller has been developed and its performance compared Fig. 1. The cost estimator calculates the minimum value of
with conventional PSO-PI controller. The improved PSO cost function to obtain optimal value of Kp and Ki as defined in
increases convergence rate and can be used in solving multi (11).
modal problems. The pseudo code for this algorithm is given t
in Table 1.Table II tabulates the parameters for conventional J = te ( t ) (12)
PSO. The equations for the conventional PSO are: 0
vik +1 = vik + r1 ( pik xik ) + r2 ( pgbest xik ) (7)
D. Hardware-Co Simulation of APF with FPGA
xik +1 = xik + vik +1 (8) Hardware co-simulation is being used in the industry to
Using the above algorithm, we get kp=7 and ki=23. design different control systems algorithms for complex
C. Improved PSO embedded systems without designing the actual hardware
prototype in real time. Actuating signals from the prototype.
The improved PSO neglects each particles best position Actuating signals from the controller are converted into
and considers only global best position, while the algorithm physical signals and sent to the plant model. FPGA Spartan3E
remains the same. This leads to greater diversity amongst the kit is connected to the PC via a Joint Test Action Group
solutions. The simplified equations for the ith particles (JTAG) which provides communication link between the plant
position after k+1th iteration are given as: model and FPGA. FPGA based dc link voltage and hysteresis
xik +1 = (1 ) xik + pgbest + (9) current controller designed for the APF system in HIL
where, decreases the randomness after successive iterations simulation can be utilized alongwith the actual hardware after
and can be defined as: complete testing. It achieves rapid prototyping of FPGA based
controller for APF system. The Spartan 3E kit used further
= 0 e t (0 < <1) helps reduce cost and programming complexity. Parallel flash
and memory, low cost per logic gate further eases implementation
0.5 < 0 < 1 (10) on a large scale. A detailed description of FPGA
where, depends on scale of each variable. Value of =0.5, implementation using hardware co-simulation for solar array
=0.5 and 0=0.8 are taken for the present study. Using this simulator is given in [10].
 APF SIMULINK Model

es1 Zs is(t) iL(t)

es2 Non- L
n Linear
es3 Load R
ic(t) Zf PWM-VSI

Unit Current
Vector
Cdc

isaref
isbref Hysteresis Driver
iscref Multiplier Current Circuit
Controller
Imax
Vdc_ref XSG based APF
Cost PI
- Controller Developed in
Estimator Controller
Vdc MATLAB/SIMULINK

Fig. 1 Hardware Co-Simulation of APF using FPGA based Spartan 3E development board

III. REAL TIME SIMULATION VALIDATION using Spartan-3E development board. This helps to reduce
space and time complexity of the controller and results in
The performance of the control schemes are validated
rapid prototyping of the desired model.
through simulation studies performed in the
MATLAB/SIMULINK environment. A. Startup and Nominal Response
TABLE III The starting up procedure of dc link voltage was tested
APF SYSTEM PARAMETERS [5] as shown in Fig. 2 (a). The capacitor voltage reaches the
System parameters Value
reference value of 500V within a short span of 0.26 sec with
Source voltage (L-L) 440V IPSO tuned PI controller, whereas the conventional PSO-PI
Source frequency (f) 50 Hz controller exhibits a large overshoot. The six pulse diode
Source resistor (RS) 1 rectifier based load current or the source current before
Source inductor (LS) 0.1mH compensation network is setup is shown in Fig. 2 (b). The
Filter resistor (RF) 0.015
reference currents with peak amplitude of 60A are generated
Filter inductor (LF) 0.9mH
DC-Bus Capacitor using multipliers from the XSG toolset which computes the
2100 product of unit sine vector and max reference current. The
(CDC)
Non-linear Load:
6 compensation currents are depicted in Fig. 2 (c). These
Diode rectifier reference currents are compared with the actual source
Load resistor (RL) 20
Load inductor (LL) 100mH
current to generate the switching pulses for the PWM-VSI.
The 3 phase APF system is composed of a PWM VSI
with IGBTs as the switching device, a dc link capacitor,
filter current compensation control system and switching
pulses generator for each of the 6 IGBT switches. The shunt
APF system parameters are tabulated in Table III.
Different operating regimes are considered in simulation
studies which helps verify the dynamic performance of the
system in the presence of an actual FPGA controller built
using Xilinx System Generator (XSG). Hardware co-
simulation allows the user to verify the performance of the
model in a real time simulation environment. After
verification, the actual hardware performance can be
estimated based on the performance of controller during
hardware co-simulation. The control algorithm of the PSO- (a)
PI and IPSO-PI is realized with the help of Xilinx blocks
 based APF system was 4.98% whereas for the IPSO-PI
tuned controller was 3.34%.
B. Load Disturbance Response
In any practical operating scenario the APF integrated
power grid would be subjected to different load transients
thereby varying the output power demand. Under such
conditions it is necessary to regulate the dc bus voltage at
the nominal value and ensure reliable and efficient

(b)
120
80
40
0
-40
-80
-120
120
80
40
0
-40
(a)
-80
-120

120
80
40
0
-40
-80
-120
1 1.02 1.04 1.06 1.08 1.10
Time(sec)

(c)

(b)

(d)
Fig.2 (a) Startup response of dc link voltage, (b). Load current before
compensation (c). Compensation Current from APF network and (d)
Source current after compensation
(c)
The nearly sinusoidal source current after compensation Fig. 3 Load transient response for (a) source current and on (b).Connecting
is shown in 2. (d). THD content for PSO-PI tuned controller load and (c) Disconnecting load on DC link voltage
performance of the APF system. Fig.3 (a) shows the
transient response of source current when a nonlinear load
consisting of series resistance of 30 and parallel inductor
of 200 mH was connected at t=4 sec and later disconnected
at t=4.4 sec. The IPSO-PI based dc link voltage controller
settles back to its nominal voltage within an extremely short
time period of ts=0.36 sec as evident in Fig.3 (b). Similarly,
in Fig. 3 (c), at t= 4.4 sec, the load was disconnected leading
to a sudden decrement in the source current while the PSO
tuned PI controller shows larger overshoot whereas the
IPSO-PI controller ensures continuous operation around the
nominal operating point. Quick settling time and minimum
overshoot/undershoot validates superior performance of the
proposed IPSO-PI controller.
C. Set-point Change Response
570
560
ts=0.60 sec
550
540
530
520
510
PSO-PI
500 IPSO-PI
490
7.0 7.5 8.0 8.5 9.0 9.5
Time(sec)
(a)
(b)
Fig.4 DC link voltage for (a) Step up and (b) Step down change in
reference voltage
In order to validate the effectiveness of the IPSO tuned
PI controller, the magnitude of the desired dc bus voltage
was varied. The transient response of dc link voltage was
recorded at step up and step down variation. Fig. 4 (a)
exhibits the transient response for step up change in dc link
voltage from nominal voltage of 500V to 550V at t=8 sec.
The minimal overshoot and quick recovery of the set-point
is visible. The settling time is equal to 0.60 sec which is
marginally smaller than the PSO-PI controller. Similarly,
fig.4 (b) shows the dc link voltage response when the
reference voltage is decreased in a step manner from 500V
to 450V at t=10.4 sec. Fast settling time is the primary merit
of the proposed controller.
IV. CONCLUSIONS
The present paper dealt with development of hardware
co-simulation of a shunt active power filter with FPGA
based PI controller tuned using conventional PSO and
Improved PSO. ITAE was taken as the objective function to
be minimized. The proposed controller was employed as a
dc link voltage regulator along with a fixed frequency
hysteresis current controller which generates the switching
signals for the PWM Voltage source inverter supplying the
compensation current. The performance of both PSO-PI and
IPSO-PI controller was tested under different dynamic
conditions of voltage reference change and load transients.
Simulation studies showed that the servo and regulatory
performance of the proposed IPSO-PI controller conjoined
with HCC was found to be satisfactory and in agreement
with IEEE-519 standards.
ACKNOWLEDGEMENT
This work was supported by Board of Research in Nuclear
Sciences (BRNS), Department of Atomic Energy, Govt. of
India, under the grant no: 34/14/53/2014-BRNS.
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