Computer Arithmetic

By: Batu, Michelle C., Plaza, Bernard

• The Arithmetic and Logic Unit

ALU –Performs arithmetic and logical operations on data

-Does the calculations

-Everything else in the computer is there to service this unit

-Handles integers

• Integer Representation

 Only have 0 & 1 to represent everything

 Positive numbers stored in binary

◦ e.g. 41=00101001

 No minus sign

 No period

 How to represent negative number

◦ Sign-Magnitude

◦ Two’s complement
 SIGN-MAGNITUDE REPRESENTATION

 Left most bit is sign bit

 0 means positive

 1 means negative

 +18 = 00010010

 -18 = 10010010

 Problems

 Need to consider both sign and magnitude in arithmetic

 Two representations of zero (+0 and -0)

****sign-magnitude representation is rarely used in implementing the integer portion of the ALU.

TWO’S COMPLEMENT REPRESENTATION

 Similar to sign magnitude, twos complement representation uses the most significant bit as a
sign bit.

 Converting between Different Bit Lengths

◦ the rule for twos complement integers is to move the sign bit to the leftmost position
and fill in with copies of the sign bit. For positive numbers, fill in with zeros, and for
negative numbers, fill in with ones. This is called sign extension.

Fixed-Point Representation

 Representations discussed in this section are sometimes referred to as fixed point. This is
because the radix point (binary point) is fixed and assumed to be the right of the rightmost digit.
• Integer Arithmetic

• This section examines common arithmetic functions on numbers in twos complement

representation

1.) NEGATION
• Take Boolean complement of each bit, I.e. each 1 to 0, and each 0 to 1.

• Add 1 to the result

• E.g. +3 = 011

• Bitwise complement = 100

• Add 1

• = 101

• = -3

Negation Special Case 1

 0= 00000000

 Bitwise not 11111111

 Add 1 to LSB +1

 Result 1 00000000

 carry out of the most significant bit position is ignored, so:

 - 0 = 0 OK!

Negation Special Case 2

 128 = 10000000

 bitwise not 01111111

 Add 1 to LSB +1

 Result 10000000

 So:

 -(-128) = -128 NO OK!

 It should change during negation

  >> There is no representation of +128 in this case. (no +2 n)

2.) ADDITION AND SUBTRACTION

• Monitor sign bit for overflow (sign bit change as adding two positive numbers or two
negative numbers.)

• Subtraction: Take twos compliment of subtrahend then add to minuend

• i.e. a - b = a + (-b)

• So we only need addition and complement circuits

Geometric Depiction of
Two Complement
Integer
Hardware for
Addition and
Subtraction
3.) MULTIPLICATION
 Complex operation, whether performed in hardware or software
 Variety of algorithms are used in computers

Unsigned Integer

-- Long-hand multiplication is used.

 Making a Computerized Multiplication more Efficient
 Perform a running addition on the partial products rather than waiting until the end. This
eliminates the need for storage of all the products; fewer registers are needed
 We can save some time on the generation of partial products. For each 1 on the multiplier,
an add and a shift operation are required; but for each 0, only a shift is required.

Figure:
 Multiplier and multiplicand are loaded into two registers (Q and M). A third register, the A
register, is also needed and is initially set to 0. There is also a 1-bit C register, initialized to 0,
which holds a potential carry bit resulting from addition.

Multiplier operation
Twos Complement Multiplication

 Convert both multiplier and multiplicand to positive numbers, perform the multiplication,
and then take the twos complement of the result if and only if the sign of the two original
differed.

Booth’s Algorithm

- Has the benefit of speeding up the multiplication process, relative to a more straightforward
approach.

Arithmetic Shift – Preserve the sign of the number in A and Q.

Example of Booth’s Algorithm

 4.) DIVISION
 More complex than multiplication but based on the same general
principles.

Division with Negative Numbers (Approach for Twos Complement Numbers)

1.) Load the divisor into the M register and the dividend into the A, Q register. The dividend must
be expressed as a 2n-bit twos complement number. (e.g. the 4-bit 0111 becomes 00000111, and
1001 becomes 11111101.
2.) Shift A, Q left 1 bit position.
3.) If M and A have the same signs, perform A  A – M; otherwise, A  A + M.
4.) The preceding operation is successful if the sign of A is the same before and after the operation.
a. If the operation is successful or A = 0, then set Q 0  1.
b. If the operation is unsuccessful and A =! 0, then set Q 0  0 and restore the previous
value of A.
c. Repeat steps 2 through 4 as many times as there are bit positions in Q.
d. The remainder is in A. If the signs of the divisor and dividend were the same, then the
quotient is in Q; otherwise, the correct quotient is the twos complement of Q.
9.4 FLOATING POINT REPRESENTATION

PRINCIPLES
Fixed Point Representation represents a range of positive and negative integers by assuming a
fixed binary or radix point. This also allows the representation of numbers w/ a fractional component.
But it cannot represent very large numbers, nor can very small fraction. Same manner w/ scientific
notation one can overcome this limitation by representing binary floating-point numbers in the form:
± S x B±E
; where B is the base w/c is same for all numbers and need not to be stored. Therefore this can be
stored in a binary word w/ 3 fields:
1. sign: plus (0) or minus (1)
2. Significand (S) also called Mantissa is the final portion of the word.
3. Exponent (E).
To simplify operations w/c is shifting the radix point to the right of the leftmost 1 bit and
adjusting the exponent accordingly into normalize nonzero number (one in w/c the most significant
digit of the significand is nonzero or in binary is 1) of the form:
± 1.bbb…b x 2 ± E
is required, where b is either one or zero.

Note the following features:

1.The sign is stored in the first bit of the word.
2. The first bit of the true significant is always 1 and need not be stored in the significant field.
3. The value 127 is added to the true exponent to be stored in the exponent field.
4. The base is 2.

Possible ranges of numbers:

1. Negative numbers between - (2 - 2-23) x 2128 and -2-127
2. Positive numbers between 2-123 and (2 – 2-23) x 2128

Five regions of the number line are not included in these ranges:
1. Negative numbers less than -(2 - 2-23) x 2128, called negative overflow
2.Negative numbers greater than 2-127, called negative underflow.
3. Zero
4.Positive number less than 2-127, called positive underflow
5 Positive numbers greater than (2 - 2 -23) x 2128, called positive overflow
 Overflow occurs in a magnitude greater than can be expressed with an exponent of 128.
Underflow occurs when the fractional magnitude is too small and sometimes approximated by 0. The
maximum number of different values that can be represented with 32 bits is still 2 32.
The numbers in floating-point notation get closer to the origin and farther apart as you move
away (shown in figure9.20). In figure 9.18, we expand the range of expressible numbers if we increase
the numbers of bits in the exponent but reduce the density of those numbers and therefore the
precision. The only way to increase both range and precision is to use more bits.

The advantage of using larger exponent is that a greater range can be achieved for the same number of
exponent bits.

IEEE Standard for Binary Floating-Point Representation

The most important floating-point is defined in IEEE Standard 754 [IEEE85]. This standard was
developed to facilitate the probability of programs from one processor to another and to encourage the
development of sophisticated, numerically oriented programs. The standard has been widely adopted
and is on virtually all contemporary processors and arithmetic coprocessors.
Following classes of numbers that represent special values:

1. The normalized number of single biased (-126 through +127) and double biased format (-1022
through +1023) gives an effective 24-bit or 53-bit significand (called fraction in the standard).
2. A combination of a zero exponent and a zero fraction represents ± zero depending on the sign
bit.
3. An exponent of all ones w/ a fraction of zero represents positive or negative infinity,
depending on the sign bit.
4. An exponent of zero together w/ a nonzero fraction represents a denormalized number.
5. An exponent of all ones together w/ a nonzero fraction is given the value NaN, w/c means
not a number, and is used to signal various exception conditions.
9.5 FLOATING-PORT ARITHMETIC

Figure 9.5 summarize the basic operations for floating-point arithmetic.

A floating point may produce one of these conditions:

Addition and Subtraction

Addition and subtraction are more complex than multiplication and division since they need
alignment. Below are the 4 Basic Phases of Algorithm for Addition and Subtraction:
1. Check for zeros - We begin the process by changing the sign of the subtrahend if it is a
subtract operation. And if either operand is 0 the other is reported as the
result.
2. Align the significands - Achieved by repeatedly shifting the magnitude portion of the
sinificand right 1 digit and incrementing the exponent until the exponent are
equal. 3. Add and subtract the significands – the two
significands are added together. 4.
Normalize the result – the final phase is normalizing the results.

Figure 9.22 shows the flowchart of step-by-step function required for floating addition and subtraction.
The two operands must be transferred to registers that will be used by the ALU. If the floating-point
includes an implicit significant bit, that must be made implicit for the operation. Below is an example.
Multiplication and Division
In multiplication, zero operands give 0 results. We add the exponent if it is stored
in bias form the sum would have double the bias. Thus the bias value must be subtracted
from the sum. The ending result could be an exponent overflow or underflow.
If the exponent of the product is within the proper range, we multiply the
significands taking into account their signs. The product will be double the length of the
multiplier and multiplicand. The extra bits will be lost during rounding.
The final answer is then normalized and rounded, that could result into
exponential underflow. The whole process found at the flow chart below figure 9.23.
Now let us consider division. We first test for 0. If the divisor is 0, it would
appear as an error. A dividend of 0 results in 0. Next, the divisor exponent is subtracted
from the dividend exponent. This removes the bias, w/c must be added back in. Tests are
then made for exponent underflow or overflow.
The next step is to divide the significands. This is followed with the usual
normalization and rounding. Refer to figure 9.24 the flowchart for division.
Precision Considerations

A. Guard Bits
Guard bit are additional bits in the registrar w/c are used to pad out the right end
of the significand with 0s.

B. Rounding
Rounding policy affects the precision of the results, storing in longer register and
putting it back into the floating-point formal may result to extra bits disposition.

IEEE standard lists four alternative approaches:

 Rounding to nearest is the rounding mode listed in the standard and is defined
as follows:
The representable value nearest to the infinitely precise result shall be delivered;
if two nearest representable values are equally near, the one w/ its least significant bit
shall be delivered.
Rounding to plus and minus infinity are useful in interval arithmetic. This
technique provides an efficient method for monitoring and controlling errors in floating
point computation by producing two values for each result. The width of the intervals or
the difference between the upper and lower endpoints determines the accuracy of the
result. Then the interval endpoints are rounded down or up.
Round to zero simply ignored the extra bits, therefore the truncated value is
always less than or equal to the more precise original value.

IEEE Standard for Binary Floating-Point Arithmetic

A. Infinity
Infinity arithmetic is treated as the limiting case of real arithmetic, with the
infinity values given the following interpretation:
-∞< (every finite number) < +∞
Arithmetic operation involving infinity:

B. Quiet and Signaling NaNs

A NaN is a symbolic entity in floating-point format, of w/c there are 2 types:
signaling and quiet. Signaling affords values for uninitialized variables and arithmetic-
like enhancements that are not the subject of the standard. A quiet on the other hand
propagates through almost every arithmetic operation without signaling an exception. See
table 9.6.
C. Denormalized Numbers
Denormalized numbers are included in IEEE 754 to handle cases of exponent
underflows. When the exponent of the result becomes too small, the result is demoralized
by right shifting the fraction and incrementing the exponent for each shift, until the
exponent is within a representable range. The use of denormalized number is referred to
as gradual underflow.