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ECC-3231 Project Two-Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Amplifier
ECC-3231 Project Two-Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Amplifier
A =
C
2
v =
s
1
(15 )(33 )
=
D
1
C
2
When VDS = 0
For linear amplification, the MOSFET has to operate in the
saturation region. The current through the drain and source in
saturation region is calculated as shown below. =
15
= 12 ( )( )2 = = 1.2
2.6 + 9.8
+
equation: =
DC Load Line
open the gate above the threshold voltage; therefore:
1.5
1 2
= (600 ) (3 1.4 ) = 768
IDS(mA)
1
2
2
= =
15 7.5
= 9.8 0 5 10 15 20
768 VDS (volts)
2
= = = 2.6 Fig. 3 DC Load Line Graph
768
III. AC ANALYSIS
The power consumption was calculated using the following
formula, which was under the requirement specification. A. AC Equivalent
In this step, the voltage gain of the amplifier circuit was
= ( +
) calculated. The original circuit shown in Fig. 2 was
transformed into a hybrid PI equivalent circuit to perform
1
the analysis. The model can be found in Fig 4.
15 5
= 15 (768 +
) = 1.38
66
200
= = = 260.4
4
7.68 10
66 33
1 2
= = = 22
1 + 2 66 + 33
9.8 260
= = = 9.4
(( )) = = 6.6
B. DC Load Line +
= 6.6
= = ( ( ) = 9.6 10 4 6.6
= 6.336
3
A. DC Analysis
B. AC Load Line A simulation was run to obtain the DC currents and
voltages. The schematic with the simulated DC currents and
Observed from reference 1, the equations to perform the voltages is shown in figure 7. The currents and voltages were
AC load line analysis were: found to be within the acceptable percent error from the
=+ ( )
calculated values.
4
= 5.5 + 7.60 10 (6.6 ) = 10.516
5.5
=+ = 7.60 104 +
( )
6.6
= 1.6
AC Load Line
2 0, 1.6
IDS(mA)
1.5
1 y = -0.1524x + 1.6 Fig. 7 PSpice Simulated DC Currents and Voltages
between the calculated and simulated gain was 1.19%. Fig. 12 Output Impedance vs. Frequency
The phase vs. frequency plot is shown in figure 10. This Table 2. Percent Error Calculations between Hand-calculated
plot shows the phase shift differences across the gain region of and Simulated Values
the amplifier. Measurement Hand PSpice % Error
calculations
Gain -6.16 -6.26 1.62
Rin 22 k 22 k 0
Rout 9.44 k 9.8 k 3.81
C. Transient Analysis
For the transient analysis the input signal was set to 1 V
peak-to-peak. The output voltage was found to be 6.16 V
peak-to-peak. The waveform show that the amplifier was
Fig. 10 Phase vs. Frequency providing a linear amplification with no clipping on the
output.
The input impedance is the voltage divider equivalent
resistance looking at the gate and is calculated as follow:
(66 )(33 )
= 1 2
= = 22
(66 ) + (33 )
1 +2
| |
V. RESULTS
200
Where = = = 260
768
The circuit shown in Fig 2 was constructed. The signal
source was replaced by sinusoidal source. The source was set
Therefore, = 9.44
up with the amplitude of 800 mV peak-to-peak. The frequency
was at 1 kHz. Because a 9.8 k resistor (R D) was not
The plots of the input and output impedances versus available, a 10 k resistor was used instead. The circuit was
frequency are shown in figures 11 and 12, respectively. Input carefully inspected before the power supply was turned on.
impedance increases as frequency decreases because of the The following measurements were obtained.
low pass filter. The output impedance also increases as the Voltage Gain:
frequency decreases due to the RC time constant on the output. The voltage gain of the amplifier circuit was recorded and
shown below:
The above figure has shown that the voltage gain of the
amplifier was met the designs specification. Which was,
5.1mV/840 mV = 6.07 V.
Signals swing:
5
The amplitude of the signals swing can be seen from Fig 14. VG 5 4.87 2.60
It was indicated the signal successfully swing from a -2.71 V VGS 3 2.73 9.00
to a 2.44 V. From the experiment, it was observed that the
swing of the signal was approximately symmetric. IDS(mA) 0.768 0.77 0.26
Rin(K) 22 25 13.64
Input Resistance: Rout(K) 9.6 10.4 8.33
To calculate the input resistance, the circuit shown in Fig 2 Gain 6.33 6.07 4.11
was modified. A coupling capacitor and a 1K resistor were
added to the gate terminal of the MOSFET. The set up can be Discrepancies:
found in the below figure: From the above table, the results were within the expected
percent error. The gain of the amplifier circuit was
successfully archived within a 5 % error. The other parameters
were off by almost a 10 % error. This happened because the
resistor RD used in the lab was 10 k instead of 9.8 k. Also,
the Kn factor of the MOSFET were different from the
manufacture.
=
1.05 1.01
= 4 105 . Thus, the input resistance the circuit. Thus, a small capacitor value (1F) was selected to
1
The result from the lab session has shown that the
Output Resistance: symmetrical swing of the signal was not observed. In the
future design, the designer should add a negative rail power
supply to the transistor. This can help to improve the
symmetry of the signals swing.
VII. CONCLUSION
The objectives of this project were met. The gain of the
amplifier circuit was measured to be 6.07. The signal was able
to have a 5 V peak-to-peak swing. The power consumption
was less than 75 mW. The measurement results have shown
Fig 16. Output Resistance Measurement Setup that VD = 7.7V, this yielded a 2.67% of difference from the
initial assumption. VDS was measured to be a 5.02 V, which
A 1 k resistor and a 0.1 F coupling capacitor were added was matched to the assumption. The source voltage Vs was
to the drain terminal of the MOSFET amplifier circuit. The measured to be 2.14 V, which was within the expected error of
voltage Vout was measure to be 0.94 V. Then, the output 7%. In general, most of the assumptions that were made to
current was calculated as, =
=
1.03 0.94