AML6210DPA/VProcessorUserGuideVersion0.

AML6210DPA/VProcessor

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UsersGuide

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AMLOGIC,Inc.
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3930FreedomCircle
SantaClara,CA95054
U.S.A.
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www.amlogic.com
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AMLOGICreservestherighttochangeanyinformationdescribedhereinatanytimewithoutnotice.
AMLOGICassumesnoresponsibilityorliabilityfromuseofsuchinformation.

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TableofContents
1 INTRODUCTION..............................................................................................................................................................4
2 FEATURES ........................................................................................................................................................................5
3 EXTERNALINTERFACES ..............................................................................................................................................7
3.1 GLOBALCONFIGURATIONS................................................................................................................................................................. 7
3.1.1 PowerOnConfiguration........................................................................................................................................................... 7
3.1.2 Clocks................................................................................................................................................................................................. 7

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3.1.3 JTAGforSoftwareDevelopment............................................................................................................................................ 8

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3.1.4 GPIOs.................................................................................................................................................................................................. 8
3.2 MEMORYINTERFACES ......................................................................................................................................................................10
3.2.1 SDRAMInterfaces ......................................................................................................................................................................10

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3.2.2 FLASHInterface..........................................................................................................................................................................10
3.2.3 NANDFLASHInterface............................................................................................................................................................10
3.3 AUDIOINTERFACES ...........................................................................................................................................................................12
3.4 VIDEOOUTPUTINTERFACES ...........................................................................................................................................................13

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3.4.1 DigitalVideoOutput.................................................................................................................................................................13

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3.4.2 LCDTimingController.............................................................................................................................................................13
3.5 PERIPHERALS .....................................................................................................................................................................................14
3.5.1 CardReaderInterface .............................................................................................................................................................14
3.5.2 USBInterface ...............................................................................................................................................................................14
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4 OPERATINGCONDITIONS ........................................................................................................................................ 15
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4.1 DCCHARACTERISTICS ......................................................................................................................................................................15
4.2 ABSOLUTEMAXIMUMRATINGS ......................................................................................................................................................15
4.3 RECOMMENDEDOPERATINGCONDITIONS....................................................................................................................................15
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5 PINOUT ......................................................................................................................................................................... 16
5.1 PACKAGEPINOUTDIAGRAM ...........................................................................................................................................................20
5.2 MULTIPLEFUNCTIONPINS ...............................................................................................................................................................21
5.2.1 CardReaderinterfacemultifunctionpins.....................................................................................................................21
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5.2.2 TCONMultiFunctionPins .....................................................................................................................................................21

5.2.3 JTAGinterfacemultifunctionpins.....................................................................................................................................21
5.2.4 FLASHandm1_*interfacemultifunctionpins............................................................................................................22
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6 MECHANICALSPECIFICATIONS .............................................................................................................................. 24
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RevisionHistory

Revision Revised By Changes
Number Date
0.1 2008/3/3 bwester Initial release
0.2 2008/3/3 Bwester Fix some errors in diagram and text
0.3 2009/2/13 J Z Revise pin description

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0.4 2010/03/25 J Z Revise content

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1 Introduction
TheAML6210DPA/Vprocessorisacompleteintegratedsystemtargetingthedigitalpictureframemarket.
ThedevicecombinesasuperfastJPEGdecoder,alldigitalLCDdrivers/TCONsignals,USBandcardreader
I/Osanda32bithostCPUinasmall144pinpackage.

Theembedded32bitscoreCPUhandlesallsystemrelatedapplicationsoftware.ItexecutesAVOS,thebase
operatingsystemforAML6210DP.AllapplicationsanddriversrunontopofAVOS.DriversincludingUSB

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drivers,cardreaderhardwaredriver,andvideoandotherhardwarerelatedprogramminginterfacesare

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providedbyAVOS.Applicationsincludegraphicaluserinterfacesandfilesystemsubsystemarealso
included.Developerscanaddadditionalapplicationstocustomizeforeachplatform.

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ThecoreCPUinterfacestothevideoandaudioprocessinghardware.Itperformsadvanceddigitalaudio
decoding.Itprovidessupportforallexistingaudioformatsanditalsohasenoughflexibilitytoaccommodate
newaudiostandards.PopularaudioformatslikeMPEGLayerI/II/III,LPCM,MP3,WMA,AACandWAVcan
besupported.

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JPEGpicturesareprocessedbydedicatedpicturedecodinghardwareandtheflexiblePictureAMRISCTM

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engine.ThehardwareandmicrocodecombinationiscapableofdecodingJPEGpictureswithnolimitsin
pictureresolution.Oncedecoded,theoutputpicturesarepassedtoasophisticatedvideosubsystemthat
performsimageanalysis,enhancementandscalingfunctions.Contrastenhancement,hueadjustment,video
scaling,videointerpolation,andzoomarealsosupported.Thehighresolutionscalarsupportsbothup
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scalinganddownscalingofimagesandvideo.ThescalarcanalsomixinmultiplegraphicsandOSDlayersfor
thefinaldisplay.TheintegratedvideoencodersupportsalldigitalLCDpanelresolutionsthrutheonchip
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triplepanelDACs.Inaddition,aprogrammabledigitalLCDTCONisincludedfortheAML6210DPtointerface
todigitalLCDpanelsdirectly.

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TheAML6210DPalsointegratedaUSB2.0HighSpeedOTGcontroller/PHYandcardreadercontroller.The
cardreadercontrollercansupportSD/SDHC,MS/MSPro/MSDuo/MSProDuo,MMC,xDandCFcards.FAT
andFAT32filesystemsaresupported.TheUSBcontrollercanbeconnectedtoUSBharddisk,FLASHdrive,
digitalcamerasandMP3players.TheAVOSdriversandapplicationsforAML6210DPfirmwareincludesthe
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basicUSBdevicedriver,USBprotocolstackstosupportbulkandINTRtransfer,Hub,MassStorage(MS)class
andPictureTransferProtocol(PTP).TheAVOSUSBfirmwarealsosupportsmultiplefilesystemsand
includesflexiblefiletransferfunctionsbetweenUSBdevices.

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AML6210DPA/Vprocessorhasasetofveryflexibleclockingcircuitsthatimplementtheadaptive
AMPOWERIIpowerreductionalgorithms.ThechipworksinconjunctionwiththeAVOSsoftwaretoreduce
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totalpowerconsumptionbasedonprocessingload,typeofmediastreamsbeingprocessedandtheoutput
requirements.WithAMPOWERII,thesystemcanreducepowerconsumptionforportableapplicationsand
helpsconsumerelectronicstoachievetheEnergyStarrating.Inaddition,AMPOWERIIalsoprovideshigher
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performancewithinsmaller,thermallyconstrainedenvironments.

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2 Features
TheAML6210DPchipisveryflexibleandmostofthecapabilitiesareunderfirmwarecontrol.Thefollowing
listoffeaturesmayormaynotbeincludedinthefirmwarelibraryorbinary,dependingontheactual
applicationandplatform.

HighIntegration
o Embedded32bitscoreRISCprocessorforsystemcontrol

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o CompleteJPEGdecodinglogicandvideoscalinglogic

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o CompleteaudiodecodingandstereoaudioDACs
o IntegrateddigitalLCDvideosignalsandTCON
o IntegratedUSB2.0HighSpeedOTGport

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o Integratedcardreadercontrollers
o IntegratedNANDFLASHcontroller

JPEGDecoding

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o SuperfasthardwaredecodingofJPEGpicture
o Unlimitedpixelresolution(currentlytestwith16Mpixelpictures)

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o Supportsscaling(zoominorout),rotationandtransitioneffects
o Automaticimageanalysisandenhancement

OtherImages/PicturesDecoding
o DecodesBMP,PNG,GIF,TIFFandotherpopularpictureformats
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o Supportszoominandout,rotationandtransitioneffects
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SpecialTrickModes:
o Pause
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o Reverseplayback
o Multiplestepsfastforward/backward

PictureProcessing
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o Automaticimageanalysisandenhancement
o Variablestepspicturezooming(upto8x)
o OnScreenDisplay(OSD)capableofsupporting4/16/256colorsorTrueColor
o OSDalphablendingovervideodisplay
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TVEncoder/TCON
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o DigitalvideooutputsignalsespeciallyfordigitalLCDpanels
o Programmabletint,brightnessandotherTVenhancements
o Integratedprogrammabletimingcontroller(TCON)fordigitalLCDpanels
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Graphics
o Graphicscanbescaledindependentlyofthevideooutput
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o Unifiedgraphicsmemoryarchitectureformaximumflexibilityandsystemcostsavings

AudioDecoding
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o FullMPEGaudiolayersI,IIandIII
o Capableofdecodingpopularaudioformatsincluding:MP3,WMAandWAV

AudioPostProcessingandOutput
o Integrateda2channelaudioDACs
o Muting,volumecontrol,etc.

USBInterface
o IntegratedOTG2.0HighSpeedcontrollerandPHY
o BackwardcompatiblewithUSB1.1devices
o USBOTGportcanbeconfiguredasUSBdevice,hostorOTGport
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o DMAsupportfordatamovementforBULK,INTRandISOtransfer
o USBdevicedriver,nativeUSBprotocolstacksupportedinAVOSfirmware
o IntegratedsupportforMassstorageclass(MSClass)andPictureTransferProtocol(PTP)
o USBHubsupport
o Video,audioandimagedecodingfromUSBattachedMSClassorPTPdevices
o ConnectingtoPCsorApplecomputersasUSBMSClassdevices

CardReaderInterfacesandControllers
o SupportMS,SD/SDHC,MMC,andxDmemorycardformats

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o Supportsreadingandplaybackofaudioandpicturemultimediafiles
o AVOSsoftwaresupportsallfileoperationsviafilesystemoneachmemorycard

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CoreCPUSubsystem
o 32bitcoreCPUdedicatedforuserapplications

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o EmbeddeddebuginterfaceusingICE/JTAG
o SharedMPEGSDRAMasruntimedatastorageforminimalsystemcost
o Integratedinterruptcontroller
o Integratedgeneralpurposetimersandcounters

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o IntegratedgeneralpurposeDMAcontrollers

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o Supportsupto8Mbytesof8bitFLASHchip
o SupportssingleSDRAMinterface(m1_*).TheSDRAMinterfacecansupport8Mor16M
bytesofSDRAM.

System,PeripheralsandMisc.Interfaces
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o One27MHzcrystaloscillatorforA/Vsystem
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o AMPOWERIIpowerreductionalgorithmforportabledevices
o NumerousprogrammableGPIOpinsforsystemcontrolandinterrupts
o Integratedi2cmastercontrollers,remotecontrolinputcircuitry,quadPWMoutputpins
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o 1.25voltand3.3voltpowersupplies
o 3.3voltI/Osupport
o 144pinsLQFPRoHSpackage


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3 ExternalInterfaces
3.1 GlobalConfigurations
3.1.1 PowerOnConfiguration
Thechiphasacommonactivelowresetsignalcalledreset_n.Thissignalputstheentirechipintoaknown

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statebyresettinginternalregistersandstatemachinestotheirdefaultstates.Typicallythissignalisheldlow

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foratleast100msecafterthepowerandcrystalclockisstabilized.Theresetprocessalsoplaysarolein
configuringcertainfunctionswithinthechip.Usingthestateoftheconfigurationpinsandtherisingedgeof
thereset_nsignal,theusercandictatetheconfigurationoftheJTAGpinsandthebootdevice.The

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configurationpinsshouldbepulledupordownusing10Kresistorstoeither3.3vorground.


PIN Function

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m1_a_10 This pin controls the JTAG configuration after RESET:

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Tie to 3.3v with 10k resistor for JTAG debugging
Tie to ground with a 10k resistor to use the JTAG pins as GPIO
m1_we_n This pin controls the Boot Option after RESET: h
Tie to 3.3v with 10k resistor if the boot device is NAND FLASH
Tie to ground with a 10k resistor if the boot device is NOR FLASH
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m1_dqm1 This pin controls the FLASH Data Wide after RESET:
Tie to 3.3v with 10k resistor for 16-bit FLASH device
Tie to ground with a 10k resistor for 8-bit FLASH device
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m1_cas_n This pin controls the NAND Page Size after RESET (only for NAND flash):
Tie to ground with a 10k resistor for 2048 bytes page size
Tie to 3.3v with 10k resistor for 512 bytes page size
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m1_ras_n This pin controls the NAND Flash Size after RESET. The pin controls the number of
ALE pulses that are issued to set the ROW address.
Tie to 3.3v with 10k resistor for large size NAND flash device that needs 3 ALE
pulses
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Tie to ground with a 10k resistor for small size NAND device that needs 2 ALE
pulses
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Clocks
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TheAML6210DPhasmultipleinternalclockdomains,butalltheinternalclockdomainsarederivedfroma
singleexternalreference:OSC.Asillustratedbelow,thecrystal/oscillatorpinpairs(OSCIN/OSCOUT)canbe
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connectedtoacrystalordrivenfromanexternaloscillator.InthetypicalA/Vapplication,a27MHzcrystalis
connectedtotheOSCpins.Thefollowingdiagramdepictsatypicalcrystalcircuit;theactualvaluesofthe
componentsdependonthetypeofcrystalusedintheapplication.
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OSCIN OSCIN
22pF
100k 27Mhz
OSCOUT OSCOUT NC
XTAL
27MHz 22pF

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3.1.3 JTAGforSoftwareDevelopment
TheembeddedcoreprocessorcanbecontrolledthroughitsJTAGportusingtheembeddedICEinterface.The

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embeddedICEinterfaceallowsthedevelopertodownloadcode/datatotheSDRAMmemory,proberegisters
ontheAML6210DPchip,executeanddebugtheRISCcodeusingauserfriendlydevelopmentenvironment.

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TheJTAGinterfaceisenabledbytyingm1_a_10highhighasillustratedbelow.

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TDI TDI
TMS TMS
VCC AOGPIO
TCK TCK
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TDO TDO

JTAGController

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3.1.4 GPIOs
Configurablehardwarecontrollers(e.g.i2c,cardreader,etc.)andDMAsareintegratedintotheAML6210DP
devicetospeedupthecommonoperationsandrelievethecoreRISCforuserlevelapplications.Since
hardwarecontrollersandstatemachinescannotcoverallpossibleexternaldevicesorsystemlevelsignals,
numerousgeneralpurposeI/OpinsareavailableonthechipforpurposelikePortableMediaPlayerkeypads.
EachGPIOpincanbeindependentlyconfiguredtobeaninputoranoutput.Asindicatedinthediagram,
therearevariousI/Otypes.

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GPIOPADTYPES

GPIOI/OTypeI GPIOI/OTypeO

I Readback O I/O_O
Register Register

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GPIOI/OTypeOD (Pulluprequired) GPIOI/OTypeFC (NOPulluprequired)

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Readback Readback
Register Register
I/O I/O

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I/O_O
Register

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I/O_EN I/O_EN
Register Register

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3.2 MemoryInterfaces
3.2.1 SDRAMInterfaces
TheAML6210DPdeviceusesexternalSDRAMfordatastorageandcodeexecution.TheSDRAM1interfaceis
labeledasm1_*interface.TheSDRAMinterfacecanaccessupto16Mbytesofmemory.Dependingonthe
application,166MHz4Mx16or8Mx16SDRAMchipscanbeused.Thefollowingexampledepictsasystem
with8MbytesofSDRAMonm1_*interface.

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M1_D[0..15] D[0..15]
M1_A[0..11] A[0..11]
M1_BA1 BA1
M1_BA0 BA0
M1_CLK0 CLK

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M1_RAS_n RAS#
M1_CAS_n CAS#

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M1_SCS0_n SCS#
M1_DQM0 DQML
M1_DQM1 DQMH
M1_WE_n WE#



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8Mx16SDRAM

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3.2.2 FLASHInterface
TheFLASHinterfacecanaccommodatean8bitsFLASHdevice.DuetothelimitednumberofI/Opins,the
FLASHinterfaceissharedwiththeSDRAM(m1_*)interface.Upto8MbytesofFLASHisaccessiblewiththe
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8bitswideFLASHinterfacedesign.TheFLASHshouldbeconnectedasindicatedinthefollowingdiagram:

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M1_BA1 A[17]
M1_BA0 A[16]
M1_CAS_n A[15]
M1_RAS_n A[14]
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M1_DQM1 A[13]
M1_DQM0 A[12]
M1_A[11:0] A[11:0]
M1_D[15:0] D[15:0]
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M1_WE_n WE#
FLASH_CS_n CS#
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FLASH_OE_n OE#
8bitFLASH

3.2.3 NANDFLASHInterface
TheNANDFLASHinterfacecanaccommodatean8bitsor16bitsNANDFLASHdevice.Duetothelimited
numberofI/Opins,theFLASHinterfaceissharedwiththeSDRAM(m1_*)interface.NANDFLASHhasavery

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largecapacitythatrangesfrom32MBtomorethan1GB.TheNANDFLASHshouldbeconnectedasindicated
inthefollowingdiagram:

NAND_R/nB R/B*
NAND_nRE RE*
NAND_CE CE*
NAND_nWE WE*

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M1_BA1/NAND_CLE CLE

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M1_BA0/NAND_ALE ALE

M1_D[7:0] DQ[7:0]

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8bitNANDFLASH

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3.3 AudioInterfaces
ApairofaudioDACsisprovidedintheAML6210DPdevice.TheaudioDACsaredesignedforconnectingto
smallspeakerinsidethephotoframeorearbudsforexternallistening.Asimpleexternalamplifierisneeded.
Pleaseseethefollowingsamplecircuitdiagram.

Internally,thedeltasigmaalgorithmisusedtoimprovetheperformanceandensurehighSNRoutput.The
implementationincludesamultitapinterpolationfilterwhichincreasesthesamplerateoftheaudio

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channelstothemodulatorrate.Thentheaudiostreamispassedthroughasigmadeltamodulatorthat
generatestheserialPWMdatastream.Aninternalanalogfilteristhenusedforoutofbandnoisefiltering

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andanalogsignalreconstruction.Externalamplifierisneededtoprovidethenecessarycurrenttodrivethe
speakersorheadphones.

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ADATA_0(L) R

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ADATA_1(R) AMPIFLER
Circuit

Internal
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StereoADC

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3.4 VideoOutputInterfaces
3.4.1 DigitalVideoOutput
TheAML6210DPintegratedinternalLCDvideoscalarandencoderandhighresolutiontriplepanelDACs
(PDAC)fordirectconnectiontodigitalLCDpanels.TheLCDscaleandencoderconvertthevideoimagesto
theLCDresolutionandpreparetheimagetobedisplayed.ThenspecialLCDspecificditheringlogicand
gammacorrectionalgorithmisappliedbeforethevideodataissenttothedigitalvideooutput.

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3.4.2 LCDTimingController
TheAML6210DPAVprocessorhasabuiltinLCDtimingcontroller(TCON)thatworksinconjunctionwiththe

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digitalvideooutputtoprovidethebestvideoperformanceonadigitalLCDpanel.TheTCONanddigitalvideo
outputdrivethedigitalLCDpaneldirectlywithoutanyadditionallogic.AML6210DPsTCONis
programmableandcanbeusedinanysmalltomediumsizedigitalLCDpanels.TheLCDTCONalsoincludesa
dedicatedVGH/VGLpulsegeneratorfortheLCDpanelvoltagegenerator.Togetherwithsomesimplepassive

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components,VGH/VGLcanbegenerated.

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DVOut

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LCD Digital
Timing LCD
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Controller Panel
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VGH/VGL
Control
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3.5 Peripherals
3.5.1 CardReaderInterface
TheAML6210DPhaveanintegratedhardwarecontrollerforSD/MS/MMC/xDcardreaderoperations.The
hardwarecontrolleriscapableofexecutingthelowlevelcardinterfaceprotocols,computingtheCRCor
checksum,andtransferringdatato/fromSDRAM.Thehardwareprovidesinterfaceforthenecessarysignals
(e.g.SD_CLK,SD_CMD,SD_D03forSDcards)butsignalslikecarddetectandwriteprotectareprovidedusing

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GPIOonly.

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3.5.2 USBInterface
AM6210DPAVprocessorhasintegratedonehighspeedUSB2.0OTGcontrollerandPHYintothechip.The
outputUSBsignal(DP/DM)candrivetheexternalUSBcontroller(e.g.Hub,FLASHdrive,camera,PC,Mac,etc.)
directly.TheOTGcontrollercanactsasahighspeedUSBHostorUSBDeviceoratryOTGcontroller.

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4 OperatingConditions
4.1 DCCharacteristics
Table41DCCharacteristics

VDD = 3.3 +/- 0.3V, TA = 0 to 65C

Symbol Parameters Condition Min Typ Max Unit

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VIH High Level Input 2.0 3.3 V

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VIL Low Level Input -0.3 0.8 V
VT+ Schmitt trigger, positive going Threshold 1.5
VT- Schmitt trigger, negative going threshold 0.93 V
Voh High-level output voltage Ioh = -2.0mA 2.4

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V
to 24mA
Vol Low-level output voltage Iol = 2.0 mA 0.4
V
to 24mA
IIH High-level input current Vin = VDD 10nA 1

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IIL Low-level input current 10nA 1 uA
Ioz Tri-state output leakage current 10nA 1

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PD Power Dissipation Vin = VDD 0.8 W


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4.2 AbsoluteMaximumRatings
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Thetablebelowgivestheabsolutemaximumratings.Exposuretostressesbeyondthoselistedinthistable
mayresultinpermanentdevicedamage,unreliabilityorboth.
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Table42AbsoluteMaximumRatings

Characteristic Value Unit

1.25V Core Supply Voltage 1.4 V
3.3V Pads Supply Voltage 3.6 V
Input voltage, VI -0.5 ~ 4.6 V
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Output voltage, VO -0.5 ~ 4.6 V

Junction Temperature 125 C

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4.3 RecommendedOperatingConditions
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Table43RecommendedOperatingConditions

Symbol Parameter Min. Typ. Max Unit

VDD(CORE) 1.25V Core Supply Voltage 1.2 1.25 1.32 V
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VDD(PADS) 3.3V Pads Supply Voltage 3.0 3.3 3.6 V

TJ Operating Temperature 0 65 C

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5 Pinout
TheAML6210DPA/Vprocessorpinoutisdescribedinthefollowingtable.
Abbreviations:
I==Inputdigitalpin,O==Outputdigitalpin,I/O==Input/Outputpin
AI==Analoginputpin,AO==Analogoutputpin,AIO==Analoginput/outputpin
P==Powerpin,AP==Analogpowerpin,NC==Noconnection
Pin# PinName Description AlternateUsage/Comments Type

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1 VAA3V Analogpower 3.3Vanalogpower AP

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2 APAD0 Audiooutput AudiooutputLEFT AP
3 APAD1 Audiooutput AudiooutputRIGHT AO
4 AGND Analogground Analogground AP

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5 TCON_STH2 LCDPanelsignal LCDpanelclockpulse I/O
6 TCON_STH1 LCDPanelsignal LCDpanelclockpulse I/O
7 TCON_OEV1 LCDPanelsignal LCDpanelclockpulse I/O

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8 TCON_CPV1 LCDPanelsignal LCDpanelclockpulse I/O

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9 VDD33 DigitalI/OPower DigitalI/O3.3VPower P
10 TCON_STV1 LCDPanelsignal LCDpanelclockpulse I/O
11 TCON_STV2 LCDPanelsignal LCDpanelclockpulse I/O
12 VSS33 DigitalGround DigitalGround P
13 TCON_VCOM LCDPanelsignal
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LCDpanelclockpulse I/O
14 TCON_OEH LCDPanelsignal LCDpanelclockpulse I/O
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15 TCON_CPH1 LCDPanelsignal LCDpanelclockpulse I/O
16 GPIO//XD_INS GPIO GPIOforcardreader I/O
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17 GPIO//SD_INS GPIO GPIOforcardreader I/O

18 GPIO//MS_INS GPIO GPIOforcardreader I/O
19 NAND_WE_n NANDInterface NANDInterfaceWE I/O
20 NAND_RDYBSY NANDInterface NANDInterfaceRDYBSY I/O
21 NAND_CE_n NANDInterface NANDInterfaceCE I/O
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22 NAND_RD_n NANDInterface NANDInterfaceRD I/O

23 VDD12 DigitalCorePower Digitalcore1.2Vpower P
24 M1_A_3 M1_A_3 SDRAM1and/orFLASH I/O
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25 M1_A_2 M1_A_2 SDRAM1and/orFLASH I/O

26 M1_A_1 M1_A_1 SDRAM1and/orFLASH I/O
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27 VDD33 DigitalI/OPower DigitalI/O3.3Vpower P

28 M1_A_0 M1_A_0 SDRAM1and/orFLASH I/O
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29 M1_A_4 M1_A_4 SDRAM1and/orFLASH I/O

30 M1_A_5 M1_A_5 SDRAM1and/orFLASH I/O
31 M1_A_6 M1_A_6 SDRAM1and/orFLASH I/O
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32 VSS DigitalGround Digitalground P

33 M1_A_7 M1_A_7 SDRAM1and/orFLASH I/O
34 M1_A_8 M1_A_8 SDRAM1and/orFLASH I/O
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35 M1_A_9 M1_A_9 SDRAM1and/orFLASH I/O

36 M1_A_10 M1_A_10 SDRAM1and/orFLASH I/O

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Pin Pinname Description Comments/Alternateusage Type
37 M1_A_11 M1_A_11 SDRAM1and/orFLASH O
38 M1_BA1 M1_BA1 SDRAM1and/orFLASH O
39 M1_BA0 M1_BA0 SDRAM1and/orFLASH O
40 VDD33 I/OPower3.3V DigitalI/Opower3.3V P
41 M1_CLKO M1_CLKO SDRAM1and/orFLASH O
42 M1_DQM1 M1_DQM1 SDRAM1and/orFLASH O

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43 M1_DQM0 M1_DQM0 SDRAM1and/orFLASH O

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44 M1_SCS0_n M1_SCS0_n SDRAM1and/orFLASH O
45 M1_RAS_n M1_RAS_n SDRAM1and/orFLASH O
46 M1_CAS_n M1_CAS_n SDRAM1and/orFLASH O

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47 M1_WE_n M1_WE_n SDRAM1and/orFLASH O
48 M1_D_8 M1_D_8 SDRAM1and/orFLASH I/O
49 VSS VSS Digitalground P

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50 VDD12 DigitalCore1.2V Digitalcorepower1.2V P
51 M1_D_9 M1_D_9 SDRAM1and/orFLASH I/O

ee
52 M1_D_10 M1_D_10 SDRAM1and/orFLASH I/O
53 M1_D_11 M1_D_11 SDRAM1and/orFLASH I/O
54 M1_D_12 M1_D_12 SDRAM1and/orFLASH
h I/O
55 VDD33 I/OPower3.3V DigitalI/Opower3.3V P
56 M1_D_13 M1_D_13 SDRAM1and/orFLASH I/O
C
57 M1_D_14 M1_D_14 SDRAM1and/orFLASH I/O
58 M1_D_15 M1_D_15 SDRAM1and/orFLASH I/O
59 M1_D_7 M1_D_7 SDRAM1and/orFLASH I/O
to

60 VSS VSS Digitalground P

61 M1_D_6 M1_D_6 SDRAM1and/orFLASH I/O
62 M1_D_5 M1_D_5 SDRAM1and/orFLASH I/O
63 M1_D_4 M1_D_4 SDRAM1and/orFLASH I/O
te

64 M1_D_3 M1_D_3 SDRAM1and/orFLASH I/O

65 M1_D_2 M1_D_2 SDRAM1and/orFLASH I/O
u

66 M1_D_1 M1_D_1 SDRAM1and/orFLASH I/O

67 M1_D_0 M1_D_0 SDRAM1and/orFLASH I/O
ib

68 VDD33 I/OPower3.3V DigitalI/Opower3.3V P

69 REMOTE Remote RemoteControl I
70 PWM_LCD LCDPWM PWMfortheLCD? I/O
tr

71 GPOutput//LCD_PWR_EN GPO GPOforLCD_powercontrol O

72 RESET_N Reset MasterReset I

is
D

6/7/2010 17/24 AMLOGICProprietary

 AML6210DPA/VProcessorUserGuideVersion0.4

Pin Pinname Description Comments/Alternateusage Type
USBMinireceptacleIdentifierbetweenmini
73 USBA_id USBAidentifier A/miniBplug AI
USBpowersupplypin(5volt).Anoffchipcharge AP
74 USBA_vbus USBAminiVBUS pumpisusedtoprovidepowertotheVBUSpin.
USBADigital1.2V AP
75 USBA_vdd12 Power Digital1.2VpowerforUSBA
76 USBA_vss12 USBADigitalGround DigitalgroundforUSBA AP

77 USBA_vssa33t USBAground AnaloggroundforUSBAtransceiver AP

!
78 USBA_dp USBAD+ D+analogsignalfromtheUSBcable A

ip
79 USBA_dm USSAD DanalogsignalfromtheUSBcable A
80 USBA_vdda33t USBA3.3Vpower Analog3.3VpowerforUSBAtransceiver AP
Externalresistorthatcontrolsthebiascurrentfor AP

ch
81 USBA_rext USBAExtRefresistor USB
AP
82 USBA_vdda33c USBA3.3Vpower Analog3.3VpowerforUSBAcore
83 USBA_vssa33c USBAground AnaloggroundforUSBAcore AP
84 PLLC_AVDD33 PLLVDD PLLpower AP

r
85 PLLC_AVSS33 PLLGround PLLground AP
AP

ee
86 PLLB_AVDD33 PLLVDD PLLpower
87 PLLB_AVSS33 PLLGround PLLground AP
88 PLLA_AVDD33 PLLVDD PLLpower AP

89 PLLA_AVSS33 PLLGround PLLground AP

90 OSCIN OSCInput
h
27MHzcrystaloscillatorinput I
C
91 OSCOUT OSCOutput 27MHzcrystaloscillatoroutput O
92 VDD12 DigitalCorePower Digitalcore1.2Vpower P
93 BUTTON1 BUTTON_1 BUTTONorGPIOorMISC I/O
BUTTONorGPIOorMISC
to

94 BUTTON2 BUTTON_2 I/O

95 BUTTON3 BUTTON_3 BUTTONorGPIOorMISC I/O
96 VDD33 VDD DigitalPower3.3V P
97 I2C_CLOCK GPIO GPIO I/O
te

98 I2C_DATA GPIO GPIO I/O

99 VSS VSS DigitalGround P
100 XD_CE CardReaderI/O CardReaderI/ForGPIO I/O
u

101 XD_RB CardReaderI/O CardReaderI/ForGPIO I/O

102 XD_WP//SD_WP CardReaderI/O CardReaderI/ForGPIO I/O
ib

103 GPIO//CARD_POWER CardReaderI/O CardReaderI/ForGPIO I/O

104 XD_RE CardReaderI/O CardReaderI/ForGPIO I/O
tr

105 XD_WE CardReaderI/O CardReaderI/ForGPIO I/O

106 XD_RE CardReaderI/O CardReaderI/ForGPIO I/O
107 XD_CE CardReaderI/O CardReaderI/ForGPIO I/O
is

108 VDD33 DigitalI/OPower DigitalI/O3.3Vpower P

D

6/7/2010 18/24 AMLOGICProprietary

 AML6210DPA/VProcessorUserGuideVersion0.4

Pin Pinname Description Comments/Alternateusage Type
109 GPIO GPIO GeneralPurposeI/OorCARD_ENABLE I/O
110 XD_D0 CardReaderI/O CardReaderI/ForGPIO I/O
111 XD_D1 CardReaderI/O CardReaderI/ForGPIO I/O
112 XD_D2//SD_CMD CardReaderI/O CardReaderI/ForGPIO I/O
113 XD_D3//SD_CLK CardReaderI/O CardReaderI/ForGPIO I/O
114 VSS VSS DigitalGround P

!
115 XD_D4//SD_D0 CardReaderI/O CardReaderI/ForGPIO I/O

ip
116 XD_D5//SD_D1 CardReaderI/O CardReaderI/ForGPIO I/O
117 XD_D6//SD_D2 CardReaderI/O CardReaderI/ForGPIO I/O
118 VDD33 DigitalI/OPower DigitalI/O3.3Vpower P

ch
119 XD_D7//SD_D3 CardReaderI/O CardReaderI/ForGPIO I/O
120 VDD12 VDD DigitalPower1.2V P
121 LCD_R0 LCDVideoOut LCDVideoSignalOutput O

r
122 LCD_R1 LCDVideoOut LCDVideoSignalOutput O

ee
123 LCD_R2 LCDVideoOut LCDVideoSignalOutput O
124 LCD_R3 LCDVideoOut LCDVideoSignalOutput O
125 LCD_R4 LCDVideoOut LCDVideoSignalOutput O
126 LCD_R5 LCDVideoOut LCDVideoSignalOutput O
127 LCD_G0 LCDVideoOut
h LCDVideoSignalOutput O
128 LCD_G1 LCDVideoOut LCDVideoSignalOutput O
C
129 VSS VSS DigitalGround P
130 LCD_G2 LCDVideoOut LCDVideoSignalOutput O
to

131 LCD_G3 LCDVideoOut LCDVideoSignalOutput O

132 LCD_G4 LCDVideoOut LCDVideoSignalOutput O
133 LCD_G5 LCDVideoOut LCDVideoSignalOutput O
134 VDD33 VDD DigitalPower3.3V P
te

135 LCD_B0 LCDVideoOut LCDVideoSignalOutput O

136 LCD_B1 LCDVideoOut LCDVideoSignalOutput O
137 LCD_B2 LCDVideoOut LCDVideoSignalOutput O
u

138 LCD_B3 LCDVideoOut LCDVideoSignalOutput O

139 LCD_B4 LCDVideoOut LCDVideoSignalOutput O
ib

140 LCD_B5 LCDVideoOut LCDVideoSignalOutput O

141 JTAG_TMS//I2C_MASTER_CLOCK JTAGTMS JTAG I/O
142 JTAG_TDI//I2C_MASTER_DATA JTAGTDI JTAG I/O
tr

143 JTAG_TCK//AUDIO_MUTE JTAGTCK JTAG I/O

144 JTAG_TDO//OTG_VBUS JTAGTDO JTAG I/O
is

6/7/2010 19/24 AMLOGICProprietary

 AML6210DPA/VProcessorUserGuideVersion0.4

5.1Packagepinoutdiagram

JTAG_TMS//I2C_MASTER_CLOCK
JTAG_TDI//I2C_MASTER_DATA
JTAG_TCK//AUDIO_MUTE
JTAG_TDO//OTG_VBUS

XD_D2//SD_CMD
XD_D3//SD_CLK
XD_D7//SD_D3
XD_D6//SD_D2
XD_D5//SD_D1
XD_D4//SD_D0

!
ip
LCD_R5
LCD_R4
LCD_R3
LCD_R2
LCD_R1
LCD_R0
LCD_B5
LCD_B4
LCD_B3
LCD_B2
LCD_B1
LCD_B0
LCD_G5
LCD_G4
LCD_G3
LCD_G2
LCD_G1
LCD_G0
VDD33

VDD12
VDD33

XD_D1
XD_D0
GPIO
VSS

VSS

ch
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109



VAA3V 1
APAD0 2 108 VDD33
APAD1 3 107 XD_CE

r
AGND 4 106 XD_RE
TCON_STH2 5 105 XD_WE
TCON_STH1 6

ee
104 XD_RE
TCON_OEV1 7 103 GPIO//CARD_POWER
TCON_CPV1 8 102 XD_WP//SD_WP
VDD33 9 101 XD_RB
TCON_STV1 10 100 XD_CE
TCON_STV2 11 99 VSS
VSS33 12 h 98 I2C_DATA
TCON_VCOM 13

AML6210DP
97 I2C_CLOCK
TCON_OEH 14 96 VDD33
TCON_CPH1 15 95 BUTTON3
GPIO//XD_INS 16 94 BUTTON2
C
GPIO//SD_INS 17 93 BUTTON1

GPIO//MS_INS 18 92 VDD12
NAND_WE_n 19 91 OSCOUT
NAND_RDYBSY 20 90 OSCIN
NAND_CE_n 21 89 PLLA_AVSS33
to

NAND_RD_n 22 88 PLLA_AVDD33
VDD12 23 87 PLLB_AVSS33
M1_A_3 24 86 PLLB_AVDD33
M1_A_2 25 85 PLLC_AVSS33
M1_A_1 26 84 PLLC_AVDD33
VDD33 27 83 USBA_vssa33c
M1_A_0 28 82 USBA_vdda33c
M1_A_4 29
te

81 USBA_rext
M1_A_5 30 80 USBA_vdda33t
M1_A_6 31 79 USBA_dm
VSS 32 78 USBA_dp
M1_A_7 33 77 USBA_vssa33t
M1_A_8 34 76 USBA_vss12
u

M1_A_9 35 75 USBA_vdd12
M1_A_10 3 74 USBA_vbus
6 73 USBA_id
ib 37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

RESET_N
PWM_LCD
VSS

VSS

REMOTE
M1_CLKO

M1_SCS0_n
M1_RAS_n
M1_CAS_n
M1_WE_n

GPOutput//LCD_PWR_EN
M1_A_11

VDD33

M1_D_8
VDD12
M1_D_9

VDD33

M1_D_7
M1_D_6
M1_D_5
M1_D_4
M1_D_3
M1_D_2
M1_D_1
M1_D_0
VDD33
M1_BA1
M1_BA0

M1_DQM1
M1_DQM0

M1_D_10
M1_D_11
M1_D_12
M1_D_13
M1_D_14
M1_D_15
tr
is
D

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 AML6210DPA/VProcessorUserGuideVersion0.4

5.1 Multiplefunctionpins
Multipleusagepinsareusedtoconversepinconsumptionfordifferentfeatures.TheAML6210DPdevices
canbeusedinmanydifferentapplicationsbuteachapplicationwillnotutilizealltheonchipfeatures.Asa
result,someofthefeaturessharethesamepin.MostofthemultipleusagepinscanbeaGPIOpinalso.

Thefollowingtablesillustratetheapplicationsofthemultipleusagepins.

ip

5.1.1 CardReaderinterfacemultifunctionpins

ch

PIN# PACKAGE PIN NAME XD SD MS GPIO
100 XD_RE XD_RE AT_GPIO0

r
101 XD_WE XD_WE AT_GPIO1

ee
102 XD_READY XD_READY AT_GPIO2
103 XD_CE XD_CE AT_GPIO3
104 XD_ALE XD_ALE h AT_GPIO6
103 XD_CLE AT_GPIO7
110 XD_D0 XD_D0 AT_GPIO8
C
111 XD_D1 XD_D1 AT_GPIO9
112 XD_D2 XD_D2 SD_CMD MS_STB AT_GPIO10
113 XD_D3 XD_D3 SD_CLK MS_CLK AT_GPIO11
to

115 XD_D4 XD_D4 SD_D0 MS_D0 AT_GPIO12

116 XD_D5 XD_D5 SD_D1 MS_D1 AT_GPIO13
117 XD_D6 XD_D6 SD_D2 MS_D2 AT_GPIO14
119 XD_D7 XD_D7 SD_D3 MS_D3 AT_GPIO15
te

5.1.2 TCONMultiFunctionPins
u

Pin# Package Pin Name LCD TCON GPIO

5 TCON_STH2 TCON_STH2 LCD_GPIO_29
ib

6 TCON_STH1 TCON_STH1 LCD_GPIO_28

7 TCON_OEV1 TCON_OEV1 LCD_GPIO_24
tr

8 TCON_CPV1 TCON_CPV1 LCD_GPIO_25

10 TCON_STV1 TCON_STV1 LCD_GPIO_26
11 TCON_STV2 TCON_STV2 LCD_GPIO_27
is

13 TCON_VCOM TCON_VCOM LCD_GPIO_31

14 TCON_OEH TCON_OEH LCD_GPIO_30
D

15 TCON_CPH1 TCON_CPH1/2/3 LCD_GPIO_23

5.1.3 JTAGinterfacemultifunctionpins

Pin# Package Pin Name JTAG MISC GPIO
141 JTAG_TMS JTAG_TMS I2C_MSTR_CLK JTAG_GPIO_1
142 JTAG_TDI JTAG_TDI I2C_MSTR_DATA JTAG_GPIO_2
143 JTAG_TCK JTAG_TCK UART_RX JTAG_GPIO_0

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 AML6210DPA/VProcessorUserGuideVersion0.4

144 JTAG_TDO JTAG_TDO UART_TX JTAG_GPIO_3

5.1.4 FLASHandm1_*interfacemultifunctionpins

Pin# Package Pin Name SDRAM Memory Interface NAND FLASH Usage NOR FLASH Usage MISC

!
Usage (8-bits wide or 16- (8-bits wide, maximum

ip
(16bits wide only) bits wide) of 8Mbytes)
111 NAND_WE_n NAND_WE_n EGPIO_8
112 NAND_RDYBSY NAND_RDY_BSY EGPIO_9

ch
113 NAND_CE_n NAND_CE_n FLASH_CS_n
114 NAND_RD_n NAND_RD_n FLASH_OE_n
116 M1_A_3 M1_A_3 FLASH_A_3
117 M1_A_2 M1_A_2 FLASH_A_2

r
118 M1_A_1 M1_A_1 FLASH_A_1

ee
120 M1_A_0 M1_A_0 FLASH_A_0
121 M1_A_4 M1_A_4 FLASH_A_4
122 M1_A_5 M1_A_5 h FLASH_A_5
123 M1_A_6 M1_A_6 FLASH_A_6
125 M1_A_7 M1_A_7 FLASH_A_7
C
126 M1_A_8 M1_A_8 FLASH_A_8
127 M1_A_9 M1_A_9 FLASH_A_9
128 M1_A_10 M1_A_10 FLASH_A_10
to

1 M1_A_11 M1_A_11 FLASH_A_11

2 M1_BA1 M1_BA1
3 M1_BA0 M1_BA0
5 M1_CLKO M1_CLKO
te

6 M1_DQM1 M1_DQM1 FLASH_A_21

7 M1_DQM0 M1_DQM0 FLASH_A_20
8 M1_SCS0_n M1_SCS0_n
u

9 M1_RAS_n M1_RAS_n FLASH_A_22

ib

10 M1_CAS_n M1_CAS_n
11 M1_WE_n M1_WE_n FLASH_WE_n
12 M1_D_8 M1_D_8 NAND_8 FLASH_A_12
tr

15 M1_D_9 M1_D_9 NAND_9 FLASH_A_13

16 M1_D_10 M1_D_10 NAND_10 FLASH_A_14
NAND_11 FLASH_A_15
is

17 M1_D_11 M1_D_11
18 M1_D_12 M1_D_12 NAND_12 FLASH_A_16
20 M1_D_13 M1_D_13 NAND_13 FLASH_A_17
D

21 M1_D_14 M1_D_14 NAND_14 FLASH_A_18

22 M1_D_15 M1_D_15 NAND_15 FLASH_A_19
23 M1_D_7 M1_D_7 NAND_7 FLASH_D_7
25 M1_D_6 M1_D_6 NAND_6 FLASH_D_6
26 M1_D_5 M1_D_5 NAND_5 FLASH_D_5
27 M1_D_4 M1_D_4 NAND_4 FLASH_D_4
28 M1_D_3 M1_D_3 NAND_3 FLASH_D_3
29 M1_D_2 M1_D_2 NAND_2 FLASH_D_2
30 M1_D_1 M1_D_1 NAND_1 FLASH_D_1

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 AML6210DPA/VProcessorUserGuideVersion0.4

31 M1_D_0 M1_D_0 NAND_0 FLASH_D_0

!
ip
r ch
ee
h
C
to
te
u
ib
tr
is
D

6/7/2010 23/24 AMLOGICProprietary

 AML6210DPA/VProcessorUserGuideVersion0.4

6 MechanicalSpecifications

TheAML6210DPA/Vprocessorispackagedusinga144pinsLQFPpackage.Themechanicaldimensionsare
giveninmillimetersasbelow:

!
ip
22.000.25

20.000.10

ch
0.17/0.20/0.27

r
ee
Amlogic
AML6210DP
20.000.10
22.000.25

h 0.50BSC

144PinLQFP
C
20mmx20mm
to
te
u

1.35/1.40/1.45
ib

0.05/0.15 0.45/0.60/0.75
1.00REF
tr
is
D

6/7/2010 24/24 AMLOGICProprietary