08 Jespers MOS-AK SF08 PDF

MOS-AK workshop
13 Dec. 2008
Sizing CMOS circuits by means of the gm/ID

methodology and a compact model.
P.G.A. Jespers
Universit Catholique de Louvain
paul.jespers@uclouvain.be
1
MOS-AK workshop, Dec 13, 2008. P.G.A. Jespers
sizing....
find D.C. currents and transistor sizes

meeting :
a prescribed gain-bandwidth product
minimal power consumption
minimal area
large gain
.
short channel devices,..
low-voltage, low-power
low- voltage, low-power circuits
MOS circuits
2
BWRC, Dec 12, 2008. P.G.A. Jespers
Outline
Sizing...
the Intrinsic Gain Stage (I.G.S.)
gm/ID semi-empirical methodology
gm/ID compact model methodology
L-V, L-P, short channel I.G.S.
the Miller Op. Amp.
Conclusion
3
The Intrinsic Gain Stage (I.G.S.)
ID
gain-bandwidth sizing: W/L Vout
Vin (sat) C
find ID and W/L
achieving T
A (dB)
gm .V
gm = T.C ID A
- 20 dB/decade
log
gm
T =
C 4
1) (strong inversion)
W
" = Cox
#
L
ID
Vout $ ID 2 " ID
gm = =
Vin
$ VG n
(sat) C
W/L
2
! W n ( "T C ) 1
= $
gm = "T C L 2 Cox
# ID
?
!
! A = gm V = 2"
VA
A
ID nID ID
power decreases, gain increases

!
5
! BWRC, Dec 12, 2008. P.G.A. Jespers
2) weak inversion)
" VG %
ID = Io exp$ '
ID nU
# T&
Vout
ID
Vin (sat) C gm =
nUT
W/L
W
gm = "T C ! L
VA
Amax = "
nUT
!
!
sizing in moderate inversion? ! ID
I D = n UT ! T C
! 6
Outline
Sizing...
the Miller Op. Amp.
Conclusion
7
what does gm/ID represent ? 10-3
10-4
ID W.I. approx
10-5
(expon)
10-6
" gm % 1 ( ID ( 10-7
$ ' = = log ( ID )
# ID & ID (VGS (VGS 10-8
-9
10
-10
10
10-11
10-12
S.I. approx
(quadratic)
! 10-13
0 0.5 1 1.5 2 2.5 3
VG
35
gm/ID 30
25
20
15
10
0 VG
0 0.5 1 1.5 2 2.5
8 3

why gm/ID?
gm/ID does not depend on the transistor width

gm and ID are proportional to W
gm/ID bridges a small signal and a large signal quantity
gm " ID
gm/ID controls gain, power consumption ...
gm
! A = VA
ID
9
The gm/ID sizing methodology
(semi-empirical)
measurements
reconstructed data (BSIM, PSP...)
model E.K.V...
gm = "T C
W ref
gm
ID (VGS ) = "
! " gm % log ( IDref (VGS ))
$ ' "V!GS
# ID &
monitors the mode of operation
of the MOS transistor
I (V ) !
! (VGS ) = D GS (W ) ref
W
ID ref (VGS )
! 10
Example
W/L
parasitic drain junction
mobility degradation
ID (A)
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V; Wmax = 1 m;
11
First paper
A gm/ID Based Methodology for the Design of CMOS Analog Circuits and
Its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA
F. Silveira, D. Flandre, P.G.A. Jespers
IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 31, NO. 9, SEPTEMBER 1996
p. 1314 ...
12
Outline
Sizing...
the Miller Op. Amp.
Conclusion
13
The ACM and EKV compact models
+ continuous model (saturation, weak to strong inversion)

+ few parameters:
n subthreshold slope factor
ISu unary specific current
VTo threshold voltage
- uniformly doped substrate, no mobility degradation,
- gradual channel approximation (1D)
A.C.M.
- An MOS transistor model for analog circuit design
Ana I. Cunha, M.C. Schneider, C. G. Montoro.
IEEE JSSC,vol 33,n10,oct, 1998.
E.K.V.
- An analytical MOS transistor model valid in all regions of operation and dedicated to Low-Voltage
and Low-current applications.
Chr. C.Enz, F. Krummenacher, E. A. Vittoz.
Analog Integrated Circuits and Signal Processing, Kluwer Ac. Publ. 1995.
14
The compact model (1)
drain current normalization
ID
normalized drain current i=
IS
64 4744 8
! W 1 W
specific current 2nUT2Cox" nU 2
C "
14243 L 2
T ox
L
EKV ACM
ISu
!
!
unary specific current (W = L)
!
15
norm. drain current (saturation)

i = q2 + q
Qi#
normalized mobile charge density q="
2nUT Cox
#
!
channel voltage VP " V = UT [2(q "1) +!log(q)]
pinch - off voltage

!
VG " VTo
gate voltage VP =
n
16
!
ID = IDForward - IDReverse
VD
sat sat
VG VG
VS VS VD
VP " VS = UT [2(qF "1) + log(qF )] VP " VD = UT [2(qR "1) + log(qR )]
i = qF2 + qF - (qR2 + qR )
! ! 17
example : IDu(VG) of grounded source (VS = 0 V) saturated (q => qF) transistor
parametric method
i = qF2 + qF IDu = i ISu

qF
VP = UT (2(qF "1) + logqF ) VG = nVP + VTo
! !
! % data
IDu (A)
UT = .026; S.I.
n =! 1.2;
!
Isu = 1e-6;
VTo = 0.4;
% compute
qF = logspace(-4,1.2,50);
i = qF.^2 + qF;
ID = i*Isu;
VP = UT*(2*(qF-1) + log(qF));
VG = n*VP + VTo;
W.I.
% plot VTo VG (V)
semilogy(VG,ID); grid
18
gm/ID of the saturated transistor
di 2qF + 1
d log(i) = = dqF
gm d log(i) i i
= and
ID dVG
" 1% 2q + 1
dVG = n dVP = nUT $ 2 + ' dqF = nUT F dqF
# qF & qF
! gm 1 qF 1 1
! = =
ID nUT i nUT qF + 1
!
19
sizing the Intrinsic Gain Stage by means of the
E.K.V. model
% data
fT = 1e8;
C = 1e-12;
specs
n = 1.2;
E.K.V. param Isu = 1e-6;
VTo = 0.4;
% compute
UT = .026;
T = 2*pi*fT;
gm = T*C;
qF = logspace(-4,1.5,50);
gmoverID = 1./(n*UT*(1+qF));
ID = gm./gmoverID;
gm/ID sizing IDu = Isu*(qF.^2 + qF);
WsL = ID./IDu;
VP = UT*(2*(qF+1) + log(qF));
VG = n*VP + VTo;
% plot
loglog(ID,WsL,'b',ID,VG,'r');
20
sizing the Intrinsic Gain Stage by means of the
E.K.V. model
fT = 100 MHz
C = 1 pF
W/L
strong inversion
approx. gm/ID sizing
VGS (V)
ID (A)
weak inversion approx.

21
The basic EKV / ACM model does not apply to short channel devices!
Real ID(VGS) characteristics however look very similar.
ID (A)
VDS = 1.2 V
VDS = 0.2 V L = 500 nm
L = 100 nm
90 nm technology
N channel
W = 10 m
VSB = 0 V
VGS (V)
22
The spatial distribution of electrical fields in the substrate boils down to a 2D problem
controlled mainly by L, VSB, VDS, little by VGS.
The inversion layer confines to a 1D problem controlled by VGS and L, VSB, VDS.
Is it possible to model ID(VG) characteristics by means of the EKV / ACM model

with parameters that are functions of L, VS and VD.?
gate silicide
source poly drain
n-
n+ to
x
23
E.K.V. Identification log(ID) n
to be performed in the
common source configuration
S.I.
W.I.
For L, VS and VDS M.I.
VGS
gm/ID
1/nUT
mobility
degradation
80 to 70 %
VGS
VTo
24
Isu (specific current)
IDu (VGS )
= ISu (VGS )
i
VGS " VTo (A)
= VP # q
n
! ISuo
!
polynomial fit
!
ISu = 2nUT2 oCox
" # (i )
14243
I Suo
VGS (V)
mobility degradation factor

!
For L, VS and VDS 25
Verification : Iu(VGS) reconstruction
n,VTo and ISuo
IDu (A)
n slope factor
experm. data
+++ n,Vto, Isuo and (i)
VGS (V)
N-channel; L = 100 nm; VDS = 0.6 V; VSB = 0.6 V.

26
gm/ID (V-1)
edge conductance effect ?
mob. degradation
VDS = 0.6 V
VSB = 0 V
L = 100 nm
VGS (V)
experimental
+++++ model
model (no mob degradation) 27
Outline
Sizing...
the Miller Op. Amp.
Conclusion
28
gm
does not depend on W
ID as long as W >> Wmin
(true for most analogue circuits)
depends on L, VDS and VSB for

! - VT roll-off
- D.I.B.L.
- C.L.M.
- mobility degradation
- .
29
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V;
W/L
strong
inversion n, VTo and Isuo
approx. no mobilty degradation: = 1
VGS (V)
ID (A)
30
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V;
W/L
strong
inversion n, VTo and Isuo
approx. with mobilty degradation: ()
VGS (V)
ID (A)
31
Add drain junction cap. to Co
W/L
partitioning
VGS (V)
ID (A)
32
Comparison with semi-empirical method (+++ )
W/L
partitioning
VGS (V)
ID (A)
33
Param. dependence on VDS
1) n small
2) VTo
L m
0.100
0.110
0.120
0.130
0.140
0.160
0.500
1.000
4.000
VSB = 0 V. D.I.B.L.
VDS (V)
34
1) n small ISu (A)
2) VTo
3) ISu
channel length !
modulation
mobility degradation (vert)
mobility (longitudinal)
Desaturation
VDS (V)
VGS (V)
VSB = 0 V.
35
1) n small
2) VTo
3) ISuo
L m
VSB = 0 V. 0.100
0.110
0.120
0.130
0.140
0.160
0.500
1.000
4.000
C.M.L.
36
Param. dependence on VDS VSB = 0 V.
1) n small
lo n
2) VTo a l fie ld g itu
ic d in
3) Isuo v e rt al f
ie ld
4) (i)
not sat.
sat.
37
Verification : IDu(VDS) reconstruction (S.I.)
X 10-5
experimental
+++++ model
model (no mob degradation)
VGS
0.7 V
0.6 V
0.5 V
38
Verification : IDu(VDS) reconstruction (W.I.)
X 10-9
0.10 V
experimental
+++++ model VGS
model (no mob degradation)
D.I.B.L.
0.05 V
0.00 V
39
Outline
Sizing...
the Miller Op. Amp.
Conclusion
40
1) fix NDPole and Zero with respect to T to meet phase margin
V
DD
Bias
Q5 Q4
2 ID1 ID2
- vin / 2 Q1a Q1b + v in / 2 Cm node 2 vout
C2
g node 3 node1
"T = m1
Cm Q2
Q3a Q3b
g V
z = m2 = Z"T C3 C1
SS
Cm
gm2 Cm2
" ndp = = NDP"T
Cm (C1+C2)Cm + C1C2
e.g. Z = 10 and NDP = 4 5

for phase margin of approx. 60
41
2) Size the A transistors.
V
DD
spec. initial guess Bias
Q5 Q4
2 ID1 ID2
vin / 2 Q1a Q1b v in / 2 vout

gm1 = "T Cm - + Cm node 2
C2
g node 3 node1
I D1 = ! m1$
g Q2
## m && qF1 Q3a Q3b
V
" ID %1 C3 C1
SS
W1 = ID1 gm2 = Z gm1

L1 IDu 1
g
I D2 = ! m2$
g
## m && qF2
" ID % 2
W2 = ID2
L2 IDu 2
42
3) Size the B transistors.
more constraints
V
DD
Bias
zero systematic offset Q5 Q4
2 ID1 ID2
VG3 = VG2 - vin / 2 Q1a Q1b + v in / 2 Cm node 2 vout
C2
node 3 node1
"W % ID1
$ ' = Q3a Q3b
Q2
# L &3 IDu2 V
SS
C3 C1
choose bias so that Q4 and

! Q5 are in strong inversion "W % ID 2
$ ' =
# L &4 IDu4
IDu4 = IDu5
"W % 2 ID1
$ ' =
# L &5 IDu4
!
43
!
!
4) Estimate C1, C2, C3 and compute Cm
Choose
L1 medium (voltage gain)
L2 min. size
L3 large for min 1/f noise (beware from doublet!)
L4 matching + size
L5 matching + common mode rejection
the parasitic cap. are estimated knowing Ws and Ls + techno. data

a new Cm is extracted from inverted NDP equation
NDP " Z %
Cm = 0.5 ! $C1 + C2 + (C1 + C2 ) + 4 C1 C2 '
Z # NDP &
reiterate until Cm gets constant

44
example
qF1 = 0.0316 --> 3.16

qF exploration
qF2 = 0.10 --> 2
space
qF4 = 2,90
Spec: fT = 50 MHz;
C = 1 pF; Z = 10 phase
VDD = 1.2 V; NDP = 4 margin
1.2 V
L1 = 1 m
Q 2 ID1 Q4
5 ID2 L2 = 0.5 m
Q1 Cm
node 2 L3 = 1 m
node 3 node1 C2 L4 = 0.5 m
L5 = 1 m
Q3 Q2
0V
C3 C1
45
W1 W2
VG2 VG1
W3 W4
46
constant active area (m2) 47
constant supply (A)
constant gain (dB)
constant supply (A)
constant gain (dB)
constant supply (A)
The selected point Q1 Q2 Q3 Q4 Q5
0.433 1.065 1.236 2.90 2.90
qF
0.29 0.40 0.40 0.49 0.49
VGS (V)
2 x 8.1 143.7 2 x 8.1
I (A)
W (m) 67.3 47.5 2.23 57.83 7.69
L 1 0.5 1 0.5 1
45.1 39.2
gain (dB)
0.1965 1.0375 0.0576 0.6242
1.2 V
Q
C1 C2 C3 Cm
5 2 ID1 Q4
ID2
pF pF pF pF
node 2
Q1 Cm
node 3 node1 C2
gain = 81 dB
Q3 Q2 power consump. = 191 W
0V
C3 C1
51
Conclusion
gm/ID
relates a small signal param. to a large signal quantity
does not vary with transistor widths
controls the mode of operation, power consump, gain ...
paves the way for sizing CMOS circuits

semi-empirically
(look-up tables : ID, gm, gd, ..)
by means of the E.K.V./A.C.M. model
(parameters look-up tables or fitting functions)
simple expressions of ID, gm/ID, gd/ID
qF monitors mode of operation
increased physical insight
suitable for sub-micron low-voltage low-power circuits
52
gm/ID sizing methodology
for low-power/voltage
CMOS circuits
by P.G A. Jespers
to be published 2009 by Springer
paul.jespers@uclouvain.be
53
A list of references concerning the gm/ID methodology:
1) A gm/ID based methodology for the design of CMOS analog circuits and its application
to the synthesis of a silicon-on-insulator micropower OTA.
F. Silveira, D. Flandre and P.G.A. Jespers
IEEE Journal of Solid-State Circuits, vol 31, n 9, sept 1996, p. 1314 - 1319.
(the first reference)
2) A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
D.M. Binkley, C.E. Hopper, S.D. Tucker, B.C. Moss, J.M. Rochelle and D.P. Foty.
IEEE Trans. on computer-aided design of integrated circuits and systems,
vol 22, n 2, Febr. 2003.
3) gm/ID-based mosfet modeling and modern analog design.
D. Foty, D. Binkley, Matthias Bucher.
Presented at MIXDES, Wroclaw, Poland, 20 June 2002.
4) Une mthodologie de conception des amplificateurs oprationnels faible consommation
P. Jespers.
FTFC2001 records, mai-juin, Paris, p.99-106
5) Automated design methodology for CMOS analog circuit blocks in complex systems.
R. Ionita, A. Vladimirescu and P.G.A. Jespers.
contact Prof Vladimirescu, UCBerkeley, BWRC,2208 Allston Way, Berkeley, CA 94704.
6) Sizing of MOS transistors for amplifier design.
R.L. Oliveira Pinto, M.C. Schneider and C.G. Montoro.
ISCAS 2000.
7) A behavioral model of a 1.8-V flash A/D converter based on device parameters.
M. Hasan, H.H.P. Shen, D.R. Allee, M. Pennell.
IEEE Trans. on computer-aided design of integrated circuits and systems, vol 19, n 1,
Jan 2000, p 69-82
54

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MOS-AK workshop

Sizing CMOS circuits by means of the gm/ID

find D.C. currents and transistor sizes

power decreases, gain increases

BWRC, Dec 12, 2008. P.G.A. Jespers

gm/ID does not depend on the transistor width

gm/ID bridges a small signal and a large signal quantity

fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V; Wmax = 1 m;

F. Silveira, D. Flandre, P.G.A. Jespers

+ continuous model (saturation, weak to strong inversion)

drain current normalization

norm. drain current (saturation)

channel voltage VP " V = UT [2(q "1) +!log(q)]

pinch - off voltage

VP " VS = UT [2(qF "1) + log(qF )] VP " VD = UT [2(qR "1) + log(qR )]

i = qF2 + qF IDu = i ISu

weak inversion approx.

Real ID(VGS) characteristics however look very similar.

VDS = 0.2 V L = 500 nm

Is it possible to model ID(VG) characteristics by means of the EKV / ACM model

source poly drain

mobility degradation factor

+++ n,Vto, Isuo and (i)

N-channel; L = 100 nm; VDS = 0.6 V; VSB = 0.6 V.

edge conductance effect ?

depends on L, VDS and VSB for

mobility degradation (vert)

- vin / 2 Q1a Q1b + v in / 2 Cm node 2 vout

e.g. Z = 10 and NDP = 4 5

vin / 2 Q1a Q1b v in / 2 vout

W1 = ID1 gm2 = Z gm1

VG3 = VG2 - vin / 2 Q1a Q1b + v in / 2 Cm node 2 vout

choose bias so that Q4 and

the parasitic cap. are estimated knowing Ws and Ls + techno. data

reiterate until Cm gets constant

qF1 = 0.0316 --> 3.16

paves the way for sizing CMOS circuits

suitable for sub-micron low-voltage low-power circuits

to be published 2009 by Springer

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