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Module-1 Digital and Analog Signals: CS2201 Switching Circuits and Logic Design
Module-1 Digital and Analog Signals: CS2201 Switching Circuits and Logic Design
Module-1
DIGITAL AND ANALOG SIGNALS
An electrical signal can be defined as the variation of electrical quantity i.e
voltage or current with respect to time.That means the signal which does not vary with
respect to time is not a signal.For example D.C is constant with respect to time even
though it is a signal.
Fig:Analog Signal
An analog signal is a signal which takes any value from the given by taking the values
of electrical signal at different time intervals.
Signals can be categorized in various ways:for example, discrete time signals and
continuous time signals.Even when the signal functions are not continous,continuous
Analog systems can be called wave systems.The digital signals are specified as one
of the two possibilities such as 1 or 0, HIGH or LOW, TRUE or FALSE.Digital is a method
of storing, processing, and transmitting information through the use of discrete
electronic pulses that represent the binary digits 0 and 1.While the no.of recording
intervals of analog signal increases, the accuracy of signal increases.There are many
advantages with digital signals over analog signals, that is the reason why we use digital
signals more.
Noise Margin:
Digital signals are less effected by noise.If the noise is below a certain level
all.However if the noise exceeds this level, the digital circuit can not give correct results.
Digital signals can be regenerated to achieve lossless data transmission, which contain
limits.Analog signals transmission and processing , by contrast always introduces noise.
Digital systems interface well with computers and are easy to control with software.It
is often possible to add new features to a digital system without changing hardware
and to do this remotely, just by uploading new software.
More digital circuitary can be fabricated per sqare millimeter of integrated circuit
material.Information storage can be much easier in digital systems than in analog
ones.In an analog system, aging and wear and tear will degrade the information in
storage, but in digital systems as long as the wear and tear is below a certain level, the
information canbe recovered perfectly.Theoritically,there is no data loss when copying
digital data.This is a great advantage over analog systems which faithfully reproduce
every bit of noise that makes its way into the signal.
Disadvantages:-
The world in which we live is analog, and signals from this world such that light,
temperature, sound, electrical conductivity, electric and magnetic fields and
phenomenon of such as flow of time, are of most particular purpose continuous and
thus analog quantities rather than discrete digital ones.
For a digital system to do useful things in real world, translation from continuous
realm to the discrete digital realm must occur, resulting in quantization errors.This
problem can usually be integrated by designing desired degree of fredility.The nyquist
shannon theorem provides an important guide lines as to how much digital data is
needed to accurately portray a given analog signal.
A corollary of the fact that digital circuits are made from analog components is the
fact that digital circuits are slower to perform calculations than analog circuits that
occupy a similar amount of physical space.However the digital circuit will perform the
calculation with much better repeatability due to the high noise immunity of digital
circuitry.
Reference Books:
Module-2
NUMBER SYSTEM
A Digital D
D System A
C C
Decimal numbers:
The decimal system has 10 symbols: 0,1,2,3,4,5,6,7,8,9. In other words it has a base
of 10.
= 2000+700+30+4
In general in a number system with a base or radix r, the digits used are from 0 to r-1
and the number can be represented as
r= base or radix
The above equation holds for all integers. For the fractions the following equation holds
Where a-1 = 7
a-2 = 1
a-3 = 2
a-4 = 3
Binary numbers:
The binary number has a radix of 2. As r = 2, only wo digits are needed.These are 0 and
1.For the decimal system, radix is 10 which needs 10 digits.
N = (101010)2
= 1X25+0X24+1X23+0X22+1X21+0X20
= 43
For N symbols to be represented, the minimum no.of bits required is the lowest
integer r that satisfies the relationship
2r > N
Octal numbers:
Octal systems use a base or radix of 8.Thus it has digits from 0 t0 7(r-1)
N = (15.2)8
= 13.25
Hexadecimal numbers:
Below table shows a relatioship between decimal, binary, octal and hexadecimal
number systems.
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Integer part:
Fraction part:
Ex: Conversion of decimal 23 to binary is by divide decimal value by ( 2 the base) until
the value is 0.
2 23
2 11 1 ---- LSD
2 5 1
2 2 1
2 1 0
0 1 ----- MSD
0.7854X2=1.5708 ; a-1 = 1
0.5708X2=1.1416; a-2=1
0.1416X2=0.2832; a-3=0
0.2832X2=0.5664; a-4=0
For converting a binary number to octal, the following procedure can follow
1. Group the no.of bits into 3s starting at least significant symbol. If the no.of bits
are not evenly divisible by 3, then add os at the most significant bit.
4 2 3
For converting a binary number to hexadecimal, the following procedure can follow
1. Group the no.of bits into 4s starting at least significant symbol.If the no,of bits is
not evenly divisable by 4, then add 0s at the most significant end.
9 E 7 0 (hexadecimal)
Assignment:
Module-3
LOGIC GATES
Digital signal takes discrete level, we realize this by taking switch as an example on and off
represents two different states in the case of switch. If we have two level signal than we call it as
binary signal. We can convert analog signal into digital signal by using analog to digital converter. We
can represent the output signal in analog to digital converter by using multiple bits
0V 0 level
TYPES OF LOGIC:-
POSITIVE LOGIC;-
If 0 level represents low level and 1 level represents high level than we call such type of logic as
positive logic.
Level 0 0v or -5v
Level 1 5v or 0v
NEGATIVE LOGIC :-
If 0 level represents high value and 1 level represent low value than we call such type of logic as
negative logic.
Level 0 5v
Level 1 0v
systems
Subsystems
Modules
Functions
Logic levels
1. Combinational
2. Sequential
In digital systems we use both combinational and sequential function.
1.COMBINATIONAL FUNCTION:
Output value depends only on the current input. No memory is needed to store or
remember any value
2.SEQUENTIAL FUNCTION:-
Output values are depends on the current inputs and past outputs. Memory element is required to
store the previous output. Sequential logic contains combinational logic also.
LOGIC GATES;-
A logic gate is an electric circuit that performs a particular logic function. Logic gates
have one or more inputs terminals and one output terminal. Each input terminals represents an
independent variable. At any given instance of time every terminal is one of the two binary
conditions as high or low. In most logic gates, low state is approximately 0 or high state is 5v.
Logic gates are different types depending upon the logical function preformed by the gate.
The different types are AND, OR, NOT, NAND, NOR, XOR, XNOR, gates.
AND GATE:-
The output is true if both inputs are true. Other wise the output is false.
TRUTH TABLE:-
A B F
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE:-
The output is true when one of the input is true and when the both inputs are true other wise the
output as false.
SYMBOL:-
TRUTH TABLE
A B F
0 0 0
0 1 1
1 0 1
1 1 1
NOT GATE:-
It has one input and one output terminal. When the input is high, output is low and when
input is low, output is high
TRUTH TABLE:-
A B
1 0
0 1
NAND GATE;-
It has two or more inputs terminals and one output terminals. The output is an inversion of
output of AND gate. If A and B are inputs, output is NOT (A and B)
SYMBOL
TRUTH TABLE
A B F
0 0 1
0 1 1
1 0 1
1 1 0
NOR GATE;-
It has two or more input terminals and one output terminal. The output of a NOR gate is an
inversion of the output of an OR gate i.e, if A and B are the inputs the output is NOT (A OR B)
SYMBOL;
TRUTH TABLE;-
A B Y
0 0 1
1 0 0
0 1 0
1 1 0
EX-OR GATE:-
It has two or more input terminal, and one input terminal when both inputs are low or high the
output is low. If both inputs differ it is high.
SYMBOL:-
TRUTH TABLE
A B A
0 0 0
1 0 1
0 1 1
1 1 0
EX-NOR GATE;-
It has two or more inputs terminals, and one output terminal. The output of EX-NOR gate is an
inversion of output of an EX-NOR gate. i.e, if A and B are the inputs and the Output of and EX-NOR
gate is NOT (A+B)
SYMBOL; -
TRUTH TABLE
A B F
0 0 1
0 1 0
1 0 0
1 1 1
Module-4
Universal Gates
Both NAND and NOR gates are called as universal gates , because we design any gate by
using any one of the two gates. First of all we see the construction of AND, OR, NOT, XOR, XNOR
gates by using NAND.
0 1
1 0
In the
implementation of NOT using NAND we have to take only one input A.
A B C
0 0 1
1 0 1
0 1 1
1 1 0
Eliminate 2 and 3 rows from the NAND truth table and make B=A. we get NOT gate.
AND
We get AND with the help of NAND by inverting the output of the NAND gate.
Replace NOT gate with equivalent NAND then we get AND gate.
The truth table of the above circuit diagram is same as AND gate.
A B F
0 0 0
0 1 0
1 0 0
1 1 1
0R
Invert both inputs A and B and provide it to NAND gate as inputs and we get OR gate as output
NOR GATE
Invert output of OR then we can get NOR gate by using NAND gate.
The truth table of OR and NOR as same as previous. Because now we are constructing these gates
by using NAND GATE
X-OR GATE
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CS2201 Switching Circuits and Logic Design
X-NOR GATE
Inverting X-OR gives X-NOR gate.
NOR
A B F
0 0 1
1 0 0
0 1 0
1 1 0
TRUTH TABLE
0 1
1 O
OR GATE:-
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CS2201 Switching Circuits and Logic Design
AND GATE:-
We design AND gate using NOR by inverting the both inputs A and B to the NOR gate.
NAND GATE:-
Inversion of AND gate gives NAND gate.
MODULE -5
BOOLEAN ALGEBRA
2. A Boolean algebra is an algebraic system consisting of the set {0,1} the binary operations called
OR,AND,NOT and denoted by the symbols "+","." and "prime" respectively.
3. Boolean algebra enables the logic designer to simplify the circuit used achieving economy of
construction and reliability of operation.
4. Boolean algebra suggests the economic and straight forward way of describing the circuitary used in
any computer system.
5. Boolean algebra is unique in the way that , it takes only two different values either 0 or 1
* 0+ 0 = 0 * 0 +1 =1 *1+0 =1 *1+1= 1
* 0 = 1 * 1 = 0.
7. boolean properties.
1. x . 0 = 0 2. 0 . x = 0 3. x . 1 = x 4. 1 . x = x.
b. properties of OR function.
5. x+ 0 =x 6. 0 + x = x 7. x + 1 = 1 8. 1 + x = 1 9. 0 + =
d. commutative laws.
15. x . y = y . x 16. x + y = y + x
e. distributive laws.
f. associative laws.
g. absorption laws
h. demorgans laws.
* LITERAL : A primed or unprimed boolean variable is called literal. Each variable can have
maximum of two literals.
R.H.S = X.X+X.Z+X.Y+Y.Z
=X + XZ +XY +YZ
=X(1+Z)+XY+YZ
=X+XY+YZ [ 1+ Z = 1 ]
= X (1+Y)+(Y+Z) [1+Y= 1]
= X + YZ = L.H.S
22. X+ XY = X+ Y
L.H.S = X + XY
=(X + X)(X+Y)
=X+Y = R.H.S
23. X(X + Y) = XY
LHS = XX + XY = 0 + XY = XY =RHS
9. logics circuits can be simplified by simplifying the boolean equation using any one of the following
methods :
c) tabulation method
10. The properties of boolean algebra are useful for the simplification of boolean equation leading to
minimum structure.
XY + X (X+Y) = XY + XX + XY
= XY + XY
= (X+ X) Y = Y
DUALITY PRINCIPLE : The important property of boolean algebra is the duality principle.
It states that every algebraic expression deducible from theorems of boolean algebra remains valid if the
operators and identify elements are interchanged.
EXAMPLES:-
X + y= y + x xy=yx by duality
By duality
12. Standard product or minterm (M): consider two binary variables x and y combined with
an AND operation. Since each variable appears in direct form or in its complement form there are
four possible combinations X Y, X Y, X Y and XY. Each of these four AND terms is called a
minterm or a standard product.
X Y MINTERM m
0 0 XY m0
0 1 XY m1
m2
1 0 XY
1 1 XY m3
Standard sum or Maxterm (M): Two binary variables X and Y combined with an OR operation we will
an OR operation we will get four possible combinations X+Y, X+, +Y and +. Each of these four
OR terms is called a Maxterm or a standard sum term.
X Y Maxterm (M)
0 0 M0
X+Y
0 1 M1
X+
1 0 M2
+Y
1 1 M3
+
Each Maxterm is the compliment of its corresponding minters and vice versa.
Eg: - XY = Minterm
13. CANONICAL FORM: Expressing the Boolean function in standard sum of product form (SSPO)
or standard product of sums form (SPOS) is called canonical form.
1. A Boolean function may be expressed algebraically from given truth table by forming a minterm for
each combination of variables which produces 1 in the function, and then taking the OR of all those
terms.
X Y F
0 0 0
0 1 1
1 O 1
1 1 1
F(X, Y) = X + Y = m (1, 2)
This representation is called SSOP form. minterm or product of maxterm are said to be canonical form.
7. If the signals are propagating through two stages of gates, then it is called two level gate network.
Forms:
AND-AND AND
OR-OR OR
OR -NOR NOR
NOR -NAND OR
Realizing the minimal sum of products form of a function form truth table using Boolean
algebra
We are not sure that the given function or logical circuit is in its simplest form. It is possible to
design a circuit having less number of gates and inputs to realize the same function , then it saves
hard ware. Reduction at gate level is important.
IN PUTS OUTPUT
A B C F(A,B,C)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
*Here three input variables (A,B,C) are present. The possible minterms are 8.
They are:-
m0 = A B C (000), m1 = A B C (001), m2 = A B C (010), m3 = A BC (011) ,
m4 = A B C (100) , m5 = A B C (101) , m6 = AB C (110), m7 = ABC (111)
Each row in the truth table is a minterm . Output is true i.e 1 for 5 minterms. Output is false i.e 0
for 3 minterms. Function is expressed as a sum of minterms for which output is true i.e1
F ( A, B, C ) = A B C + A B C + A B C + AB C + ABC
(SOP)
= m(2,4,5,6,7)
NOTE; Reduction means reducing the number of terms and number of variables in each term. Our
goal is to make it as minimum sum of products beyond which we can not reduce further
F ( A, B, C ) = A B C + A B (C + C ) + AB (C + C )
= A B C + A B (1) + AB (C + C )
= A B C + A B + AB
= A B C + A( B + B )
= A B C + A(1)
= A B C+ A
= ( A+ A)( B C + A)
= (1)( B C + A)
= B C+ A
F ( A, B, C ) = A B C + A B C + A B C + AB C + ABC
= A B C + AB C + A
Alternative:- = ( A+ A) B C + A
= B C+ A
= A + BC
By using De Morgans Theorem ; we can use the minterms for which the output is false i.e 0. To
realise the function instead of using minterms for which the output is true i.e 1. Complement of the
function ( F ) is the sum of minterms for which the output is false i.e 0.
From this we can realize that the given function is the product of max terms for which output is false i.e
0. For max terms 0-variable ; 1- complement of variable.
A + B + C (000) M 0
A + B + C (001) M 1
A + B + C (011) M 3
Module-6
Simplification of Boolean functions
Map method of Boolean simplification
KARNAUGH maps( K-maps):
A BC 00 01 11 10
0 [ = 0][A=1]
1
Adjacency Rule:
Allowing only one of the variable to vary from one cell to neighbor cell in
horizontal and in vertical direction, but not diagonally
For ex: Assume output is true for minterms C and BC then we can combine these
minterms. = C + BC
= C(+B)
So we removed the variable which is varying from one cell to its neighbor cell.
Denoting 11 after 01 give a way to remove only one variable which is varying.
A B C F
First min term m0 ------ 0 0 0 0
Second min term- m1----- 0 0 1 0
Third min term- m2----- 0 1 0 1
Fourth min term m3----- 0 1 1 0
Fifth min termm4---- 1 0 0 1
Sixth min term ---m5----- 1 0 1 1
Seventh min term ----m6--- 1 1 0 1
Eighth min term ----m7 --- 1 1 1 1
BC 00 01 11 10
A
1
0
1 1 1 1
1
Combine the cells that are having 1, side to side or top to bottom and find which variable has
compliment in one cell and true in adjacent cell that variable can be eliminated.
(I) It is the sum of minterms 2 and 6
B + AB = B (+A) =B [here A only varies vertically]
A variable is eliminated.
[II] it is the sum of min terms 4,5,7 and 6 . here A remains constant and B and C varies with in these four
cells horizontally.
So II = A
Therefore, F = A+B
The given function is the sum of min terms 0,2,3,7,11,13,14,15 these are min terms for which output is
true i.e. 1 . in the map, map the cells corresponding to these min terms as 1 .
RS
PQ 00 01 11 10
00 1 1 1
1
01
11 1 1 1
1
10
NOTE: here 8th min term comes in last because we followed the denoting order 00, 01, 11, 10
1) Try to combine as many ones as possible in a given group, but they should all be adjacent.
2) Always start with a highest possible group of ones because sometimes the smaller group may
submerge with in the larger group.
3) We can combine a cell with 1 more than once.
4) Every one (1) should be included without leaving any one.
I-this is the maximum block of ones. Here PQ varies vertically and RS remains same. This is the combination of 3,
7, 15, 11. So we can eliminate variables PQ and RS remain in the final solution.
I= RS
II- this is the combination 13, 15. In it R only varies horizontally and PQS remains constant. So
II= PQS
III- this is the combination of 14,15. Here S varies horizontally. So III= PQR
IV- this is the combination 0,2. Here the logical adjacency exists between the cells 0 and 2 as IV=
F= RS + PQS + PQR +
Each of the product term (I, II, III, IV) which are combined to form sum of products is called an implicant.
Prime Implicant:- largest possible group ones. Implicants may be submerged into a prime implicants.
Essential Prime Implicant:- A group with at least one cell with truth value 1 has not been covered in any
prime implicant.
Those are the four essential prime implicants because they have at least one truth value 1 which is not
covered.
Note1:- To eliminate n variables there should be a combination of 2n adjacent cells having output as true i.e. 1
Note2:- An essential prime implicant covering all min terms having unique minimal form
Eg:- F= m(12,15,13,7,15,6,11)
Note3:- For the given function in K-map every min term is covered exactly by two prime implicants such a K-map
is called cyclic.
Module-7
VARIABLE MAPS
INTRODUCTION:
In the last lecture we introduce the map method of boolean simplification. we
use a karnaugh map which is a graphical representation of a truth table, filled this graph
with 1's corresponding to the cells whose minterms had a output true. The object is to
identify groups of 1's as large as possible with satisfying the adjacency rule.
possible group.
m0 m1 m3 m2
m4 m5 m7 m6
m8 m9 m11 m10
Grouping two adjacent squares containing 1's represents a term of three literals.
Grouping four adjacent squares containing 1's represents a term of two literals.
Grouping eight adjacent squares containing 1's represents a term of one literal.
Grouping sixteen adjacent squares containing 1's represents the function=1(a term
of zero literals).
PRIME IMPLICANTS:
In choosing adjacent squares in a map, we must ensure that
1. All the minterms of the function are covered when we combine the squares.
3. There are no reduntant terms. some times there may be two or more expressions that
satisfy the simplification criteria.
By following the procedure used for the five variable map ,it is possible to
construct a six variable map with 4 four variable maps to obtain the required 64 squares.
Maps with six or more variables need too many squares and are impractical to use. the
alternative is to employ computer functions with large number of variables.
Module-8
CODE CONVERTERS
INTRODUCTION:
We have seen the techniques for reduction of boolean functions by using
boolean algebra as well as kmaps. The object is to design circuits as per the given
specifications by using these techniques.
There are two types of the digital circuits i.e., combinational and sequential
circuits. Combinational circuits are the circuits whose output is based on the inputs and
the sequential circuits are the circuits whose output is depends on the input and as well as
the previous behaviour of the circuit.
Example:
When we speak into cellular phone, an encoder converts the sound of our voice
into electrical signals. which can travel very fast over very long distances. When the
electrical signal get to another cellular phone, a decoder converts the electrical signal
back to the sound of our voice.
So code converters are used for more than protecting private information from
spies.
The class of codes which are used for simplification of hardware one is called
excess-3 code and other is called gray code.
BCD EXCESS-3
b3 b2 b1 b0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
1 1 1 1 X X X X
Now we will have to take each of the values E0,E1,E2,E3 and find out the logic
function which can represent E0,E1,E2,E3 in terms of b0,b1,b2,b3.
E0,E1,E2,E3 = f(b0,b1,b2,b3)
Decimal D C B A G3 G2 G1 G0
number
Rajiv Gandhi University of Knowledge Technologies Sk.Riyaz Hussain Page 43
CS2201 Switching Circuits and Logic Design
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
GRAY CODE:
The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the code changes when moving from one code to the next. The gray
code is non weighted code, as the position of bit does not contain any weight. The gray
code is a reflective digital code which has the special property that any two subsequent
numbers codes differ only by one bit. This is also called a unit distance code. In digital
gray code it has got a special place.
Step 5: in previous step carry is occured so neglect that carry. Note that dont add
Module-9
PARITY GENERAROR
Parity Generator:
A parity bit is used for the purpose of detecting errors during transmission of binary
information .A parity bit is an extra bit included with a binary message to make the
number of is either odd or even. The message including the parity bit is transmitted and
then checked at the receiving end for the errors. An error is detected if the checked
parity does not correspond with the one transmitted
The circuit the generates the parity bit in the transmitter is called a parity generator and
the circuit that checks the parity in the receiver is called parity checker.
In even parity the added parity will make the total number of 1s an even number of
amount and odd parity the added parity bit will make the total number of 1s an odd
amount it is not necessary that should odd parity has one and even parity as zero as
long as there is a complete understanding between sender and receiver these called
protocol they no what is the number of bits we sending they should also know whether
you send parity bit or not at the end of group. And also know odd parity or even parity.
In a three bit odd parity generator the three bits in the message to ether with the parity
bit are transmitted to their destination, where they are applied to parity checker circuit
.the parity checker circuit checks for errors in the transmission.
Since the information was transmitted with odd parity the four bits received must have
an odd number of 1s an error occurs during transmission if the four bits received have n
even number of 1s,indicating that one bit has changed during transmittion.The output of
parity of the parity checker is denoted by PEC(parity
Error checker) and it will be equal to 1 it an error occurs it the four, bits received has an
even number of is.
Input output
A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
P (A,B,C)= (0,3,5,6)
From k.map
P= ABC+ABC+ABC+ABC
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CS2201 Switching Circuits and Logic Design
= A (BC+BC) + A (BC+BC)
= AP+AP
= A P
= A BC
Circuit Diagram:
Every where we are using decimal numbers.In this circuit the inputs are
decimal to we have to use decimal to binary converter.A display is made up of an LED
independent on other leds.We need 7-outputs from circuit for 7 segments.
INPUTS OUTPUTS
A B C D a B c D e f G
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 0 1 1 1 0 0 1 1
a = A + BD + CD + B D b = B + C D + CD
c = B + C+ D d = B D+ C D+ B C + B C D
e = B D+ C D f = A + C D+ B C + B D
g = A + B C+ B C + C D
There are so many gates common for some segments.So make as many as common
terms and rest of them are cant be accommodated with them.Make that common
terms unique and reduce design effort.
Module-10
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CS2201 Switching Circuits and Logic Design
ARITHMETIC CIRCUITS
Arithmetic circuits:
1. Half adder
2. Full adder
1. Half adder:
Half adder is one which can only take two digits and add the sum and
get the carry and not taking carry of previous position of addition.
A logic circuit for the addition of two one bit numbers is referred to as
an half adder.
A and B are the two inputs and s(sum) and carry(c) are the outputs
S=A+B
A B S C
0 1 1 0
1 0 1 0
1 1 0 1
Carry is when we have a digit over flowing that over flow has to accomdated
else where in the next time computation stak.you have to take into account
this over flow.
Circuit Diagram:
S=A B
C=AB
The half adder is used for 1 bit addition.No practical use except for every
first bit position.It not used for multibit number.To over come this we need
another circuit known as full adder.Half adder has only two inputs and there
is no provision to add a carry coming from the lower order bits when multibit
addition is performed.
For this purpose a 3rd input terminal is added and this circuit is used to add
An,Bn and Cn-1 where An and Bn are nth order bits of numbers A and B
respectively and Cn-1 is the carry generated from addition of (n-1)th order
bits.this circuit is refered to as full order.
Sum=A B Ci
Carry C0=AB+BC+CA
=AB+Ci(A+B)
C0=AB+Ci(A A B )
But we will use this occasionally for to know next carry to reduce time delay
Circuit Diagram:
In this circuit carry in is the carry out of previous addition such a adder
which take carry from previous addition is called full order.
Truth table:
A B Cin S C0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
But we mainly consider carry propagation delay because the carry has
to propagate through are the gates but no need of sum propagation.The sum
has to leave in every stage.
The very first carry of total circuit we will take as 0 and to calculate
sum in every stage we need carry out of previous stage so there is a delay of
carry propagation.
Module-11
CARRY LOOK A HEAD ADDERS
Propagation delay is the average transition delay time for a signal to propagate from input to output.It is the
time delay between the application of a level change at the input and the change of state at the output of a
circuit. This propagation delay depends on the lenth of signal path or the length that the signal has to traverse
from input to the output.
When we would like to design faster system or faster circuits, the propagation delay has to be taken into
consideration where the length of the paths that the signal is going to traverse has to be reduced.
A carry look ahead adder is a type of adder used in digital logic that imp roves speed by reducing the amount
of time required to determine carry bits. consider for example a four fit adder where a carry bit is calculated
along the sum bit, and each bit must wait until the previous carry has been caluclated.
Here in this adder each bit will not wait for previous carry but looks carry ahead and thus reduces the wait time
to calculate the result. For example consider,
A = A3 A2 A1 A0
B = B3 B2 B1 B0
C3 S3 S2 S1 S0
A B Ci C0
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0 A B = 1 is Ci = 1
1 0 1 1
1 1 0 1
1 1 1 1 Both A & B are 1 , AB = 1
Here the carry output is 1 if A & B are 1 irrespective of the previous carry and the carry output is 1. If
Co = AB + (A B) Ci = G + PCi
If A and B are 1 then irrespective of the carry input the output carry is generated . so , we refer to it as carry
generate.
If A B I is 1 and ci=1 then output is generated that means the carry is generated based on the previous
+
carry that is propagrated. So, we refer to it as carry propagate.
B3 A3 B2 A2 B1 A1 B0 A0
CI Cin C-1
C2 C1 C0
C3
Ci = Gi + Pi Ci-1
C0 = G0 + P0C-1
C1 = G1 + P1C0 = G1 + P1G0 + P1P0C-1
C2 = G2 + P2C1 = G2 + P2(G1+P1G0+P1P0C-1)
C3 = G3 + P3C2 = G3 + P3G2+P3 P2 (G1 + P1G0 + P1 P0 C-1)
Now from each Pi , Gi and C-1 we can generate each Ci from the set of equations that we have derived earlier .
so now the 4-bit adder can be remolded as.
So, carry look ahead adder is one of basic techniques to improve speed of addition. In the basic adder
We have to wait for previous carries which is in contrast with this technique as it just the matter of extra
combinational logic.
Fan in : no. of inputs can give to a gate without any degradation in the performance.
Fan out : no.of outputs you can take from a gate to feed similar gates without degradation in the
performance of output.
Though CLA adder is quite advantareous regarding speed or the performance it has two
disadvantares.
Module-12
12. SUBSTRACTORS
COMPLEMENTS :
In digital systems complements are used for simplifying the subtraction operation and for
logical manipulation. There are two types of complements for each base-r system. The first is referred
to as the rs complement and the second as the (r-1)s complement.
For binary numbers of radix 2 the two types are referred to as 2s complement and for decimal
numbers the two types are referred to as 10s complement and 9s complement.
RADIX COMPLEMENT :
The rs complement of an n-digital number N in base r is defined as rn-N , for N 0 and 0 for N=0
.
9s complement = (103-1)-729=999-729=27010
In the direct method of subtractions we use the barrow concept which is less efficient than
method that uses complements so, now we turn our attention towards indirect method of subtraction
that uses complements.
Let us consider the substraction of two signed numbers M,N in base r. there 2 cases will occur. They
are if 1) M>N 2) M<N
CASE 1 :
M+(rn N ) = M N + rn
The above sum will produce an end carry , rn, which can be discarded
N = 0011 -----------------3
2 s compliment of N= 1100+1=1101
Without discarding carry the sum will be M+(rn-N) which rearranged as M-N+rn. so, inorder to obtain M-N, rn
should be removed.
M-N = M+(rn-N)-rn
M and 2s complement of N. so we need to add 1 to 2s complement the number inorder to do so we utilize the
discarded overfilow that means in the sense we bring the carry around and add this to the sum that is obtained
in the previous step. After adding the carry to the list significant digit of the sum we obtained desired result.
Remember that if the discarded bit is 1 , the result is positive . if the discarded bit is 0, the result is
negative.
CASE 2 :
Here M<N and the sum doesnt produce an end carry and is equal to M+(rn-N) which can be rearranged
as rn (N-M) that means the sum is rth complement of (N-M).
MODULE-13
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CS2201 Switching Circuits and Logic Design
Here Most Significant Bit is singed bit and remaining three are magnitude bits.
If MSB is Zero then number is greater than or equal to zero (>=) that is positive.
If MSB is one then number is less than Zero (<) that is negative.
Ex: (1) b3 b2 b1 b0 if b3 is '0' then it is "positive".
if b3 is '1' then it is "negative".
(2) Q: 0 0 0 1
A: + 1
(3) Q: 0 1 0 1
A: + 5
(4) Q: 1 0 1 1
A: - 6
Here MSB is '1", it is negative. So we have to do 2's complement.
Q: 1 0 1 0
1's complement of number 101
2's complement of number 1 1 0 (101+1)
Therefore 1010 is -6
In 4- bit representation, we have only three magnitude bits.
So, The maximum "+ve" number is +7 "0111"
Ex: (1) + 5 : 0 1 0 1
(2) + 7 : 0 1 1 1
(3) - 5 : 1 0 1 1
1 0 0 ( 1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 1 0 1 (-5)
(4) - 8 : 1 0 0 0
1 1 1 (1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 0 0 0 (-8)
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 0 0 0 1 0
3 0 0 0 1 1 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 0 0 1 0 1
6 0 0 1 1 0 0 0 1 1 0
7 0 0 1 1 1 0 0 1 1 1
8 0 1 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
10 0 1 0 1 0 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 1 0 0 1 1
14 0 1 1 1 0 1 0 1 0 0
15 0 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1
In this conversion, upto '9' the BCD number is same as the binary number.
When the sum is greater than '9', we obtain non - valid BCD representation. so, the addition of binary
6 (0110) to the binary sum, converts it to the correct BCD representation and also produces an out
put carry as required.
The logic circuit that detects the necessary correction can be derived from the table entires.
S*3 S*1 = 1
When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next
stage.
BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.
BCD adder must include the correction logic in its internal construction.
The two decimal digits, together with the input carry are first added in the top 4 - bit binary adder to
produce the binary sum.
When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one,
binary 0110 is added binary sum through the bottom 4 - bit binary adder.
The output carry generated from the bottom binary adder can be ignored, since it supplies
information already available at the output carry terminal.
The BCD adder can be constructed with three IC packages. Each of the 4- bit adder is an MSI
function and the three gates for the correction, logic need one SSI package. However, the BCD adder
is available in one MSI circuit. To achieve shorter propagation delays, an MSI BCD adder includes
the necessary circuits for look - ahead carries.
The adder circuit for the correction does not need all four full - adders, and this circuit can be
optimized within IC packages.
NOTE :
A decimal parallel adder that adds 'n' decimal digits need ' n' BCD adder stages.
SUMMARY :
MODULE 14
ARRAY MULTIPLIER
ARRAY MULTIPLIER:
This array is used for the nearly simultaneous addition of the various product
terms involved. To form the various product terms, an array of ' AND' gates is used
before the adder array.
The main advantage of array multiplier over traditional bit serial multipliers is, it
improves the speed.
Shift and add several times - working all with same times.
EXAMPLES
a1 a0 ------- multiplicand
b1 b0 ------- multiplier
a1 b 0 a0 b 0
a1 b 1 a0 b1
p3 p2 p1 p0 ------- product
p0 = a0 b0
p1 = a1 b0 + a0 b1
LOGICAL DIAGRAM :
HA = half adder
c = carry
s = sum
a2 a1 a0 ------- multiplicand
b2 b1 b0 ------- multiplier
a2 b0 a1 b0 a0 b0
a2 b1 a1b1 a0 b1
p5 p4 p3 p2 p1 p0 product terms
p0 = a0 b0
p1 = a1 b0 + a0 b1
p2 = a2 b0 + a1 b1 + a0b2 + c1
p3 = a2 b1 + a1b2 + c2
p4 = a2b2 + c3
p 5 = c4
where c1, c2, c3, c4 are carry generators during the addition for p1, p2, p3, p4
respectively.
LOGIC DIAGRAM :
Where
HA = half adder
FA = full adder
c = carry
s = sum
a3 a2 a1 a0
b3 b2 b1 b0
a3b0 a2 b0 a1 b0 a0 b0
a3b1 a2 b1 a1b1 a0 b1
p7 p6 p5 p4 p3 p2 p1 p0
Logic Diagram
= 2 * 2= 4
= 3*2
= 6
Numbers of 'HA' = n
Even through it improves the speed, still there is a level of delay invovled in an
array multiplier before the final product is achieved. That is
CONCLUSION :
Array multiplier is an electronic circuit used in digital electronics to
multiply two binary numbers.
ADVANTAGE :
It improves the speed.
DISADVANTAGE :
Even though it improves the speed it has some propagation delay.
SUMMARY :
Array multiplier definition
Advantages and disadvantages of array multiplier.
Examples of Array Multiplier.
Knowledge about m * n array multiplier.
Module-15
Rajiv Gandhi University of Knowledge Technologies Sk.Riyaz Hussain Page 80
CS2201 Switching Circuits and Logic Design
In sequential circuits present output depends on present outputs and past outputs of
the system where as in combinational circuits output is influenced only by present
inputs. This is the difference between combinational circuits and sequential circuits.
There are two main types of sequential circuits and their classification depends on the
timing of their signals. A synchronous sequential circuit is a system whose behavior can
be defined from the knowledge of its signal at discrete instant of time. The behavior of
an asynchronous sequential circuit depends upon the input signals at any instant of time
and the order in which the inputs change. The storage elements commonly used in
asynchronous sequential circuits are time delay devices. Thus, an asynchronous
sequential circuit may be regarded as a combinational circuit with feedback. Because of
the feedback among logic gates, an asynchronous sequential circuit may become
unstable at times.
A synchronous sequential circuit employs the signal that affects the storage elements
only at discrete instant of time. Synchronization is achieved by a timing device called a
clock generator. That provides a periodic train of clock pulses. The clock pulses are
distributed throughout the system in such way that storage elements are affected only
with arrival of each pulse.
LATCHES
The basic storage (memory) elements are latches. The latches introduced here basic
circuits from which all flip-flops are constructed. Although latches are useful for storing
binary information and for the design of asynchronous sequential circuits, they are not
practical for used in synchronous sequential circuits.
SR LATCH
The SR latch is a circuit with two cross-coupled NOR gates or two cross coupled NAND
gates. It has two inputs labeled S for SET and R for RESET. In digital language SET
means output is 1 and RESET means output is 0. This latch has two useful states.
When the output Q=1 and QI=0, is said to be SET. When the output Q=0 and QI=1,
is said to be RESET. The each outputs Q and QI are normally the complement of each
other. How-ever when both inputs are equal to 1 at same time, an undefined state with
both outputs equal to 0 occurs.
When S=0 and R=0 the outputs are depends upon previous output of Q and QI. it is
called memory state.
Rajiv Gandhi University of Knowledge Technologies Sk.Riyaz Hussain Page 82
CS2201 Switching Circuits and Logic Design
When S=1 and R=0 the outputs Q=1 and QI=0 respectively it is called SET state.
When S=0 and R=1 the outputs Q=0 and QI=1 respectively it is called RESET state.
When S=1 and R=1 the outputs are 0. it is called invalid state. Because of Q and QI
should be complement to each other.
FLIP-FLOPS
A flip flop circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit) until directed by an input signal to switch states. The major differences
among various types of flip-flops are in the number of inputs they posses and the
manner in which the inputs effect the binary state.
SR FLIP-FLOP
The operation of the basic flip flop can be modified by providing additional control input
that determines when the state of the circuit is to be changed. An RS flip-flop with a
clock pulse (cp) input is shown.
The pulse input acts as an enable signal for the other two inputs.
Let us assume previous output is zero for starting time. At t1 cp and S=0 and R=1 so Q=0
until t2 and now cp=0 means it assigns its previous state i.e. Q as 0. In this SR flip-flop
flip to
get output as 1 we have to supply two inputs S and R as 1,0 respectively. To avoid this
we have another flip-flop
flop called D
D-flip-flop.
When clk =1
When clk =0, it gives the previous output and it is known as memory state.
1. SET operation
2. RESET operation
3. MEMORY operation
4. TOGGLE operation
All these operations can be performed by JK-flip-flop. Before going to JK-flip-flop, let us
look at this special or modified SR-flip-flop.
Toggle means complement of previous outputs. Here one disadvantage that is while S, R
and clk are at logic level 1 , it gives output Q ,QI, Q ,QI, Q ,QI............ and this
phenomenon is called RACING.
Changing states from Qn to QnI or QnI to Qn is known as toggling and when this happens
continuously it is called Racing.
Race is uncontrollable
Toggle is controllable
If we can control racing phenomenon then it is useful. It can be done by restricting the
output to clock periods means the output is effected by inputs only once at a clock
period.
If clock on time < propagation delay of flip-flop then racing can be avoided.