EE141

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ProjectPhase 1 Done Thanks for the timely

response.
Phase 2 to be announced We Launched on
Fr.
Hw 6 due on Fr.

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Last lecture
Pass transistor logic
CMOS Layout
Todays lecture
Ratioed Logic
Dynamic Logic
Reading (Ch 6)

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Goal: build gates faster/smaller than static

complementary CMOS
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Rising and falling delays arent the same

Calculate LE for the two edges separately

For tpLH:
Cgate = WCG Cinv = (3/2)WCG LELH =

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What is LE for tpHL?

Switch model would predict Reff = Rn||Rp
Would that give the right answer for LE?

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vo(t)/VDD

Rp=Rn

Rp=2Rn
Rp=4Rn
Rp=

t
Time constant is smaller, but it takes more time
to complete 50% VDD transient (arguably)
Rp actually takes some current away from
discharging C
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Think in terms of the current driving Cload

When you have a conflict between currents

Available current is the difference between the two
In pseudo-nMOS case:

(Works because Rp >> Rn for good noise margin)

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For tpHL (assuming Rsqp = 2Rsqn):

Rgate = Rn/(1-Rn/Rp) = 2Rn Rinv = Rn
Cgate = WCG Cinv = 3WCG
LEHL =
LE is lower than an inverter!
But have static power dissipation

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Differential Cascode Voltage Switch Logic (DCVSL)

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XOR/XNOR gate

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In static circuits, at every point in time (except

when switching) the output is connected to
either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary

storage of signal values on the capacitance of
high impedance nodes.
only requires n + 2 (n+1 N-type + 1 P-type)
transistors

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off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

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Once the output of a dynamic gate is

discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.

Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL

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Logic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary
CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
reduced capacitance due to lower input capacitance (Cin)
no Isc, so all the current provided by PDN goes into discharging CL

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Clk Clk
Out Out

In CL A CL

B
Clk
Clk

Cgate = Cgate =
LE = LE =

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Overall power dissipation usually higher than static

CMOS
no static current path ever exists between VDD and GND
(including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock

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CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

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Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

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Clk Mp Mkp

Out
A Out
CL

Clk Me

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Charge initially stored on CL Clk Mp

CA previously discharged Out
A CL

B=0 CA

Clk Me CB

When A rises,this charge is redistributed (shared)

between CL and CA
Makes Out drop below VDD

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VDD
Two cases:
Ma stays on complete charge share
Clk Mp Ma turns off incomplete charge share
Out
Complete charge share:
CL QCa = VOutCa
A Ma QCL = -VOutCa
X
VOut = -VDDCa/(Ca+CL)
Ca
B=0 Mb Incomplete charge share:
QCa = (VDD-VTN*)Ca
QCL = -(VDD-VTN*)Ca
Cb
Clk Me
VOut = -(VDD-VTN*)Ca/CL

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Clk Mp Mkp Clk

Out
A

Clk Me

Keeper helps a lot

Can still get failures if Out drops below inverter Vsw
Another option: precharge internal nodes
Increases power and area

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Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.

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Clock feedthrough
Clk
Out
In1
In2
Voltage

In3 In &
Clk
In4 Out
Clk
Time, ns
Clock feedthrough

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Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

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Out1
Voltage

Clk

In Out2

Time, ns

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Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

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Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0 1 transitions allowed at inputs!

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Clk Mp Clk Mp Mkp

11 Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

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Only non-inverting logic can be implemented

Very high speed
static inverter can be skewed, only L-H transition
critical
Input capacitance reduced smaller logical effort

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Designing with Domino Logic

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