EE141

EECS141
EE141 Lecture #12 1

HW 4 Due Today. New HW today as well.

Final Lab next week
Project to be launched on Wednesday!
Probably is wise to be in class that day.

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2.5

2
Wider
PMOS
1.5
Vout(V)

Symmetrical

1
Wider
NMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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2.5

2
Fast PMOS
Slow NMOS
1.5
Vout(V)

Nominal

1
Fast NMOS
Slow PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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Not all transistors are alike

Impacts parameters such as reliability and performance

Define process corners: SS, FF, SF, FS

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Discharging a capacitor

We modeled this with:

tp = ln (2) RC

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Real transistors arent exactly resistors

Look more like current sources in saturation

Two questions:
Which region of IV curve determines delay?
How can that match up with the RC model?

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With a step input:

VDD VDD/2 ID VGS = VDD

VDS
VVSAT VDD /2 VDD

Transistor is in (velocity) saturation during entire transition

from VDD to VDD/2

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In saturation, transistor basically acts like a current source:

VOUT
VOUT
VDD
IDSAT C
VDD/2

t
tp

VOUT = VDD - (IDSAT/C)t tp = C(VDD/2)/IDSAT

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Including output conductance:

VOUT

IDSAT 1/(IDSAT) C

For small :

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Transistor current not linear on VOUT how is the RC

model going to work?

Look at waveforms:

Voltage looks like a

ramp for RC too

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Match the delay of the RC model with the actual delay:

Often just:

Note that the book uses a different method and gets

0.75VDD/IDSAT instead of ~0.72VDD/IDSAT.

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Capacitance models important for analysis

and intuition
But often need something simpler to work with
Simpler model:
Lump together as effective linear capacitance to
(ac) ground
In most processes: Cg = Cd = 1.5 2fFW(m)

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As Vin increases, Vout drops

Once get into the transition region, gain
from Vin to Vout > 1

So, Cgd experiences voltage swing

larger than Vin
Which means you need to provide more
charge
Makes Cgd look larger than it really is

Known as the Miller Effect in the

analog world

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Can calculate Cg, Cd based on tech. parameters

But these models are simplified too
Another approach:
Tune (e.g., in spice) the linear capacitance until it
makes the simplified circuit match the real circuit
Matching could be for delay, power, etc.

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For gate capacitance:

Make inverter fanout 4
Adjust Cload until Delay1 = Delay2
For diffusion capacitance
Replace inverter A with a diffusion capacitance load

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Why did we need that last inverter stage?

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tpHL = 0.69 CL Reqn

tpLH = 0.69 CL Reqp

tpLH tpHL

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Derived RC model assuming input was a step

But input is not a step
Transistor turns on gradually

Lets look at gate switching more carefully

Use our models to understand the effect of input slope

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One way to analyze slope effect

Plug non-linear IV into diff. equation and solve
Simpler, approximate solution:
Use VT* model

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For falling edge at output:

For reasonable inputs, can ignore IPMOS
Either Vds is very small, or Vgs is very small

So, output current ramp starts when Vin=VT*

Could evaluate the integral
Learn more by using an intuitive, graphical
approach

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For reasonable input slopes:

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For reasonable
input slope
Model matches
Spice very well

Model breaks with

very large tr
Input looks DC
traces out VTC
Have other problems here anyways
Short-circuit current

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Switching power
Charging/discharging capacitors
Leakage power
Transistors are imperfect switches
Short-circuit power
Both pull-up and pull-down on during
transition
Static currents
Biasing currents, in e.g. analog, memory

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VDD

Vin
Vout
CL

One half of the energy from the supply is

consumed in the pull-up network, one half is
stored on CL
Energy from CL is dumped during the 10
transition
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Power = Energy/transition Transition rate

= CLVDD2 f01

= CLVDD2 f 01
= CswitchedVDD2 f

Power dissipation is data dependent depends

on the switching probability
Switched capacitance Cswitched = CL 01

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Energy consumed in N cycles, EN:

EN = CL VDD2 n01

n01 number of 01 transitions in N cycles

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