EE2801 -- Lecture 19

An Introduction To The
PIC Microcontroller

EE2801-L19P01
 The PIC 1 8 erie Microcontroller

The PIC Series of microcontrollers is representative of the current industry trend towards

highly capable, low-cost, processors for embedded applications. Although they are not

suited to everything, they can do a lot!

However, they are quite a bit different that what were used to at this point!

Some of the characteristics of the PIC 16F87X series are:

Only 35 instructions!

All instructions (except branch) execute in 1 cycle.

Eight level deep hardware stack.

4K word program space, 192 bytes of RAM

Internal A/D converter, serial port, digital IO ports, timers, and more!

Remember, what you are about to see will look completely different than anything youve

seen so far!

However, all of the techniques weve used and the concepts weve learned are directly

applicable!

EE2801-L19P02
 The PIC 1 8 il C ilitie

The following table summarizes the capabilities of the PIC16F87X series components.

Although when we use the compiler well set the processor type to 16F877, thats only

because each component in the family is compatible. The actual version well use is the

PIC16F874:

PIC1 8

Key Featu res

PICmi c ro Mid-Range Referenc e PIC16F873 PIC16F874 PIC16F876 PIC16F877
Manu al (DS33023)

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz

Resets (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)

FLASH Program Memory 4K 4K 8K 8K

(14-bit words)

Data Memory (bytes) 192 192 368 368

EEPROM Data Memory 128 128 256 256

Interrupts 13 14 13 14

I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E

Timers 3 3 3 3

Capture/Compare/PWM modules 2 2 2 2

Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART

Parallel Communications - PSP - PSP

10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels

Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions

EE2801-L19P0
 The PIC1 8 Architecture
13 Data Bus 8 PORTA
FLASH Program Counter
RA0/AN0
Program RA1/AN1
Memory RAM RA2/AN2/VREF-
8 Level Stack File RA3/AN3/VREF+
(13-bit) Registers RA4/T0CKI
RA5/AN4/SS
Program 14
Bus RAM Addr (1) 9 PORTB
RB0/INT
Instruction reg Addr MUX RB1
RB2
Direct Addr 7 Indirect RB3/PGM
8 Addr RB4
FSR reg RB5
RB6/PGC
STATUS reg RB7/PGD
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
3 MUX RC2/CCP1
Power-up RC3/SCK/SCL
Timer RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer ALU RC6/TX/CK
Control Power-on RC7/RX/DT
Reset 8 PORTD
Timing Watchdog W reg
Generation Timer
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset RD7/PSP7:RD0/PSP0
In-Circuit
Debugger
Low-Voltage
Programming Parallel Slave Port PORTE

RE0/AN5/RD
RE1/AN6/WR
MCLR VDD, VSS RE2/AN7/CS

Device Program Data Memory Data

Timer0 Timer1 Timer2 10-bit A/D FLASH EEPROM
PIC16F874 4K 192 Bytes 128 Bytes
PIC16F877 8K 368 Bytes 256 Bytes

Data EEPROM Synchronous USART

CCP1,2 Serial Port
EE2801-L19P0
 The PIC1 8 Pro r And t c Me or M

Instead of having a large memory space outside the processor and a small memory space
inside the processor (the registers) like we do in the 80x86, the PIC does two things. First,
it divides memory into two main spaces: program memory and data memory. For program
memory, the map looks as follows:

PC<12:0>

CALL, RETURN 13

RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector 0000h

Interrupt Vector 0004h

0005h
Note: The unused space in
Page 0
On-Chip

Program
07FFh this memory map is used in
Memory 0800h other family processors.
Page 1

0FFFh
1000h

1FFFh

EE2801-L19P0
 EE2801-L19P06

File
Address
Indirect addr. (*) 00h Indirect addr.(*) 80h Indirect addr. (*) 100h Indirect addr. (*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
The PIC16F874 Register File Map

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h 107h 187h
PORTD (1) 08h TRISD (1) 88h 108h 188h
PORTE (1) 09h TRISE (1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh
TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h SSPCON2 91h
T2CON 12h PR2 92h
SSPBUF 13h SSPADD 93h
SSPCON 14h SSPSTAT 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah 9Ah
CCPR2L 1Bh 9Bh
CCPR2H 1Ch 9Ch
CCP2CON 1Dh 9Dh
ADRESH 1Eh ADRESL 9Eh
ADCON0 1Fh ADCON1 9Fh
120h 1A0h
20h A0h
General General
Purpose Purpose accesses accesses
Register Register
20h-7Fh A0h - FFh
96 Bytes 96 Bytes 16Fh 1EFh
170h 1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
 e i ter In The PIC Microcontroller

Value on
Value on:
A ddr es all ot her
Name Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
s resets
BOR
(2)

Ba nk 0

00h
(4)
INDF Addressing this location uses contents of FSR to address data mem ory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 modules register xxxx xxxx uuuu uuuu
02h
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h
(4) STATUS IRP RP1 RP0 TO PD Z D C C 0001 1xxx 000q quuu
04h
(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h
(5)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h
(5)
PORTE R E2 RE1 RE0 ---- -xxx ---- -uuu
0Ah
(1,4)
PCLATH Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh
(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 (6) EEIF BCLIF CCP2IF -r-0 0--0 -r-0 0--0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11 h TMR2 Timer2 modules register 0000 0000 0000 0000
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Por t Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCO N WCO L SSPOV SSPEN CKP SSPM 3 SSPM2 SSPM1 SSPM 0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON CCP1X CCP1Y CCP1 M3 CCP1 M2 CCP1 M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON CCP2X CCP2Y CCP2 M3 CCP2 M2 CCP2 M1 CCP2M0 --00 0000 --00 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0
GO/

DONE
A DON 0000 00-0 0000 00-0

EE2801-L19P0
o To e l ith All The e e i ter

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit
bit7 bit0
U = Unimplemented bit,
read as 0

- n= Value at POR reset

bit 7: IRP:
Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit ( ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit ( ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of
the second operand. For rotate ( RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.

EE2801-L19P08
An E le PIC- ed te

EE2801-L19P09