XU et al.

: COMPACT AC MODELING AND PERFORMANCE ANALYSIS OF THROUGH-SILICON VIAS IN 3-D ICs 3407

and interface charge can be written as


(rvia + tox + wdep )2 (rvia + tox )2 qNa
2(rvia + tox )Qi
= [V ms (rvia +tox )]
tox
2ox / ln 1 + (3a)
rvia
while the electrical potential at the Si-SiO2 interface can be
expressed as
(rvia + tox )   
qNa wdep Fig. 3. Electrostatic result of a TSV surrounded by SiO2 and p-type Si:
= (rvia + tox + wdep ) ln 1 +
2
(a) depletion width and (b) middle-frequency (MHz) capacitance as a func-
2Si r + tox
via tion of the bias voltage and Si/SiO2 interface charge density (Qi ). [rvia =
1 2 2.5 m; tox = 0.5 m; the barrier metal is Ta (a work function of 4.25 eV); the
wdep wdep (rvia + tox ) . (3b) Si bulk resistivity is 10 -cm (Na = 1.25 1015 cm3 , which corresponds
2 to a work function of 4.89 eV)].
One can also interpret (3) through its physical implications: (3a)
essentially represents Gausss law, while (3b) is the integration Similarly, the electrostatics of the TSV surrounded by an
of the Poisson equation (1) in the depletion region. There are n-type Si substrate can also be obtained. In particular, (3) and
two unknowns in the two equations of (3), i.e., wdep and the (4) can be replaced by the following: in depletion condition, we
potential drop in the depletion region (rvia + tox ), which can have (6), shown at the bottom of the page, whereas the condition
be solved self-consistently. For the maximum depletion region with maximum depletion region is
condition, the electrical potential drop across the depletion   
2kB T Nd qNd 1 2
region can be written as ln = wdep wdep (rvia + tox )
   q ni 2Si 2
2kB T
ln
Na
=
qNa 1 2
wdep wdep (rvia + tox )  
q ni 2Si 2 wdep
  + (rvia + tox + wdep )2 ln 1 + . (7)
wdep rvia + tox
+ (rvia + tox + wdep )2 ln 1 + (4)
rvia + tox Using (3) and (4) or (6) and (7), we can obtain the
where ni is the intrinsic carrier concentration of Si. Here, the wdep of a TSV with typical geometrical parameters (rvia =
physical meaning of (4) is similar to that in (3b), but (rvia + 2.5 m, tox = 0.5 m) and surrounded by either p-type or
tox ) is almost fixed at 2F = (2kB T /q) ln(Na /ni ). Con- n-type Si (bulk resistivity is 10 -cm). The results of wdep
sequently, the middle-frequency capacitance3 per unit height as a function of the bias voltage (V ) are shown in Figs. 3(a)
between the TSV and the substrate (CMF ) can be obtained [3] and 4(a), while the middle-frequency CV curves are shown in
as follows: Figs. 3(b) and 4(b). It can be observed that a significant error
 1 in capacitance will be induced if the depletion region is not
1 1
CMF = + considered. Notice that the capacitance is not only dependent
Cox Cdep
     1 on geometrical parameters but also on the Si/SiO2 interface
1 tox 1 wdep charge, semiconductor type, and bias voltage.
= ln 1+ + ln 1+ .
2ox rvia 2Si rvia +tox Our MOS effect model is verified against the experi-
(5) mental and numerical simulation results in [14, Fig. 3(b)].
With the parameters provided in [14] (rvia + tox = 2.5 m;
tox = 118.2 nm; Na = 2 1015 cm3 ; ox = 3.90 ; and TSV
3 The middle-frequency capacitance is equivalent to the high-frequency
height = 20 m), the calculated capacitance in accumulation
capacitance of MOS capacitors in semiconductor device physics: at such
frequencies (1 MHz), the generation/recombination of inversion carriers or condition using our model is 89.6 fF, as compared to 89 fF from
the charging/discharging of interface states cannot follow the fast signals. the numerical simulation and 84 fF from measurement result
However, the term high frequency has different meanings in this paper: at in [14]; the calculated capacitance for the maximum depletion
such frequencies (> 1 GHz), the ac conduction of bulk Si takes effect on
the capacitance and conductance of the TSVs. To avoid conflict, we use the region condition, using our model is 36.1 fF, as compared to
term middle frequency to represent the previous case. In addition, this paper 37 fF from the numerical simulation and 34 fF from measure-
assumes a small signal capacitance at all frequencies (not the deep depletion ment result in [14].
mode capacitance), because the power supply (or realistic bias) voltage (VDD ,
around 1 V) is usually less than the difference between the threshold voltage As explained in the introduction, the Si-SiO2 interface
and the flat-band voltage. charge, which is induced by plasma damage during via-hole

  
(rvia +tox +wdep )2 (rvia +tox )2 qNd +2(rvia +tox )Qi = [V ms (rvia +tox )] 2ox / ln 1+ tox
    rvia
(6)
(rvia +tox ) = qNd (rvia +tox +wdep )2 ln 1+ wdep 1 w2 wdep (rvia +tox )
2 Si rvia+tox 2 dep