MR-12239; No of Pages 5

Microelectronics Reliability xxx (2016) xxxxxx

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier.com/locate/microrel

Rail to rail radiation hardened operational amplier in standard CMOS technology with
standard layout techniques
Peterson R. Agostinho a,b,, Odair L. Gonalez a, Gilson Wirth c
a
Instituto de Pesquisas Avanadas, So Jos dos Campos, Brazil
b
Instituto Tecnolgico de Aeronutica, So Jos dos Campos, Brazil
c
Universidade Federal do Rio Grande do Sul, Electrical Engineering Department, Porto Alegre, Brazil

a r t i c l e i n f o a b s t r a c t

Article history: This work presents a rail-to-rail operational amplier hardened by design against ionizing radiation at circuit
Received 7 June 2016 level, using only standard layout techniques. Not changing transistor layout, for instance by using enclosed layout
Received in revised form 1 November 2016 structures, allows design and simulation using the standard models provided by the foundry. The circuit was fab-
Accepted 2 November 2016
ricated on a standard 0.35 m CMOS process, and submitted to a total ionizing dose (TID) test campaign using a
Available online xxxx 60
Co radiation source, at a dose rate of 0.5 rad(Si)/s, reaching a nal accumulated dose of 500 krad(Si). The circuit
Keywords:
proved to be radiation tolerant for the tested accumulated dose. The design practices used to mitigate TID effects
CMOS operational amplier are presented and discussed in detail.
RHBD 2016 Elsevier Ltd. All rights reserved.
TID
Hardened by design

1. Introduction use of p + guard rings to avoid the inter-device leakage current of

Operational ampliers are fundamental building blocks in analog/
mixed signal (AMS) systems and are widely used in signal processing
circuits, control circuits, and instrumentation [1]. In radiation environ-
ments, like space, the abundance of ionizing particles such as protons
and electrons is sufcient to deposit energy in semiconductor material.
The effect of irradiation primarily involves charge deposition in the
oxides and at the SiO2 interface: 1) gate-oxide trapped charge, which
can have a signicant impact on the dc parameters of the devices,
with a negative shift in the dc drain current versus gate-to-source
voltage for both NMOS and PMOS transistors; 2) Interface SiO2 traps,
by the increasing of the subthreshold swing of the device; and 3) thicker
isolation oxides (STI) trapped charge, which creates leakage paths,
increasing the stand-by current [2]. The accumulation of such charges
is referred to as the total ionizing dose (TID) effect.
Designers must take into account the TID effects, which can perma-
nently degrade the performance of the circuit, potentially leading to a
catastrophic failure of a system.
There are various radiation-hardened by design (RHBD) techniques
used in analog systems, at circuit or/and layout level. A widely used
RHBD layout technique that solves the issue of radiation-induced
source-drain leakage in NMOS transistors is the edgeless transistor lay-
out (annular or enclosed) [36]. Another technique at layout level is the
Corresponding author.
E-mail address: peterson@miptech.com.br (P.R. Agostinho).
NMOS-NMOS and NMOS-PMOS devices [5,7].
Techniques of RHBD at circuit level, without changing the layout, are
an important alternative to mitigate the TID effect in analog circuits
with the advantage that the models are more accurate and readily avail-
able, since foundries provide models based on standard rectangular
transistors. Among these techniques, the use of transistors within a
feedback loop is a powerful way to compensate parameter shifts [8]. An-
other simple technique is by increasing the W and L of the transistors
since the radiation effect is much more severe in transistors with
narrow/short channels [9]. The use of PMOS devices in circuits that
typically are built with NMOS transistors are also an efcient way to
mitigate the TID effect for sub-micron technologies (tox b 10 nm), since
PMOS transistors normally exhibit an increase in threshold voltage
under irradiation, and therefore a decrease of the leakage current [2].
In [10] the most TID robust stages of an op-amp were identied as
the stages that had symmetry and current-matching in an analog
design, suggesting that asymmetric topologies are more sensible for
radiation effects and reduce the circuit hardness.
This work presents a rail-to-rail operational amplier (op-amp)
hardened by design at circuit level, without using enclosed layout
transistors. The paper is organized as follow. Section 2 presents the
three stage op-amp used here and the design considerations to mitigate
TID effects. Section 3 shows the simulations and sensitivity analysis, im-
portant to indentify the critical devices of the circuit. Section 4 presents
the experimental setup and results and Section 5 the analysis and
conclusions.

http://dx.doi.org/10.1016/j.microrel.2016.11.001
0026-2714/ 2016 Elsevier Ltd. All rights reserved.

Please cite this article as: P.R. Agostinho, et al., Rail to rail radiation hardened operational amplier in standard CMOS technology with standard
layout techniques, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.11.001
2 P.R. Agostinho et al. / Microelectronics Reliability xxx (2016) xxxxxx

2. Operational amplier and design concerns Table 2

Op-amp MOS dimensions.

A three-stage rail-to-rail operation amplier based on the topology Transistor W/L Transistor W/L
presented in [11,12] was designed. The circuit was developed in the M1, M2 12u/2u M19 72u/2u
context of Brazilian space program demands [17] and has the specica- M3, M4 36u/2u M20 110u/2u
tions shown in Table 1. M5, M6, M21, M27 6u/2u M22, M24 18u/2u
M7, M8 2u/2u M25 316u/2u
M9, M26 24u/2u M28 106u/2u
Table 1 M10, M23 8u/2u M29 316u/2u
Op-amp specications. M11-M14 68u/2u M30 950u/2u
M15-M18 204u/2u
Performance Value

Power Supply 0.9 V 10%

Maximum Output Current 1.8 mA @ RL = 500
stage, it was used a feedback loop to better control the quiescent cur-
DC Gain N 80 dB
Phase Margin N 45 rent, ensuring stable quiescent current even with the shift on the pa-
GBW N 4 MHz rameters of the transistors due to radiation effects.
Power Consumption b 500 W
Slew-rate N 4 V/s 3. TID sensitivity analysis
THD [%] @ Vin = 500mVpp, 1KHz b 0.5%

In [13] TID results of 14 NMOS and 14 PMOS devices fabricated in

The schematic of the circuit is shown in Fig. 1. The input stage con-
sists of a NMOS input pair M1, M2 in parallel with a PMOS input pair
M3, M4. A gm - control circuit M5-M8 was added to the reference circuit
to keep the output currents of the rail-to-rail input stage constant, en-
suring a gm almost constant along all the input common mode range.
The second stage is a summing circuit formed by two current mirrors
M11, M12 and M15, M16 with cascodes M13, M14 and M17, M18,
respectively.
A compact Class-AB output stage was used in the design. It consists
of two common source output transistors M29 and M30. To make the
quiescent current insensitive to supply voltage a oating current source
was used and its value is xed by two translinear loops M11, M19, M27,
M28 and M15,M20, M24, M25. Since the oating current source M19,
M20 has the same structure as the class-AB driver M21, M22, the quies-
cent current is controlled and is insensitive to supply voltage.
For simplicity, the integrated bias circuit is not presented here. Only
one component, a resistor, was used externally to set the reference cur-
rent. A simple circuit based on current mirrors and transistors in diode
conguration was used to create internal bias voltages. The circuit sizing
is shown in Table 2.
As described, all the stages of the op-amp are symmetric and have
current-matching, improving the radiation tolerance [10]. A sizing
criteria were adopted for all transistors, with W and L at least ve
times greater than minimum geometry devices, contributing to mitigate
the radiation effects [9]. And at the output stage, which is the critical
AMS CMOS 0.35 m process are presented. The drain-to-source voltage
was kept at 3.3 V during the radiation, for all devices. 8 PMOS and 6
NMOS had gate-to-source voltage set to 3.3 V, with maximum electrical
eld through the gate dielectric. On the other hand, 6 PMOS and 8
NMOS transistors had the gate connected to ground, with null electric
eld through the gate dielectric. The devices were irradiated up to 500
krad(Si) TID with a 60Co gamma-radiation beam. Figs. 2 and 3 show
the average threshold voltage VTH shifted along the radiation for
NMOS and PMOS devices, respectively. In our circuit analysis the
curve with VGS biased is considered, since it is closer to real situation.
At maximum TID, NMOS and PMOS devices had an average threshold
voltage VTH shifted for +20 mV and 35 mV, which represents a VTH
shift on the nominal VTH of + 3.5% and 4.2%, respectively.
Other parameters like leakage current, mobility and sub-threshold
slope were also affected but with lower impact, so for simplicity, the
sensitivity analysis here presented will consider only the effect of VTH
shift.
During simulations it was found that the performances of the circuit
were much more sensitive for mismatch of VTH then a uniform variation
of VTH. For instance, 1% VTH mismatch in some critical transistors had
greater impact on performances than a 10% VTH variation uniformly
on all transistors. Since radiation has impact on mismatch of transistors
[16], it is important to identify the most sensitive transistors for mis-
match at each performance. Thus the VTH of NMOS and PMOS were
shifted individually for + 5% and 5%, respectively, while all other

Fig. 1. Operational amplier circuit.

Please cite this article as: P.R. Agostinho, et al., Rail to rail radiation hardened operational amplier in standard CMOS technology with standard
layout techniques, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.11.001
 P.R. Agostinho et al. / Microelectronics Reliability xxx (2016) xxxxxx 3

Table 4
Critical mismatch devices for frequency response.

Stage Transistor GBW/GBW_nominal

Input stage M9 @ VTH-5% 22,5%

M10 @ VTH + 5% 18,8%
M11 @ VTH + 5% 21,5%
M15 @ VTH-5% 29,2%

Table 5
Critical mismatch devices for power consumption.

Stage Transistor IBIAS/IBIAS_nominal

Input stage M9 @ VTH-5% 7,3%

M10 @ VTH + 5% 5,8%
Summing stage M16 @ VTH + 5% 497,4%

Fig. 2. VTH shift of NMOS devices for TID up to 500 krad(Si).
Fig. 3. VTH shift of PMOS devices for TID up to 500 krad(Si).
transistors were kept with standard values of VTH. This analysis is im-
portant to identify the critical devices, which the designer must take
special attention during design and layout steps. The change of param-
eters was done on the model card in the CAD tool through the parame-
ter VTH0 of Bsim3v3 le.
Table 3 shows the simulation results of sensitivity analysis for total
harmonic distortion (THD). As can be seen the most sensitive devices
are M1, M2 from the N input pair and M11, M12 from N current mirror.
Similar analyses were done for the frequency response, power con-
sumption and slew-rate. Table 4 shows the critical devices for the fre-
quency response, considering only one transistor with VTH parameter
changed at a time. The gain-bandwidth product was normalized over
the nominal value without radiation. Only for four transistors a shift
N10% was observed, as shown in Table 4. M9 and M10 are current mir-
rors to bias the PMOS and NMOS input pair, respectively. The VTH shift
for both devices decreases the bias current of the input pair with direct
impact on the gm of input stage and, consequently, on the gain-band-
width product of the op-amp. Similar analysis can be made for M11
and M15, with impact on the oating current source of the summing
stage and direct reection on the bias of the output stage. The reduction
of bias current on output stage reduces its gm and consequently the
gain-bandwidth product of the amplier.
Table 5 shows that M9, M10 and M16 are the critical mismatch de-
vices for power consumption, with increase N 5% with respect to nomi-
nal values, without radiation. A curious result was observed when the
VTH of M16 was shifted by 5% and the power consumption of the
op-amp increased about 5 times. The simulations showed that all the
excess current of the op-amp was in the output transistor M29 and
M30. It can be explained as follow: the quiescent current of M29 is
established by a translinear loop, with VGS29 = VGS27 + VGS28 VGS21.
At the present design the increase of VTH16 resulted in a decrease of
IDS16, which brought M21 to the cut off region. The reduction of hun-
dreds of mV on VGS21 was transferred direct to M29, resulting in the in-
crease of power consumption, as presented in Table 5.
For Slew-rate (SR) performance, six transistors were critical on the
mismatch analysis, with impact N10% with respect to the standard SR
Table 6
Critical mismatch devices for SR performance.

The changes of VTH on the others 26 transistors of the circuit had impact Stage Transistor SR/SR_nominal
lower than 1% on the THD.
Input stage M9 @ VTH-5% 19.1%
On a second analysis, it was considered the VTH shifts by the amount M10 @ VTH + 5% 17.5%
of +5% on M1, M2 at the same time, without mismatch. The same anal- Summing stage M11 @ VTH + 5% 24.9%
ysis was repeated for the current mirror M11, M12. This analysis was M12 @ VTH + 5% 38.9%
extrapolated for a VTH shift of 10%, and for both cases the impact on M15 @ VTH-5% 18.4%
M16 @ VTH-5% 33.9%
the THD was lower than 0.2%.

Table 3 Table 7
Critical mismatch devices for THD performance. Simulation results with uniform shift in VTH for all devices of the op-amp.

Stage Transistor THD [%] Devices THD GBW/GBW_nom IBIAS/IBIAS_nom SR/SR_nom

Input stage M1 @ VTH + 5% 2.4 All PMOS @ 0.1% 2.7% 0.2% 1.6%
M2 @ VTH + 5% 2.39 VTH - 5%
Summing stage M11 @ VTH + 5% 5.86 All NMOS @
M12 @ VTH + 5% 16.08 VTH + 5%

Please cite this article as: P.R. Agostinho, et al., Rail to rail radiation hardened operational amplier in standard CMOS technology with standard
layout techniques, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.11.001
4 P.R. Agostinho et al. / Microelectronics Reliability xxx (2016) xxxxxx
Fig. 4. THD results for TID up to 500 krad(Si).
without radiation effects. All transistors are part of current mirrors from
input and summing stage, as shown in Table 6.
To conclude the sensitivity analysis, all the NMOS and PMOS transis-
tor had the VTH shifted by the amount of +5% and 5%, respectively,
without mismatch, reproducing a hypothetic scenario where the radia-
tion affects all the devices equally.
The results are summarized in Table 7. The THD and power con-
sumption were kept almost the same and can be considered insensible
for such variation of VTH. Gain-bandwidth product and Slew-rate had
only incremental reduction of 2.7% and 1.6%, respectively.
These results indicate that the topology is robust to radiation effects,
if TID effect affects the all transistors in a similar way (not causing signif-
icant mismatches).
With the sensitivity analysis here presented it is clear that the degra-
dation of the performance is greater when the threshold shift results on
mismatch of devices, and the circuit can be considered robust to radia-
tion effects up to TID = 500 krad(Si) if the shift on VTH were the same
at all transistors.
In [16] the radiation effects upon the mismatch of identically laid out
transistor pairs is presented, and the results indicate that the mismatch
becomes smaller with increasing overdrive voltage gradually moving
the transistors operating region from weak to strong inversion mode.
In the present design the critical transistors were split in four devices
each, and the common centroid layout technique was used. It is an im-
portant layout technique, since VTH mismatch is the most relevant issue,
with greater impact on the performances.
4. Measurement results
Ground-based total-dose experiments were performed on the Ioniz-
ing Radiation Laboratory at the Institute for Advanced Studies (IEAv)
using a 1 kCi source of gamma radiation 60Co, model Eldorado 78 from
Fig. 5. Op-amp current consumption for TID up to 500 krad(Si).
Please cite this article as: P.R. Agostinho, et al., Rail to rail radiation hardened operational amplier in standard CMOS technology with standard
layout techniques, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.11.001
Fig. 6. SR values for TID up to 500 krad(Si).
Atomic Energy of Canadian Limited. The test was performed with a
dose rate of 0.5 rad(Si)/s during 12 days until the accumulated dose of
500 krad(Si), with the op-amp congured as follower. The chip
remained biased, with VDD = VSS = 0.9 V, during all the experiment.
The inputs were kept grounded, except during the data acquisition
cycle, which represents around 10% of the time. We expect a degrada-
tion of the op-amp transistors lower than the degradation of the devices
reported in [13], since the op-amp does not operate at maximum elec-
tric eld (due to maximum VDS and/or VGS). But, to be conservative on
the simulations, we consider in this work the worst case of VTH shift.
The data acquisition was done online along all the experiment, with
data storage at each 20 min. A voltage generator Agilent 32250A, an os-
cilloscope Agilent DSO6054A and a multimeter Keithley 235 were used
and controlled by a program developed in the platform Agilent VEE. At
each data acquisition cycle, the following performance metrics were
saved: current consumption, total harmonic distortion (THD), frequen-
cy response (GBW), and step response (Slew-rate).
Fig. 4 shows the THD performance of the op-amp for accumulated
dose up to 500 krad(Si). The circuit was biased with VDD = VSS =
0.9 V and a sine input signal with amplitude of 0.85 V and frequency
of 1 kHz was applied. The THD value of the op-amp in inverter congu-
ration started with 0.46% and decreased down to 0.38% for TID about 30
krad(Si). After that the THD increased and at the end of the experiment
the THD reach values similar to the initial value.
The current consumption of the op-amp was 120 A at the beginning
of the experiment and remained almost constant along all the TID accu-
mulation, with a variation lower than 2%, as shown in Fig. 5.
Figs. 6 and 7 show the Slew-rate (SR) and GBW results, respectively.
For the SR measurement it was used at input a square signal of 1 kHz
and amplitude of 0.9 V and the response remained almost constant
up to 200 krad(Si) and increased around 1.3% for the maximum cumu-
lated dose. On the other hand, the GBW decreased, with a behavior close
to linear, reaching a 2% shift at maximum TID. To get the GBW value, the
Fig. 7. GBW values for TID up to 500 krad(Si).
 P.R. Agostinho et al. / Microelectronics Reliability xxx (2016) xxxxxx
frequency of the sine signal at the input of the op-amp in buffer cong-
uration was swept until output signal reach 3 dB attenuation.
Most of the works of TID analysis in op-amp found in literature are
based on commercial off-the-shelf (COTs) op-amps or circuits with
BJT transistors.
There are few works in the literature that analyze TID effects on
CMOS op-amp in sub-micron technologies. In [14] an amplier built in
a standard 0.35 m CMOS process is presented and characterized at dif-
ferent TID levels. There are few details about the topology, the author
state that it's a transconductance amplier, which had signicant degra-
dation of dynamic output range and harmonic distortion, and the circuit
operated properly up to a total dose of 180 krad(Si). Possibly circuit
level techniques to improve radiation tolerance, such as complementary
input pair or internal feedback loop, were not used. Sometimes the de-
signer chooses to use transistors with short/narrow channel to improve
frequency performance and reduce area, but this reduces signicantly
the radiation tolerance of the circuit. In [15], on the other hand, it is pre-
sented TID results of RHD5902, a commercial RHBD operational ampli-
er designed in CMOS 0.5 m process, part of Aeroex's family of
radiation hardened analog circuits. According the author, a robust topol-
ogy and techniques at layout level were employed, like edgeless NMOS
and guard rings. There are not many details about the topology, but it's a
rail-to-rail input and output range circuit, similar to the amplier pre-
sented in this work. The main difference is that this commercial op-
amp uses techniques of radiation tolerance at circuit and layout level,
and the present work uses techniques only at circuit level. The
RHD5902 was tested with 60Co gamma-radiation beam up to 2 Mrad(Si)
and the slew-rate, power consumption and gain bandwidth product
had the initial values of 4.5 V/s, 4.5 mA and 32 MHz reduced to the
values of 3.3 V/s, 3.3 mA and 24 MHz, respectively.
5. Conclusion
A rail-to-rail CMOS operational amplier robust to an accumulated
TID of 500 krad(Si) was presented. TID tolerance was obtained by hard-
ening by design, avoiding the use of any non standard layout tech-
niques, such as enclosed layout. This makes the employed design ow
to be fully compatible with standard CAD tools, and simulation models
provided by the foundry. The design phase included critical evaluation
of key aspects to achieve radiation hardening, backed by previous irra-
diation results for transistors fabricated on the same technology used
in this work, as well as design practices and results for radiation perfor-
mance reported in the literature. During the radiation campaign of the
fabricated op-amp different performance metrics (such as power
Please cite this article as: P.R. Agostinho, et al., Rail to rail radiation hardened operational amplier in standard CMOS technology with standard
layout techniques, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.11.001
5
consumption, Total Harmonic Distortion, Gain Bandwidth Product and
Slew Rate) were monitored.
References
[1] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 3 ed. Oxford University Press,
August 2011.
[2] H.J. Barnaby, Total-ionizing-dose effects in modern CMOS technologies, 2006. IEEE
Trans. Nucl. Sci. Vol. 53, http://dx.doi.org/10.1109/TNS.2006.885952.
[3] G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Floria, A. Giraldo, E. Heijne, P.
Jarron, K. Kloukinas, A. Marchioro, P. Moreira, W. Snoeys, Radiation tolerant VLSI cir-
cuits in standard deep submicron CMOS technologies for the LHC experiments:
practical design aspects, 1999. IEEE Trans. Nucl. Sci. vol. 46 (6), http://dx.doi.org/
10.1109/23.819140.
[4] R.C. Lacoe, J.V. Osborn, R. Koga, S. Brown, D.C. Mayer, Application of hardness-by-de-
sign methodology to radiation-tolerant ASIC technologies, 2000. IEEE Trans. Nucl.
Sci. vol. 47 (6), http://dx.doi.org/10.1109/23.903774.
[5] R.N. Nowlin, J. Bailey, R. Turer, D.R. Alexander, A total-dose hardening-by-design
approach for high-speed mixed-signal CMOS integrated circuits, 2004. Int. J. High
Speed Electron. vol. 14 (2), http://dx.doi.org/10.1142/S0129156404002417.
[6] R.N. Nowlin, S.R. McEndree, A.L. Wilson, D.R. Alexander, A new total-dose-induced
parasitic effect in enclosed-geometry transistors, 2005. IEEE Trans. Nucl. Sci. vol.
52 (6), http://dx.doi.org/10.1109/TNS.2005.860713.
[7] R. Lacoe, CMOS Scaling: Design Principles and Hardening-by-Design Methodology,
NSREC Short Course, 2003.
[8] J.Y. Ahn, W.T. Holman, R.D. Schrimpf, K.F. Galloway, D.A. Bryant, P. Calvel, M.-C.
Calvet, Design Issues for a Radiation-Tolerant Digital-to-Analog Converter in a
Commercial 2.0-m BiCMOS Process, Presented at the Radiation and Its Effects on
Components and Systems Conference, 1997. 1997, http://dx.doi.org/10.1109/
RADECS.1997.698866.
[9] F. Faccio, Radiation-induced edge effects in deep submicron CMOS transistors, 2005.
IEEE Trans. Nucl. Sci. vol. 52 (6), http://dx.doi.org/10.1109/TNS.2005.860698.
[10] A.H. Johnston, B.G. Rax, Failure modes and hardness assurance for linear integrated
circuits in space applications, 2010. IEEE Trans. Nucl. Sci. vol. 57 (4), http://dx.doi.
org/10.1109/TNS.2010.2049583.
[11] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, J.H. Huijsing, A compact power-efcient
3 V CMOS rail-to-rail input/output operational amplier for VLSI cell libraries,
1994. IEEE J. Solid State Circuits vol. 29 15051512, http://dx.doi.org/10.1109/4.
340424.
[12] K.-J. de Langen, J.H. Huijsing, Compact low-voltage power-efcient operational am-
plier cells for VLSI, 1998. IEEE J. Sol. State Circ. vol. 33 (10), http://dx.doi.org/10.
1109/4.720394.
[13] T.H. Both, Anlise dos Efeitos de Dose Total Ionizante em Transistores CMOS
Tecnologia 0,35 m, Universidade Federal do Rio Grande do Sul, Dissertao de
Mestrado, 2013.
[14] L. Zhi, L. You-bao, N. Hong-ying, Design of a Radiation Hardened DC-DC Boost Con-
verter. International Conference on information Engineering and Computer Science
(ICIECS), 2010. 2010, http://dx.doi.org/10.1109/ICIECS.2010.5678208.
[15] R. Benson, P. Resch, R. Milanowski, Characterization and Analyses of RadHard-by-
Design CMOS Quad Operational Ampliers, IEEE Radiation Effects Data Workshop
(REDW), 2013. 2013, http://dx.doi.org/10.1109/REDW.2013.6658185.
[16] J. Verbeeck, P. Leroux, M. Steyart, Radiation effects upon the mismatch of identical-
ly laid out transistor pairs, 2011. IEEE Conf. Microelectron. Test Struct., Amsterdam,
The Netherlands, 2011, http://dx.doi.org/10.1109/ICMTS.2011.5976845.
[17] [Online]. Available: http://www.aeb.gov.br/wp-content/uploads/2013/01/PNAE-In-
gles.pdf