DESIGN AND IMPLEMENTATION OF DIGITAL COSTAS LOOP FOR

RADIO RECEIVERS
MR.VARUN DAS P.P
Mtech in Digital Electronics, Department of E.C.E,
Don Bosco Institute of Technology, Bangalore, Karnataka, India.
varundaspp@gmail.com

MR.SHASHI RANJAN
Assistant Professor, Department of E.C.E,
Don Bosco Institute of Technology, Bangalore Karnataka, India.
shashiranjanbe@gmail.com

MR. SACHIN
Mtech in Digital Electronics, Department of E.C.E,
Don Bosco Institute of Technology, Bangalore, Karnataka, India.
sac1357patil@gmail.com

ABSTRACT: Communication is a part of our day to day life. While transferring the data, the
receiver should receive the data in proper form. Due to noise and Doppler Effect in the wireless
medium, there are chances of phase error at the receivers end. This paper describes the design and
implementation of the low power demodulation unit that undergoes carrier recovery and detection
using Costas loop. There happens to be an imbalance between the in-phase and quadrature-phase
in analog design. A fine tuning is required in order to compensate the effect. To overcome this
problem of analog design, digital design is used.In terms of size, complexity and for fine tuning, it
is beneficial to implement using a FPGA. In this paper, the whole system is implemented in a
single FPGA. It is simulated digital domain using digital multiplier and NCO (numerically
controlled oscillator) replacing VCO (Voltage Controlled Oscillator). The NCO is implemented
using Lookup Table (LUT) and then using CORDIC Algorithm.

INTRODUCTION

Wireless communication is the transfer of information between two or more points that are not
connected by any electrical conductor but are separated by mere medium like air or vacuum.
Wireless operations are used in services where in it is impossible or impractical to implement with
the use of wires, such as in long-range communication. The most common wireless technologies
use radio. With radio waves distances travelled can be short, such as a few meters for television or
as far as thousands or even millions of kilometres for deep-space radio communications. At the
receiver end, demodulation must be accomplished to recognize and retrieve the message signals.
Nowadays, a lot of research is being carried out to reduce the power of circuits involving
complexities in both mathematics and also communication. A Costas loop is a phase-locked loop
based circuit which is used for carrier phase recovery from suppressed-carrier modulation signals,
such as from double-sideband suppressed carrier signals. A Costas loop is used most commonly
for carrier synchronization in a receiver when the modulation is BPSK. The primary application of
Costas loops is in wireless receivers. This translates to double the sensitivity and also makes the
Costas loop uniquely suited for tracking Doppler-shifted carriers especially in OFDM and GPS
receivers.

The basic block diagram of Costas loop is shown in Fig. 1. It is also termed as the in-phase and
quadrature loop. The basic components of the Costas loop are three multipliers called mixers, two
low-pass filters (LPF), a loop filter (LF), a VCO and a 90 degree phase shift. As in Fig. 1, the
incomingsignals are sent to both the multipliers of the upper called in-phase branch and the lower
called quadrature branch respectively. The in-phase branch multiply input data by VCOs output,
and the quadrature branch multiply input data by VCOs output after 90 degree phase shift. The
multiplier output of the in-phase branch is passed through the low-pass filter; similarly the
multiplier output of quadrature branch is passed through another low-pass filter. Then the output
of both the low-pass filters are then multiplied together to get the error signal. Finally, the error
signal is filtered by the LF, whose output is control voltage that can control VCOs phase and
frequency.

Demodulated signal
V3 Low pass
filter
V5

V1 VCO Loop filter

s(t)
V7

90 degree
phase shift

V2 V4 Low-pass V6
filter

Figure 1. Block diagram of Costas loop

In Fig.1, it is assumed that the loop is locked and noise signal is not considered. To be specific,
suppose we have an amplitude signal of the form
s(t)=A(t)cos(2 ) (1)
If we demodulate the signal by multiplying s(t) with the carrier reference
V1= cos(2 ) (2)
We obtain
V3=s(t)V1 (3)
= A(t)cos(-)+ A(t)cos(4 ) (4)
The double-frequency component may be removed by passing the product signal V3 through a
low-pass filter. This filtering yields the in-phase component
V5= A(t)cos(-) (5)
Where =- is the phase error.
Similarly, If we demodulate the signal by multiplying s(t) with the quadrature carrier reference
V2=sin(2 ) (6)

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We obtain
V4=s(t)V2 (7)
= A(t)sin(-)+ A(t)sin(4 ) (8)
multiplication of s(t) with V2 followed by low-pass filtering yields the quadrature component
V6= A(t)sin(-) (9)
Multiply V5 by V6, then we can get
V7=V5*V6= sin(-)cos(-) (10)
= sin2(-) (-)= (11)

This voltage controls VCO to the same frequency with and a small phase error after passing
through a loop filter. At this time, V1 is the synchronous carrier that we want to extract and V5 is
the demodulation output signal.From the processing of mathematical analysis, we can see that
Costas loop works in the frequency which is lower than the square loops working frequency and
dont need the squarer and frequency divider. While the loop locks normally, the output of in
phase branch is the original digital sequence which we need to demodulate. Therefore, this circuit
has dual function of extract coherent and demodulation carrier.

LITERATURE SURVEY

In the paper by Huimei Yuan, Xiaoguang Hu, Juyong Huang, Design and Implementation of
Costas Loop Based on FPGA, 2008, the author implemented the design of Costas loop on FPGA
because of its high flexible in system programmability. It also specifies the limitations in terms of
bit length, digitizing loop parameters and clock design of the components within the loop. The
VCO is implemented in the form of DCO. DCO has the same working principle as that of the
VCO and the output of the DCO is a local carrier which is controlled by the regulated output from
the loop filter. The functional modelling of the entire loop was done in HDL.

In the paper by LaiGongGuo, MingSanOuYang, Jun Cai, Simulation and Implementation of

Costas Loop Based on FPGA, 2011, the author describes the limitations of the squaring loop
method which could be used to extract carrier signal after nonlinear transformations and how
Costas loop method is more beneficial than it. In this paper the author uses DDS (Direct Digital
Synthesiser) principle instead of VCO. DDS is a digital frequency synthesis with high frequency
resolution, frequency conversion and phase-speed continuous, high precision output etc.

In the paper by Shamla B, Gayathri Devi K.G, Design and implementation of Costas loop for
BPSK demodulator, 2012,the author describes the defects in traditional analog Costas loop such
as imbalance between in-phase branch and quadrature-phase branch, direct current zero excursion
and difficulty to debug. In this paper the digital design of the system is based on direct
transformation of every analog components of Costas loop to its respective discrete time and
subsequent digital domain. Here VCO is replaced by NCO which is implemented by sine LUT
which is offset by the loop filter output which is proportional to the phase error.

In the paper by Roshna T R, NivinR,Sherly Joy , Dr.Apren T J, Alex V, Design and

implementation of digital Costas loop and Bit synchronizer in FPGA for BPSK demodulation,
2013, the Costas loop is implemented using Coordinate Rotation Digital Computer algorithm

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(CORDIC). It is used when hardware multipliers are not available. It works on simple addition and
subtractions. But the implementation is slow as in the multipliers has a large coefficients. The
filtering process used also has larger coefficients that lead to higher power consumption.

In the paper by Salman Sadruddin, Muhammad SaadSohail, FPGA based Telecommand Receiver
Module for Microsatellites, 2014, the author details about the usage of Costas loop to attain
carrier recovery of the BPSK signals. The demodulated signal is applied at the input of an
integrate and dump module as well as it calculates the threshold value which is used by data
sampler module. Theintegrate and dump module output and threshold value are applied to the bit
synchronizer and data sampler module. This module passes the signal through three stages; peak
detect, preamble match and data sampler. The peak detect module uses the early-late-gate
sampling algorithm.

METHODOLOGY

In this paper, the digital version of the typical analog Costas loop is implemented. Here in, the
VCO is replaced by the NCO. The NCO is implemented by using a LUT. The LUT can be
implemented only to a set of signals that falls in particular frequency range. The LUT method is
later on replaced by CORDIC Algorithm which required less power, memory and is adaptable
with the nature of the signals received.

Look up Table Method

In this method the NCO generates the pre-stored data on each clock cycle depending upon the
frequency. This paper is designed for frequency specifications with sampling frequency 9.6 MHz
and carrier frequency 120 kHz. The following flow chart shows the overall design flow of the
LUT for this paper. First the LUT was designed and simulated in Matlab 7.0 for the previously
mentioned frequency specifications to achieve the required sine and cosine values. From the sine
and cosine values so obtained, the Verilog code for the LUT is generated. The verilog coding was
simulated in Modelsim SE 6.3 for verification before being synthesized. All the results are then
being analysed.

LUT design and simulation in Matlab 7.0

Generate sine and cosine values

Generate Verilog code for LUT

Verilog code simulation in Modelsim SE 6.3

Result analysis

Figure 2. LUT Design Flow

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CORDIC Algorithm Method
In this method, the NCO is implemented by using CORDIC (Coordinate Rotation Digital
Computer) Algorithm. It is also known as digit by digit method and Volders Algorithm. It is a
simple and efficient algorithm to calculate hyperbolic and trigonometric functions. It uses simple
shift add operations for several computing tasks.CORDIC is generally faster than other
approaches when hardware multiplier is not available.

The flow chart for the overall design flow of the CORDIC Algorithm for this paper is similar to
that of LUT design. First the CORDIC Algorithm was designed and simulated in Matlab 7.0 for
the previously mentioned frequency specifications to achieve the required sine and cosine values.
From the sine and cosine values so obtained, the Verilog code for the CORDIC Algorithm is
generated. The Verilog coding was simulated in Modelsim SE 6.3 for verification before being
synthesized. All the results are then being analyzed. The design of NCO is done by subdividing it
into two blocks, one block for theta generation and other for CORDIC Algorithm. Both of these
blocks are synchronized to each other with the help of an external clock.

EXPERIMENTAL RESULTS

Simulation result in Modelsim SE 6.3

The NCO implemented using LUT approach has been coded in verilog and is simulated in
Modelsim SE 6.3 and the result is shown in figure below. The clock period used in this verilog
coding is 100ns. The output of the filter designed in this paper is shown below.

Figure 3. Simulation result of LUT method

Simulation result in Matlab 7.0

The LUT implemented here is of sampling frequency 9.6 MHz and carrier frequency 120 kHz. The
Matlab design provides the desired table values for the LUT method. From the desired sampling
frequency, the required table values are obtained. The CORDIC Algorithm implemented here is of
the same frequency mentioned, i.e. sampling frequency of 9.6 MHz and carrier frequency of 120
kHz.

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 Figure 4. Simulation result of Theta generator for CORDIC Algorithm

CONCLUSIONS

A design and implementation of the NCO unit with LUT approach in the system was successfully
achieved. Results produced in Matlab 7.0 and modelsim SE 6.3 shows that design meet the
specification requirement. Similarly the NCO with CORDIC Algorithm approach was designed
and implemented which meet the required specification.

REFERENCES

Rupanagudi, Sudhir Rao, et al.(2008), Reducing computational complexity of branch metric

calculations in a trellis decoder
Huddar, S.R.; Rupanagudi, S.R.; Kalpana, M.; Mohan, S.,( 2013), Novel high speed vedic
mathematics multiplier using compressors
Sushma R. Huddar, Sudhir Rao Rupanagudi, Venkatesh Janardhan, Surabhi Mohan, and S.
Sandya,(2013) ,Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic
Mathematics on FPGA
Huimei Yuan, Xiaoguang Hu, Juyong Huang( 2008), Design and Implementation of Costas Loop
Based on FPGA
LaiGong Guo, MingSan OuYang, Jun Cai (2011) Simulation and Implementation of Costas Loop
Based on FPGA
Shamla B, Gayathri Devi K.G, (2012), Design and implementation of Costas loop for BPSK
demodulator
Roshna T R, Nivin R,Sherly Joy , Dr. Apren T J, Alex V (2013.)Design and implementation of
digital Costas loop and Bit synchronizer in FPGA for BPSK demodulation
Salman Sadruddin, Muhammad Saad Sohail,( 2014), FPGA based Telecommand Receiver Module
for Microsatellites

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