41 -/EEE Date : 01/08/2015, BANGLADESH UNIVERSIIY OF ENGINEERING AND TECHNOLOGY, DRAKA LATA B.Sc, Engincuring Esemimations 2013-2014 sub EEE 453 (vist-1) Full Marks: 210 Tuas: 3 Hows USE SEPARA IE SCRIPTS FOR HAGH SECTION ‘The figures in dhe mangin Indicate fll marks, SEETION- A “Tyere ace FOUR questions in this secon. Answer any THREE. (68) Stow the procase sequence of fabricating an anverter ona NWELL CMOS process. Clenly show the mask used ané the devick cross-seational diagram after each step. (o) Two cesaston caeh having 4 une resistors are 10 be matched na Isyout, The sheet resistance varies Tiaesrly as 2 tunchen of pesition Between interdigitated layout end samamon centroid layout whieh one wall you prefer for matching? Justity your answer ‘with mumencal values (2) Show in w dhagiam the origin and model of CMOS latch up in a PAYELL process. How latch up cae be prevented? (hy Consider designing, « control sirouit that will swap the contents of two registers Ry and Rp, whe the control sigaal w yacs to HIGH. You can use another register Rs 1 temporarily hold the value of ene of the registers whese value Will be swapped. Draw lhe sate diagram. slave table and siate assigned table of the Moore type Finije State ‘Machiwe (PSM) snd the citcuie diagram of the controller (a) Using # structured design approsch, develop bas avbitiation logic for miine bus such thar access i= given to the highest provty line. If priority is given aesording securing order (line N baghest privrty) draw dhe exrcor’ and sticc diagram ef a basic leat cell. (6) Draw the gate fevel elreult for implementing the function $—A.B+ A.B using NOT, AND and OR gates. Suppose that you want to detect stuck at L faults a! all the primary inputs and the primary ouput. Derive Ute comerponding minimum: tet of test vectors, (In the Fog, How Q. (a), trunsistor 1 i stuck open (Oy). Find all the two pater teat vectors that wall decect the fault Contd ea ees PR 20) as) «1s 20) a9) as) (10)Vedat Fg. for @. yea) (b) Show the NOR-NOR implementetion ef 8 PLA circut which will provide We Sohowmng outputs in CMOS logic. . tcab ved Zab (6) Draw che schematic diagram of a seansable D flip-flop built trom inverters and CMOS transmission gates SECTION. ‘Thare ure FOUR questions in this section Answer sy THREE, {a} For the conngetion of the NMOS pass tranisior shown in Fig. for Q. 5a) find the output VoRERE Vouto Yoo Ad Voge Assume Ves = 1V, 77 0.5 Wi Conta PO as) oO as)EEE JSUEFE Wo. 5 fo) Wath necessary figures explain what happens to switching ports of uansstor shuuneter curve and woise margins NM, snd NM When Pi/By is increased in a CMOS inverter pair. Assume thet the loge levels are selecied at the unicy gain points of the DC ranaier characteristics curve (© maximize the noise margin fe) Ifthe data ys completely random tbr e 4 input OR gale built out of 2 input NOT and > input NAND gates, find the activity faeror. Alte find the dynamic power dissipated in. the gates, if the clock frequency is | GH2, the Supply vollage Is 1.2 V and the toad capacitance is 5 ph 6G) AS inpat CMOS NOR jae as diving h ntumber of similar gates. Draw the schematic diagram of the NOR gate at MOS wansistor level. Asmme that mobility of elestrons 1s Ghrive the mobility of holes. Show whe aspeet ratio of Ube transistors tw achieve equal rise and fall resistance (6 that ofa uait inverter sn the worst case. Show the switch level RG model of the NOR gate and calculate the rising propagation delay ou), falling propagation delay (ipa) and filling conlarsination delay (tat (8) Derive the expression for the short cireait dissipation of a CMOS inverter. 7 (A baller chain 19 he designed for 6 clock signal which will drive 1590 logic gates ‘he input eapacttance of each of the loic gates is 8 pF and the output cepneitanes is 3 pe. The minimum sized inverter un the process has an input capacitance of 4 pF and output capacitance of 2 pit amd output capacitance of 2 pR. Find the sfze (a) and the ‘number of stages (m) of Ue required butfer chain. You have to derive the equations used in your calealation first. (®)A 4 bic data path consists of seayster, ALU and a shifler Show two possible bus arelutectures of the system such shut an addition operation of two operands siored in the epister and storiag the vesble backs in the regaster can be compated in at most two clock cycles Cont case Pd 0) a9) @0) as) (20) a5)ERE 453/EEE 8 a) i) Show the cxouit dogram of 21 SRAM aay which uses 6 uansistrs memory cell as basic storage cell, Clearly show the row select. column select, pre-charge and sense sgral fn your eso 20) () Esplin iow READ acd WRITE opctacon ave pertorsed showing Ine Brst row and second columa cell os an examsle, iy splen how sense ampherredoets the READ time of he cel (0) Draws the selection and sortrol of a 44 register aray that can select any regia Yor READ or WRITE, com select non registers sumulianesaly and can READ the coments of a single rosiater to both A and B buses of 2 cwo bus architecture system. Briefly cexplsin the operation, as)meee ae Full Marks : 210 ‘Time :3 Hours we “There are FOUR qucstions inthis section. Answer any THREE, 1 you feel there is any ambiguity make reasonable assumptions and state iin your solution. 1. @ Show the provess sequence of fabricating the following circuit (NMOS inverter with a resistance load) in NEWLL CMOS process. You have the fieedom to design the resistance ether from polysilicon layer or frm the NveliffP+diff layer 20) fw [rts “TT! Fig, for 0. 4@ () You have to design a four line gray code to binary code converter in a structured way “The truth table is shown in Fig for Q.No. 100), asy () Show the schematic diagram of the design using a suitable leaf cel, Gi) Draw the layout diagram of the leaf cell in such way that the Vop, GND and the intermediate signals are automatically connected when the eaFeells are butted together. Contd paEEE 453 2. (@) Show transistor level NOR-NOR PLA implementation of a digital czcult which has ‘three output (2, Zz and 24) a8 follows eres: Ba (©) (0 Show the circuit diagram of a 2 x2 SRAM array which uses .tansstor memory cell as basic storage coll. Clearly show the row select, column selec, pre-charge and a! be+bs; Zp =b+abe sense signal in your cireuit. (Gi) Explain how the READ and WRITE operations are performed showing the frst row and second column cell as an example. (Gil) Explain how sense amplifier reduces the READ time ofthe cell 3. (@) Design a S:bit Cary Select Adder such that the delay Becomes minimum. Assume that the delay through one adder cell i= SOO pS and the propagation delay through the ‘multiplexer is 250 ps. Derive any equstion used in your calculation and show the schematic diagram of the adder citeuit, Compare the delay of this adder with that of @ ripple carry adder (©) () Show the schematic diagram of #4 % 4 bit array multiplier designed in a structured ‘way. Wdentfy the basic cell of the multiplier and explain the operation of the circuit. ‘Show the critical path ofthe signal which will experience the longest delay. Gi) Design a general purpose UO pad having ESD protection circuit. Explain the operation of your elreuit. 4. (@) (@) Show the cirouit diagram and device cross-sectional diagram of a one transistor ‘wench capacitor DRAM Cell. By showing the timing diagram explain the READ and WRITE operation of the cireut, Gi) To fully torn on the access MOSFET, word line of the above DRAM is driven to 20 $F and Vp+Vey. The memory bit capacitance Cy is stored in the capacitance bby charging it 10 full Vpp = IV. The bit line capacitance is 100 fF and before READ ‘operation the bit Line is pre-charged to Vpp/2. What voltage will be obtained in the bit line during the read operation? (8) In the CMOS circuit shown in Fig for Q. No, 406) a bridging fault occurs between line €1 and £2, Explain how you will detect the full snd which lest Vector will you apply? Contd Pea as) 20) «gy an 20) as)section “There are FOUR questions in this soction. Answer any THREE, If you fel there ix any ambiguity make reasonable assumptions and stat it in your solution. 5. (@) @) Show that the threshold voltage of a MOS transistor with body bias Vay can be approximated as V; = Vig + ¥/Vop where the symbols have ther usual meanings. Gi) When used as a pass transistor, explain why a PMOS transistor passes good ‘1 and ‘bad 1, Assume Vip = —1V, Von = SV, Vig) = SV, Vi (L) = OV. (8) ( An NMOS inverter with NMOS enhancement load is designed such that the output ‘voltage becomes 0.2V when the input voltage is high (SV). Calculate the aspect ratio of the inverter. The following data are given: Cox = 30 WAV?, Vig = IV, Voo. ‘y=0.S. Assume, the body of the transistors are connected with ground, (Gi) What would be the output voltage ifthe input voltage is 02V7 6. (8) Show that the dynamic power diss square of the power supply voltage whereas the delay ofthe circuit varies inversely with mn of « CMOS inverter varies directly with the power supply voltage (©) The output of 3 input NAND gate drives 15 similar NAND gates. Calculate the worst ease rise time and fl time of the NAND gate. The following data for the gate are {iven: jg Cop = 120 HAVA, Con = 40 HAV, Ving = HV, Ving =-1V. Vo = SV. = 05 Wy = TOKE, Wp = 20m, Cy = Ep = 1 um, sourcedrain length = Sum, gate oxide ‘capacitance = 20 £F/jm?, source drain diffusion capacitance = 10 #F/jm?. Assume the ‘body of NMOS transistor is connected with GND and the body of PMOS transistor is ‘connected with Voo- 7. (@) What is latct-up? A CMOS integrated circuit is designed on « PWELL process, Show the possible Isteh-up circuit and explain how latch-up could be induced. Explain the fabrication measures and the design measures that should be taken to prevent latch-up in €MOS circuits (&) Am inverter busfer chain is designed in a SV CMOS process so that each stage i four times larger than the previous stage. The first stage of the chain is designed with « ‘minimum size inverter gate, which has an input (Ca) snd output (Cou) capacitances of (0.1 pF and 0.2 pF, resposively. The chain drives 2000 minimum sized basic gates Calculate the delay trough the chain. Assume P~ p= 2 10% A/V? forthe minimum size inverter If = 100 Miz caleulate the dymamic power consumed by the buffer chain circuit Contd pa an as) as) 20) as) 20EEE 453 8 (2) 43:2 priority encoder is defined as follows Yo =Ao-(Ay +A2)s Y= KoA (Sketch the transistor level schematics ofthe logic functions Yo and ¥,, each of which is implemented in single CMOS complex logic gate. Assume that both true and ‘complementary versions of the inputs are available Gi) Ifthe above logic functions are to be implemented with worst case equal rise ané fall times, determine the relative width of the PMOS transistors with respect to the NMOS transistors for both of the logic gates. Assume jig =3 jp and gate length of NMOS and PMOS transistors are equal tothe minimum allowable in the process (Ly ~ Ly Lin. (©) Sketch the transistor level schematic for the logic functions of Q. 8(a) in (i) pseudo NMOS, (i) footed dynamic CMOS, and Gi) domino CMOS. 0) as)L-4T-VEEE Date : 23/07/2013 BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA L-A/T-1_B, Se, Engineering Examinations 2011-2012 sub: EEE 453 visi) Full Marks : 210 Time: 3 Hours “The figures in the margin indicate fell marks. ‘Symbols have their usual meanings. USE SEPARATE SCRIPTS FOR EACH SECTION SECHION=A “There are FOUR questions in this Section, Answer any THREE. 1G) Bxplain the statement, "NMOS past transistor passes good ‘0! but bad '1"". For the connection of the NMOS pass transistors shown below find the output voltage Vow and Vers The following data are given Vis “IV, = 0.5. (b) What is sheet resistance? A 100 am CMOS process uses a polysilicon layer as resistors. The resistivity of the polysilicon layer is 20 « 10-6 Cm and the thickness is 500 nm. Calculate the number of squares needed to form a 5 KE? resistor. (©) Show the cireuit diagram of « peeudo NMOS inverter, The Inverter is designed such ‘that output Voltage becomes 0.2 V when the input vollage is High (5 V). Calculate the the ratio of driver transistor size to load transistor size. The 50 HAN, Vin = IVs aspect ratio of the invertes following data are given: Con = 120 WAV", uyCox Vuop == 1-Vs Von = $V, 7 = 0.5. Assume the body of the NMOS transistor is connected “with the ground and the body of the PMOS transis js connected with Voo- 2. (@) In 180 am CMOS process the minimum gate length and width are 22 and 42, respectively. A minimum sized and sinimam gate length CMOS inverter is designed such that the inversion voltage becomes Vpe!2. The following data are given igCox = 120 WAV, iyCox ~ 60 HAIV?, Vin = 1V, Vip IVs Vin = Viv = 0S (Calculate the aspect ratio ofthe NMOS and the PMOS transistor. Gi) In the transfer curve show the minimum and maximum input and ousput voltage levels and hence give an expression of low level and high level noise margin. Gi) Now suppose that the designer increased the aspect ratio of the NMOS iransistor ten times than that obtained in (). What changes in noise margin do you expect? Conta Pa oy ao) asy «agygates. The input capacitance of each of the logic gate is 12 fF and the output capacitance {4 fF, The minimum sized inverter in the process has an input capacitance of 3 #F and ‘output capacitance is also 3 AF. Find the size (n) aod the number of stages (m) of the ‘required buffer chain. You have to derive any equations used in your calculations, (@) Derive the expressions for rise time and dynamic power dissipation of » CMOS (©) The output of a CMOS inverter is connected to the input of logic gate ae shown in Fig. for Q, No. 3(6) Calculate the rise time, fall time and dynamic power dissipation of | the CMOS inverter. The following data are given: Process Technology 500 nm CMOS process. Cx 120 WAV, 14Cr= 50 HAIV*, Gato oxide capacitance Cor 35 (Pham ‘Source/Drain bottom Junction capacitance of both NMOS and PMOS, C;~ 10 fF/um", ‘M, = 033,Source/drain side wall capacitance of both NMOS and PMOS, Cow = 02 fim, Maw = 0.1, yo = 0.7 V at room temperature, poly-substrate ‘spacitance ~ 15 f/m’, Metal-subsrate capacitance = 6 jm, All poly width = 22, poly extending N-Difusion/P-Disfusion = all metal width ~ 22 except Veo and GND bus 1, freauency, f~ 500 MHz. total Fig for. No. 210) Conta pa an (a0): yo tsa i eo Bepin yt sce of Be foing design ees: Pay ovr Dion ; 4 isle mohunichenbaunns peter one pmuaratsnet ep ae NWELL to P-Diffusion~6A. (6) Neos hey te ann fhe owing SPICE MOS model prsmto (KP 4 Gnonvta p Mag LAMEDA GPE on as (©) Draw the truth table of a 3-input majority circuit in which the output is ‘T when ss ‘majority of the input is‘. Minimize the Boolean expression of the output and implement : amormutin gy ena, Feud 0S, Gi og dmani COR. as” is (@) A 4-input NOR gate is designed for worst case equal rise and fall times. If 4a = 2-544. oy ‘calculate the aspect ratio of the PMOS transistor in terms of aspect ratio of the NMOS is tensor. © SE B ‘There ate FOUR questions ia this Section. Answer any THREE, 5. (@) Explain the following: () positive mesk, (i) negative mask, (ii) positive photoresist and (i) negative photoresist 416) Show the process sequence of fabricating an inverter in a dual well CMOS process. In each sequence show the mask diagram and the deviee cross sectional diagram up to that sequence. (by Design an n-bit party generation circuit in bit sliced and structured way. The required response is such that Z-~ 1 if there is even number of Is in the input and z = 0 if there is ‘odd number of 1. Show the schematic diagram of the parity generator including, the connection of the fist cell. Draw the layout diagram of the leaf cell using CMOS technology in a modular way stich that interconnections between cells are achieved wen calls are butted together as) 6. @) You have w design a G4bit adder. The delay through one adder cell is 1 see and the delay through the multiplexer cell is 2 nsee. Calculate the delay if the adder is designed as (i) tipple exrry adder, (i) camry select adder and (Ui) carry skip adder. ‘Make any reasonable assumptions ao) (b) Design a 16 bit cary 100K ahead (CLA) adder in 44 block CLA adder. Show the schematic diagram of the complete system and the detailed circuit level implementation ‘of the block. Explain the operation ofthe system. as) () Ina 100 am CMOS process the minimum width of metal is 3A. The metal layer ‘consists of copper conductors of thickness 1 jim. The electro-migration limited maxims current density of copper wire is 5 mA/umn®. Caleulate how many nMOS 9:1 inverters ean tye driven by a minimum sized metal interconnect. Assume the resistance of the driver transistor is 10 kO and Vio = SV. ao) Contd ses PIA Sea BaanBe or seaaianai ‘EEE 453 7. (@) Show the NOR-NOR implementation of a PLA circuit which will provide the following ourputs: ZraBerFed+ Z-abedtaba Zrbersbdrwed (&) Show the circuit level implementation of a 2 x 2 SRAM cell using 6-T SRAM core ‘cell. Clearly show in your design the pre-charge circuit, column select and row select ‘circuits and the sense amplifier circuit, Explain how the read and write operations are performed showing the first row and second column cell as an example. Explain how the sense amplifier accelerates the READ operations. 8, (@) Name the four fault models most commonly used for CMOS circuits and explain them. (b) Theve faults Sy, S: and Oy occurs in the cireult shown (Fig. for Qg{b)). Assuming fault tty the faults. (©) Show the cirenit diagram and device cross-sectional diagram of a one transistor DRAM cell. Explain the operation ofthe cieuit, any Z as) @ @0) oL-4T-1/EEE Date : 29/02/2012 BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA L-4/T-1_B. Se. Engineering Fxaminations 2010-2011 Sub: EEE 453 (vist Full Marks: 210 Time : 3 Hours ‘The figures in the margin indicate fll marks, USE SEPARATE SCRIPTS FOR BACH SECTION SECTION= ‘There are FOUR questions in this Section, Answer any THREE, 1, (@) Ina table show clearly the influence of scaling on L, Wy aw Vio» Vay Na and MOS device characteristics B, Iu, R, C, gate delay +, clock frequency f, dynamic power dissipation per gate P, chip area A, power density and current density. Assume thi constant field scaling is adopted. (‘The symbols have their usual meanings.] (b) Assume that mobility of electeons is thrice that of holes. Show the schematie diagram at transistor level of a unit inverter driving a similar inverter. Clearly mark the aspect ratio of each transistor. What will be the propagation delay ifthe input tothe frst inverter is falling? For this scenario, show the equivalent switch level RC models. Assume that C is the gate capacitance of a unit NMOS transistor. Diffusion capacitance at source oF drain of a unit NMOS transistor is also C. The unit NMOS transistor ean be assumed 10 have effective resistance R, 2. (@) For the following figure, calculate the diffusion parasitic capacitance of transistor 1, (Can when the drain is at 0-V and at Vp ~ 1.8 V. Assume the substrate is grounded. The wansistor characteristics are CJ = 0.98 fFjum?, MJ = 0.36, CISW = 0.22 HF/um, CISWA ~ 0.33 MF/jum, MISW ~ 0.10, MISWG ~ 0.12 and yo ~ 0.75 V at room temperature. Assume 50 nm. The symbols have their usual meanings cons Pa @0) as) asEEE 453 Conta... Q.No. 2 (&) Show that fall ime of an inverter is piven by +Linte-20n] eva Yoo ‘The symbols have ther usual meanings (a) Show that short cireuit dissipation of an inverter is given by, Pan Boo where Vir = wrt tp pulse width “The symbols have thelr usual meanings. (©)A digital system in @ 1.2 V, 100 nm process has 200 million transistor, of which 25 million are in logic gates and the remainder in memory arrays. The average logic transistor width is 12% and the average memory transistor width is 4%, The process has ‘oo threshold voltages and two oxide thicknesses. Subthreshold leakage for OFF devices Is 25 nA/jum for low threshold devices and 0.02 nA/jm for high threshold devices. Gate leakage is 4 nA/um for thin oxides and 0.002 nA/ium for thick oxides. Memories use low leakage devices everywhere. Logic uses low leakage devices in all but 15% of the paths that are most eritcal for performance. Diode leakage is negligible. Estimate the static power consumption. How would the power consumption change if the low leakage devices were not available? 4. (@) Show the process sequence of fabricating an inverter on @ NWELL CMOS process, Cleary show the mask used and the device cross-sectional diagram after cach step. () Show in @ diagram, the origin and model of CMOS latch up in a NWELL process, How latch up can be prevented? SECTION=B “There are FOUR questions in this Section. Answer any THREE. 5. (@) Design an &-bit camy select adder such thatthe total propagation delay is minimized Assume delay of each adder cell is 4 nSee. and propagation delay of the multiplexer is 2 nSee. Derive any equation used in your calculation, and slow the schema diagram of the adder circuit, Compare the delay of the circuit with that ofa ripple carry adder. Contd ps an 0) as) as an anEEE 453 Contd. Q.No. $ (©) Show the circuit diagram of the square Version of a 4 <4 bit array multiplier. Explain the operation of the circuit. 6. (@) (Show the circuit diagram of a2 = 2. SRAM array which uses 6-ransistor memory cell as basic storage cell. Clearly show the row select, column select, pre-charge and sense signal in your (Gi) Explain how the READ and WRITE operation are performed showing the second row and first column cell as an example, (Gil Explain how sense amplifier reduces the READ time of the cel (©) A 4-bit datapath consists of register, ALU and a shifter. Show two possible bus ult architectures of the system such that an addition operation of two operand stored in the register and storing the result back in the register can be computed in atmost two clock eveles, 7. (Using a strvtuted design approach, develop a bus arbitration loge for nline bus such that access fs given to the highest priory Hie. If priority is given according to ascending coder (lino N highest priority) draw the circuit and stick diagram of abasic leaF ell. (©) Draw the Schematic diagram at transistor Level of « CMOS PLA to implement the functions ain aBsed aoabsed 5. @) Draw and explain the operation of ()t-sate pad, i) bidirectional pad with the help of a ruth table ©) In the figure shown below transistor 1 is stuck opens (01). Find all the to patter test veetors that detect the fii Fig. fer &. 84) sy @0) as) an as 20) as)