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AGB GameBoy Advance Register Table
AGB GameBoy Advance Register Table
AGB GameBoy Advance Register Table
Initial
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W
Value
Window Display Flag Display Flag OBJ Frame
Forced OBJ CGB
00 DISPCNT Map Buffer BG Mode R/W 0080h
Blank Hoff mode
OBJ WIN1 WIN0 OBJ BG3 BG2 BG1 BG0 Format No.
V counter
HBlank VBlank V Counter HBlank VBlank
04 DISPSTAT V Count Setting - - Match
Interrupt Interrupt Eval. Status Status
R/W 0000h
Interrupt
Color
08 BG0CNT Size - Screen Base Block Mosaic 0 0 Character Base Block Priority R/W 0000h
Mode
Color
0A BG1CNT Size - Screen Base Block Mosaic 0 0 Character Base Block Priority R/W 0000h
Mode
Area Color
0C BG2CNT Size Screen Base Block Mosaic 0 0 Character Base Block Priority R/W 0000h
Overflow Mode
Area Color
0E BG3CNT Size Screen Base Block Mosaic 0 0 Character Base Block Priority R/W 0000h
Overflow Mode
10 BG0HOFS - - - - - - - Horizontal Offset W 0000h
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W Initial Value
40 WIN0H Window 0 upper- left x-Coordinate Window 0 lower- right x-Coordinate W 0000h
42 WIN1H Window 1 upper- left x-Coordinate Window 1 lower- right x-Coordinate W 0000h
44 WIN0V Window 0 upper- left y-Coordinate Window 0 lower- right y-Coordinate W 0000h
46 WIN1V Window 1 upper- left y-Coordinate Window 1 lower- right y-Coordinate W 0000h
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W Initial Value
OBJ Mosaic BG Mosaic
4C MOSAIC W 0000h
Vertical Size Horizontal Size Vertical Size Horizontal Size
nd Type of Color st
2 target pixel 1 target pixel
50 BLDCNT - - Special Effect R/W 0000h
BD OBJ BG3 BG2 BG1 BG0 BD OBJ BG3 BG2 BG1 BG0
52 BLDALPHA - - - Color Special Effect Coefficient EVB - - - Color Special Effect Coefficient EVA R/W 0000h
SOUND1CN
60 - - - - - - - - NR10 R/W 0000h
T_L
SOUND1CN
62 NR12 NR11 R/W 0000h
T_H
SOUND1CN
64 NR14 NR13 R/W 0000h
T_X
SOUND2CN
68 NR22 NR21 R/W 0000h
T_L
SOUND2CN
6C NR24 NR23 R/W 0000h
T_H
SOUND3CN
70 - - - - - - - - NR30 R/W 0000h
T_L
SOUND3CN
72 NR32 NR31 R/W 0000h
T_H
SOUND3CN
74 NR34 NR33 R/W 0000h
T_X
SOUND4CN
78 NR42 NR41 R/W 0000h
T_L
SOUND4CN
7C NR44 NR43 R/W 0000h
T_H
SOUNDCNT
80 NR51 NR50 R/W
_L
Direct Sound B Direct Sound A DSB DSA
SOUNDCNT Sound 1-4
82 - - - - Output Output R/W 0000h
_H FIFO B L R FIFO A L R Mix Ratio
TIMER TIMER Ratio Ratio
reset Output Output reset Output Output
SOUNDCNT
84 - - - - - - - - NR52 R/W 0000h
_X
PWM modulation
88 SOUNDBIAS - - - - Bias Level R/W 0000h
resolution
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W Initial Value
WAVE_RAM
90 Step 2 Step 3 Step 0 Step 1 R/W -
0_L
WAVE_RAM
92 Step 6 Step 7 Step 4 Step 5 R/W -
0_H
WAVE_RAM
94 Step 10 Step 11 Step 8 Step 9 R/W -
1_L
WAVE_RAM
96 Step 14 Step 15 Step 12 Step 13 R/W -
1_H
WAVE_RAM
98 Step 18 Step 19 Step 16 Step 17 R/W -
2_L
WAVE_RAM
9A Step 22 Step 23 Step20 Step 21 R/W -
2_H
WAVE_RAM
9C Step 26 Step 27 Step 24 Step 25 R/W -
3_L
WAVE_RAM
9E Step 30 Step 31 Step 28 Step 29 R/W -
3_H
A0 FIFO_A_L Sound Data 1 Sound Data0 W -
DMA0DAD_
B6 - - - - - DMA 0 Destination Address W 0000h
H
B8 DMA0CNT_L - - Word Count W
DMA 0 Control
DMA0CNT_
BA Source R/W 0000h
H Transfer Destination
Enable Interrupt Startup Timing - Continuous Address - - - - -
Width Address Control
Control
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W Initial-Value
DMA 1 Control
DMA1CNT_
C6 R/W 0000h
H Transfer Source Address Destination
Enable Interrupt Startup timing - Continuous - - - - -
Width Control Address Control
C8 DMA2SAD_L DMA 2 Source Address W 0000h
DMA2SAD_
CA - - - - DMA 2 Source Address W 0000h
H
CC DMA2DAD_L DMA 2 Destination Address W 0000h
DMA2DAD_
CE - - - - - DMA 2 Destination Address W 0000h
H
D0 DMA2CNT_L - - Word Count W
DMA 2 Control
DMA2CNT_
D2 R/W 0000h
H Transfer Source Address Destination
Enable Interrupt Startup timing - Continuous - - - - -
Width Control Address Control
D4 DMA3SAD_L DMA 3 Source Address W 0000h
DMA3SAD_
D6 - - - - DMA 3 Source Address W 0000h
H
D8 DMA3DAD_L DMA 3 Destination Address W 0000h
DMA3DAD_
DA - - - - DMA 3 Destination Address W 0000h
H
DC DMA3CNT_L Word Count W 0000h
DMA 3Control
DMA3CNT_
DE R/W 0000h
H Transfer Source Address Destination
Enable Interrupt Startup timing DREQ Continuous - - - - -
Width Control Address Control
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W Initial-Value
Timer 0 Control
102 TM0CNT_H Count R/W 0000h
- - - - - - - - Operation Interrupt - - - Up Prescalar
Timing
104 TM1CNT_L Timer 1 Setting R/W 0000h
Timer 1 Control
106 TM1CNT_H Count R/W 0000h
- - - - - - - - Operation Interrupt - - - Up Prescalar
Timing
108 TM2CNT_L Timer 2 Setting R/W 0000h
Timer 2 Control
10A TM2CNT_H Count R/W 0000h
- - - - - - - - Operation Interrupt - - - Up Prescalar
Timing
10C TM3CNT_L Timer 3 Setting R/W 0000h
Timer 3 Control
10E TM3CNT_H Count R/W 0000h
- - - - - - - - Operation Interrupt - - - Up Prescalar
Timing
Initial-
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W
Value
SIODATA32_
L(32bit
20 Normal SIO), 32Bit Normal SIO Communication Data and Multi-play Communication Data 0 R/W 0000h
SIOMULTI0(
Multi Play)
SIODATA32_
H(32bit
22 Normal SIO), 32Bit Normal SIO Communication Data and Multi-play Communication Data 1 R/W 0000h
SIOMULTI1(
Multi Play)
24 SIOMULTI2 Multi-play Communication Data 2 R/W 0000h
Initial-
ddr Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 R/W
Value
JOY Bus Communication Control
Device
140 JOYCNT R/W 0000h
Send Receive reset
- - - - - - - - - Interrupt - - -
Complete Complete signal
receive
JOY_RECV_
150 JOY Bus Communication Receive Data 0 R/W 0000h
L
JOY_RECV_
152 JOY Bus Communication Receive Data 1 R/W 0000h
H
JOY_TRANS
154 JOY Bus Communication Send Data 0 R/W 0000h
_L
JOY_TRANS
156 JOY Bus Communication Send Data 1 R/W 0000h
_H
JOY Bus Communication Receive Status
158 JOYSTAT Send Receive R/W 0000h
General
- - - - - - - - - - Status - Status -
Purpose Flag
Flag Flag
Interrupt Enable Flag
200 IE R/W 0000h
Game TMR TMR V Counter H V
- - Key DMA 3 DMA 2 DMA 1 DMA 0 SIO TMR3 TMR0
Pak 2 1 Match Blank Blank