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Pid - Kopia
Pid - Kopia
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: This code is a result of the VLSI lab case study for 5th
-- Semester students.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pid is
Port ( ADC_DATA : in STD_LOGIC_VECTOR (15 downto 0); --16 bit unsigned PID
input
DAC_DATA : out STD_LOGIC_VECTOR (15 downto 0); --16 bit unsigned PID
output
CLK1 : in STD_LOGIC);
end pid;
architecture Behavioral of pid is
type statetypes is (Reset, --user defined type to determine the flow
of the system
CalculateNewError,
CalculatePID,
DivideKg,
Write2DAC,
SOverload,
ConvDac);
begin
PROCESS(CLK1,state) --sensitive to Clock and current state
variable Output_Old : integer := 0;
variable Error_Old : integer := 0;
BEGIN
IF CLK1'EVENT AND CLK1='1' THEN
state <= next_state;
END IF;
case state is
when Reset =>
sAdc <= to_integer(unsigned(ADC_DATA)); --Get the input for PID
next_state <= CalculateNewError;
Error_Old := Error; --Capture old error
Output_Old := Output; --Capture old PID output