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FPGA Based Implementation of Variable-Voltage Variable-Frequency Controller For A Three Phase Induction Motor
FPGA Based Implementation of Variable-Voltage Variable-Frequency Controller For A Three Phase Induction Motor
FPGA Based Implementation of Variable-Voltage Variable-Frequency Controller For A Three Phase Induction Motor
AbstractThis paper presents the design and implementation [2]. This is particularly true in case of high performance drive
of a Variable-Voltage Variable-Frequency (VVVF) Controller systems, uninterruptible power supply and programmable AC
based on Sinusoidal Pulse Width Modulation (SPWM) Technique power sources. Since PWM inverters play an important role
for a 3 Phase Induction Motor using a Field Programmable Gate
Array (FPGA). The work involves implementation of an Open in each of these applications, the whole system is depen-
loop control scheme for an induction motor. The technique is used dent on the algorithm controlling the PWM inverter [3]. In
extensively in the industry as it provides the accuracy required recent years, Field Programmable Gate Arrays have drawn
at minimal cost. Voltage/ frequency (v/f) controlled motors fall much attention due to its short design cycle, low cost and
under the category of Variable Voltage Variable Frequency high flexibility in terms of programmability. The Field Pro-
(VVVF) drives. To maintain maximum torque for a given working
condition, the flux in the machine must be maintained constant. grammable Gate Arrays (FPGAs) offer significant advantages
In other words, the ratio of Voltage to frequency must be over microprocessors and DSPs for high performance, low
held constant. For Variable Voltage Variable Frequency (VVVF) volume applications, particularly for applications that can
drives, there is a need to control the fundamental voltage of exploit customized bit-widths and massive instruction-level
the inverter if its frequency (and therefore the frequency of the parallelism. The innovative development of FPGAs whose
induction motor), need to be varied. To vary the fundamental
component of the inverter, the Modulation Index of the carrier configuration could be re-programmed an unlimited number
signal has to be changed. The speed at rated supply frequency of times spurred the invention of a new field in which many
is normally used as the base speed. At frequencies below the different hardware algorithms could execute, in turn, on single
base speed, the supply magnitude needs to be reduced so as to device, just as many different software algorithms can run on
maintain a constant Volt/Hertz. The FPGA controller is used to a conventional processor [4]. When comparing the dynamic
generate SPWM pulses based on the frequency input, that are
used to control the inverter. The VVVF output of the inverter can performance, control capabilities and concurrency in PWM-
be used as supply to a three phase induction motor and thereby controlled Power Converters, FPGA based digital techniques
speed of the motor can be controlled. are better than DSPs [5] [6]. The paper is organized with
the Introduction in section I, followed by a brief report on
speed control of three phase induction motor in section II.
I. INTRODUCTION
The capability of the proposed system is explained in Section
Controlling the speed of induction motors has ever since III. Section IV includes the results obtained from the FPGA
been an important topic of research. The control methodolo- controller with the conclusion in section V.
gies have evolved from electromechanical switching to high
speed digital controllers using DSP and FPGA [1]. Of late, II. SPEED CONTROL OF INDUCTION MOTOR
Pulse-Width Modulation techniques have been the subject
The synchronous speed of the induction motor is given by:
of intensive research; as PWM controlled power electronic
devices find increasing applications in many new industrial 120f
Ns = (1)
processes involving more stringent performance specifications p
Krishna Chandran Vinay is a Masters student in the Department of where f is frequency and p is number of poles.The running
Electrical Engineering: Systems, University of Michigan, Ann Arbor, USA, speed of the induction motor is given by the equation:
with a concentration in Control Systems and Power. He received his Bachelors
degree from National Institute of Technology, Trichy, India. His areas of inter- Nr = Ns (1 s) (2)
est include Feedback Control Design, Power Electronics, and Battery Systems,
especially for Electric Vehicle applications. (e-mail: kcv@umich.edu) where s is slip of the induction motor expressed in terms
Shyam H N completed his B.Tech (EEE) in the Department of Electrical of percentage. The speed control can be performed using
and Electronics Engineering, National Institute of Technology, Tiruchirappalli,
INDIA during April 2010. His area of interest includes research and analysis open loop algorithms or closed loop algorithms. The most
of alternative and sustainable energy systems. commonly used open loop algorithm is Voltage/ frequency
Rishi S. is a B.Tech student in the Department of Electrical and Electronics control method [7]. Closed loop algorithms include sensor and
Engineering, National Institute of Technology, Tiruchirappalli, INDIA. His
area of interest includes VLSI Systems and Electronic circuit design. sensorless feedback using scalar or vector control. Open loop
Dr. S. Moorthi is a faculty in the Department of Electrical and Electronics control of induction motor is used extensively in the industry
Engineering, National Institute of Technology, Trichy, India. He completed as it provides the accuracy required at minimal cost. Voltage/
his Ph.D in the area of VLSI for Communication circuits. His area of interest
includes VLSI for signal processing and Embedded systems. (*Corresponding frequency controlled motors fall under the category of Variable
author: srimoorthi@nitt.edu). Voltage Variable Frequency drives which are fed by an inverter
= m sin(1 t) (3)
DC bus voltage is applied at the output. Note that, over the
But the back emf is:
period of one triangle wave, the average voltage applied to the
d load is proportional to the amplitude of the signal (assumed
e1 = N = N 1 m cos(1 t) (4)
dt constant) during this period. The resulting chopped square
In RMS, waveform contains a replica of the desired waveform in its low
e1 = 4.44N f1 m (5) frequency components, with the high frequency components
being at frequencies close to the carrier frequency [8]. Also,
The modes of operation of a VVVF drive working under the root mean square value of the AC voltage waveform is
Constant V/f control method is given in Figure 1. Figure 2 still equal to the DC bus voltage and hence the total harmonic
shows the variation of Voltage V with respect to frequency distortion is not affected by the PWM process. The harmonic
in a V/f control scheme. At all frequencies above the rated components are merely shifted to the high frequency range and
frequency, the voltage is maintained at the rated value. At are automatically filtered due to inductances in the AC system.
low frequencies below 5 Hz, the Voltage is maintained at a When the modulating signal is a sinusoid of amplitude Am ,
minimum fixed value. Voltage/ frequency control is based on and the amplitude of the triangular carrier is Ac . The ratio
the following assumptions: The motor impedance increases of the amplitude of the modulating signal to the amplitude of
when the frequency increases and there should be a fixed the carrier signal is called the modulation index. Therefore,
current as much as possible. So that it is simple to increase the controlling the modulation index controls the amplitude of the
motor speed by increasing the frequency and the related volt- applied output voltage. Modulation index,
age. Variable-frequency drives are widely used in ventilation
Am
systems for large buildings, variable-frequency motors on fans m= (6)
save energy by allowing the volume of air moved to match the Ac
system demand. They are also used on pumps, conveyor and From figure 4, it can be seen that Distortion Factor is about 4-5
machine tool drives. In the most straightforward implementa- in case of multi-pulse, and this value is considerably reduced
tion of Sinusoidal Pulse Width Modulation, generation of the to about 0.8-1 in case of SPWM. Hence, SPWM is preferred
desired output voltage is achieved by comparing the desired over multi-pulse for producing gate-pulses for inverters.
reference waveform (modulating signal) with a high-frequency
triangular carrier. wave as depicted schematically in Figure.3. III. THE PROPOSED SYSTEM
Depending on whether the signal voltage is larger or smaller The system block diagram with various modules is shown
than the carrier waveform, either the positive or negative in Figure 5. The FPGA controller produces the SPWM pulses
Oscillator Clock
Frequency,
Multiplexed Initial Phase
Data (8 bit)
(Frequency, Oscillator
Amplitude,
Initial Phase)
Interface
Input Selection
(2 bit) Phase Value
(0 to 360 deg )
Enable
(1 bit)
V cc = +12V
1K 1K
10 K
Output
Fig. 13. Experimental Setup of the proposed system
1K
2N2222 2N2222
Input
GND
here, to have both half wave and quarter wave symmetry, Fig. 14. Inverter IGBT Gate pulse for f=25 Hz
the counter counts from zero to 512. Such symmetry greatly
reduces inverter harmonics. The comparator outputs low if the
value of the count is between (256-input) and (256+input), and H. Clock divider module
high otherwise, thus resulting in both half wave and quarter The internal clock on the Spartan 3 E FPGA has a frequency
wave symmetry. This entity also generates the clock for the of 50 MHz, which would result in a PWM signal with
oscillator which clearly has to have a frequency 1/512 times switching frequency approximately 200 kHz, which is too high
the clock used for the countercomparator pair. From the three for the inverter being used. To bring this switching frequency
SPWM signals, six gate driving pulses have to be generated. down to about 10 kHz, the internal clock frequency has to be
The pulses for one of the branches of the inverter have to be divided by 250. This is done by the entity clock divider, using
phase shifted by 180 and those for two adjacent branches a counter that counts from 0 to 249 and outputs high when
have to be phase shifted 120 . Thus, to generate the two out- the counter value less than 125 and low otherwise. Thus this
of-phase pulses from a single pulse, the following steps are entity takes a clock signal as input and gives a clock signal
done: 1. Zero crossing is detected, 2. the pulses representing of (1/256) times the frequency of the input as output.
the positive half cycle of the Sinusoid form the first pulse are
generated. 3. The pulses representing the negative half cycle
are inverted to form the second pulse are generated. 4. The I. Voltage level shifting circuit
process is repeated for the other two phases. The final pulses The FPGA outputs PWM Pulses consisting of highs and
generated for two the IGBTs in any one of the branches will lows, where a high is 3.3 V and a low is 0. However, to drive
be as shown in figure 11. the inverter model in use, the high of the pulses must be at 12
V. Hence a circuit, as shown in figure 12, to shift the voltage
level of the pulses from 3.3 Volts to 12 Volts was designed.
G. Top level module Hence, upon using a Vcc of 12 V, the level shifted pulses can
be obtained and fed to the inverter.
This is the top-level entity in which copies of all the other
entities are instantiated. In other words, this is the entity that
takes the inputs to the FPGA, viz. The 8 bit data signal, the J. Inverter module
two bit selection signal, the enable signal and the clock, and The three Phase Inverter Module (as shown in figure 13)
gives the three PWM sinusoids as outputs, using instances of consists of a three phase voltage source inverter with its gate
each of the above mentioned entities. driver circuits. All six SPWM gate-driving pulses have to
inverter to produce a proper supply voltage which is fed to
drive the three phase induction motor.
R EFERENCES
[1] R.Nandhakumar, S.JeevananthanP.Dananjayan, Design and Implementa-
tion of an FPGA-Based High Performance ASIC for Open Loop PWM
Inverter, IICPE, 2006, pp.349-354.
[2] Arulmozhiyal, R. Baskaran, K. Devarajan, N. Kanagaraj, Space Vector
Pulse Width Modulation Based Induction Motor Speed Control Using
FPGA, ICETET, 16-18 Dec 2009, pp 242-247.
[3] Nitish Patel, UdayaMadawala, A Bit stream based scalar control of an
Fig. 15. Phase Voltages at f=50 Hz Induction Motor,IECON, 2008, pp. 1071-1076.
[4] Maya Gokhale, and Paul S.Graham (2005), Reconfigurable Comput-
ing Accelerating Computation with Field-Programmable Gate Arrays,
Springer.
[5] A. Fratta, G. Griffero, and S. Nieddu (2004), Comparative analysis among
DSP and FPGA-based control capabilities in PWM power convertersin
Proceedings of the 30th Annual Conference of the IEEE Industrial
Electronics Society (IECON .04). Novemeber: 257.262.
[6] de Castro, A., P. Zumel, O. Garcia, T. Riesgo, and J. Uceda (2003),
Concurrent and simple digital controller of an AC/DC converter with
power factor correction based on an FPGA,IEEE Transactions on Power
Electronics. 18(1 Part2): 334343.
[7] AungZawLatt Ni Ni Win,Variable Speed Drive of Single Phase Induction
Motor Using Frequency Control Method,International Conference on
Education Technology and Computer, 2009.ICETC 09. 7-20 April 2009,
pp 30-34.
[8] Guay, L. Salmon, J., DSP Speed Control of Single-Phase Induction Mo-
Fig. 16. Line voltage at f=12.5 Hz tor Using C Programming,IEEE International Symposium on Industrial
Electronics, 9-13 July 2006, pp 246-251.
V. C ONCLUSION
The open loop control scheme for a three phase inverter is
implemented using FPGA. The versatility in FPGA program-
ming makes the designer to implement an efficient controller
in it. The most important factor in support of using FPGA
based designs is that it can be started from scratch and the
design can be improved along the way by continuously testing
and improving the code. One noteworthy fact is that the
first version of the VHDL model used 64 per cent of the
FPGA resources, and the final version uses only 8 per cent
of the resources. Furthermore, using a digital controller make
the system less susceptible to noise, temperature and other
environmental factors. More significantly, the controller size
and complexity is considerably reduced. The reconfigurable
feature of FPGAs makes it more flexible. In conclusion, the
VVVF controller is successfully implemented using FPGA and
the experimental results show that the controller enables the