Design of RISC Processor Using VHDL and

Cadence
Saeid Moslehpour#1, Chandrasekhar Puliroju#2, Akram Abu-aisheh#3
#1,#2#3
Department of Electrical and Computer Engineering, University of Hartford, West Hartford, CT
#1
moslehpou@hartford.edu
#2
puliroju@hartford.edu
#3abuaisheh@hartford.edu

programs. It is also important to show that a VHDL model can

Abstract The project deals about development of a basic be represented in a working PSPICE schematic. Each part of a
RISC processor. The processor is designed with basic processor, whether it be an Arithmetic Logic Unit or a simple
architecture consisting of internal modules like clock generator, Program Counter- has a specific set of input and output logic
memory, program counter, instruction register, accumulator,
that can be emulated from PSPICE. If the logic is already
arithmetic and logic unit and decoder. This processor is mainly
used for simple general purpose like arithmetic operations and known to the user, then the user does not have to build the part
which can be further developed for general purpose processor by using each individual logic gate. Instead, a circuit designer can
increasing the size of the instruction register. The processor is create a PSPICE part that gives the desired logical outputs.
designed in VHDL by using Xilinx 8.1i version. The present Most importantly, this study can help bridge a gap between
project also serves as an application of the knowledge gained those who simulate with VHDL and those who use PSPICE.
from past studies of the PSPICE program. The study will show
how PSPICE can be used to simplify massive complex circuits
designed in VHDL Synthesis. The purpose of the project is to III. METHODOLOGY
explore the designed RISC model piece by piece, examine and The following VHDL synthesis model provided is an
understand the Input/ Output pins, and to show how the VHDL attempt toward a RISC processor. First, a data path module of
synthesis code can be converted to a simplified PSPICE model. the processor will be shown which clearly shows how the
The project will also serve as a collection of various research
individual modules are going to send the data from one
materials about the pieces of the circuit.
module to the other and then a screenshot will be shown of the
top-module view to show each piece of the processor from an
I. INTRODUCTION
outside perspective (with view of all modules)
The present project serves as an application of the
knowledge gained from past studies of the PSPICE program.
The study will show how PSPICE can be used to simplify
massive complex circuits. In other words, the study will
involve the breakdown of a complex circuit designed by a
graduate student at the University of Hartford. The circuit is a
VHDL Synthesis Model of an 8-bit processor. The purpose of
the project is to explore the designed processor model piece by
piece, examine and understand the Input/ Output pins, and to
show how the VHDL synthesis code can be converted to a
simplified PSPICE model. The project will also serve as a
collection of various research materials about the pieces of the
circuit. Background information will be given to give the
reader a basic understanding of the parts to support the further
exploration in the project methods. This report is useful for
students who would like to know more about the PSPICE
program and how it is useful for many educational purposes.

II. SIGNIFICANCE OF THE PROJECT

The study of VHDL and PSPICE is important because
technology students are using computer software to design and
analyze circuits. A better understanding of computers and
computer languages can be gained when exploring these
Figure 1 Data path module of the processor

K. Elleithy (ed.), Advanced Techniques in Computing Sciences and Software Engineering,

DOI 10.1007/978-90-481-3660-5_89, Springer Science+Business Media B.V. 2010
518 MOSLEHPOUR ET AL.

generated. The data operand is loaded on to the data bus and

transferred to the ALU for its respective micro operations as
specified by its opcode. In the second case the address of the
data operand is loaded onto the address bus (As the fetch
signal is low and the multiplexer loads the IRs address
contents onto the address lines) and a memory read cycle is
initiated. Here the memory location in the main memory
specified by the address lines is read and the data is transferred
onto the data bus and thus given the ALU to undergo the
operations specified by its opcode.
The results of the ALU are stored in the accumulator. Data
operations may be combined with the memory contents and
the accumulator and the result is transferred back to the
accumulator. The function of the NOR gate is that when ever
all inputs are low the output is high and at all other times
remains low. It is attached to tri-state buffer. When the tri-
state buffer is enabled the data from ALU is fed to the
memory thus allowing the data to be stored into the memory.
When disabled the data is given to all and cut off from being
written onto the data bus. Whenever there results a zero in the
ALU a zero flag is set.

A. CLOCK GENERATOR

Figure 2 Screenshot of VHDL synthesis top module

If one is familiar with PSPICE, it would not be hard to

recognize the style of the schematic. However this is not a
PSPICE model, yet only a graphical representation of the
VHDL synthesis. It may not be clear in the above screen shot,
however the complete processor contains nine separate
modules. These modules include: Program Counter (PC), Figure 3 Clock generator
Clock Generator, Instruction Register, ALU, Accumulator,
Decoder, IO Buffer, Multiplexer, and Memory. All of these Clock generator generates clock, clock2, fetch signals. For
pieces with the appropriate busses form together to create a every negative edge of clock, clock2 is generated and for
processor capable of storing, loading, and performing every positive edge of clock2, fetch signal is generated.
arithmetic and logical operations. This processor only contains Clock2 is generated from clock and fetch is generated from
one accumulator which means that the two operands in a clock2. They are used as the inputs to the decoder which
mathematical operation will not be loaded simultaneously. controls the operation of the processor. It generated reset pulse
The accumulator acts as a simple buffer to hold a value so that which must be active low. The reset should allow the rest of
the next operand can be loaded. the signals to go high on falling edge of clock2 when fetch is
To read an instruction, the contents of Program counter are low.
transferred to the address lines. This is done when the fetch
signal is high and the address multiplexers chooses the
contents of the Program counter to be loaded on to the address B. INSTRUCTION REGISTER
bus. As soon as the contents of the program counter are
loaded onto the address bus a memory read cycle is initiated
and the instruction is read from the location pointed out by the
address lines and the micro instruction code is placed onto the
data bus. The program counter is incremented to point to the
next micro instruction in the memory location of the control
memory. The data bus transfers the micro instruction to the
Instruction Register. The instruction register has two fields, in
the different formats namely,
1. Opcode, data operand.
2. Opcode, Address of data operand.
During the first case the opcode is given to the ALU and
decoder for decoding and a series of micro operation are Figure 4 Instruction Register