Computer Organization (Jin, Hatfield)

COMPUTER ORGANIZATION
PRINCIPLESANALYSISAND DESIGN

LAN J IN

BO HATFIELD

CIP
COMPUTER ORGANIZATIONPRINCIPLESANALYSISAND DESIGN/

LAN JINBO HATFIELD .
.

ISBN ---
. . JIN B .
. TP
CIP

http/ / www. tup. com. cn
- -

ISBN --- / TP

Dr . Lan J in

Dr . Bo Hatfield

?
?
?

?
?
?
?
?

?
?

The Scope of the Book

!""#$%& &()*+(*# &#,#&

-.),#)/0.)(& $(120)# .3 3#*0"/#3 /3()"4#3 &#,#&

5013.63.*3($$0)* &#,#&
70*0/(& &.*01 &#,#&

!8,()1#8 1.$6+/#3 .3*()09(/0.)

Use of the Book

A.

B.

C.

D.

Acknowledgments

CHAPTER 1 INTRODUCTION
!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 2 THE REPRESENTATION OF INFORMATION IN A COMPUTER
!!!!!!!!!!!!
!!!!!!!!!!!!!

!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 3 LOGIC DESIGN OF COMBINATIONAL CIRCUITS
!!!!!!!!!!!!!!
!!!!!
!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!

!!!!!!!!!!!!!!
!!!!!!!
!!!!!!!!!!
!!!!!!!!!

!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 4 LOGIC DESIGN OF SEQUENTIAL CIRCUITS
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 5 THE ARITHMETIC LOGIC UNIT
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!!!
!!!!
!!!!!!!!!
!!!!!!!!!!!!
!!!!!!
!!!!!!!!!!!
!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

CHAPTER 6 COMPLEX ARITHMETIC OPERATIONS
!!!!!!!!!!!!!!!!!!!!
!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!
!

!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!
!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!
!!!!

!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 7 INSTRUCTION SET ARCHITECTURE
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!
!!
!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 8 THE CENTRAL PROCESSING UNIT
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!
!!!!
!!!!
!!!!!!
!!!!!!!!
!!!!!!!!!!
!!!!!!!

!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 9 THE CONTROL UNIT
!!!!!!!!!!!
!!!!!!!!!!!!!!!
!!!!!!!!!
!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!

!!!!!!!!!
!!!!!!!!!!!!!!!!!!

!!!!!!!
!!!!!!!!!!!!

!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!
!!!!!!!!!

!!!
!!!!!!!
!!!!!!!
!!!!!!!
!
!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 10 PRIMARY MEMORY
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!
!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!
!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 11 INPUT / OUTPUT
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!

!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!
!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!

!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
CHAPTER 12 PIPELINING
!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!

!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!
!!!!!!!!

!!!!!!!!!!!
!!!!!!!
!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!

!!!!!!!!!!!
!!!!!!!!!

!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
INTRODUCTION
1. 1 The Scope of Computer Architecture and Organization
1. 2 Modeling Computer Or ganization
1. 2. 1 The Layer ed Str uctur e of Computer Design Pr ocess

1. 2. 2 The RTL Model of Computer Or ganization

1

!"# $%&(

!&)*%&+ $%&(

,-.&%/ $%&(

?

?

?

?
?

1. 2. 3 The Per for mance Model of a Computer System

Example 1. 1

1
Table 1. 1 The fr equency of usage and CPI for four types of instr uctions

Example 1. 2

1. 3 A Histor ical Sketch of Computer Evolution
1. 4 Repr esentative Computer Families
1. 4. 1 The Pentium Family

?

?

?

?

?
1. 4. 2 The SPARC Family

1. 4. 3 The Power PC Family

1. 5 Per spectives of the Computer Evolution
1. 5. 1 The Challenges of a Billion-Tr ansistor IC

1. 5. 2 The New Role of the Next-Gener ation PC

1

1. 5. 3 Embedded Systems

1

Specialization

Customization

Automation

1. 6 Summar y

THE REPRESENTATION OF
INFORMATION IN A COMPUTER
2. 1 Data Types Representing Information in a Computer
2. 2 Repr esentation of Fixed-Point Unsigned Number s
2. 2. 1 The Gener al Positional Number System

2

1. The Decimal System

2. The Binar y System

3. The Octal System

2

4. The Hexadecimal System

Example 2. 1

2. 2. 2 The Repr esentation of Fr actional Number s

Example 2. 2

2

2. 2. 3 Conver sion Between Number s of Differ ent Repr esentations

1. Conver sion of an integer fr om decimal to binar y using binar y ar ithmetic

Example 2. 3

2. Conver sion of an integer fr om decimal to binar y using decimal ar ithmetic

while &&
if

else

if

else
for

Example 2. 4

2

3. Conver sion of a fr actional number fr om decimal to binar y using decimal ar ithmetic

while &&
if

else

for

Example 2. 5

2. 3 Repr esentation of Fixed-Point Signed Number s
2. 3. 1 Sign-Magnitude Repr esentation

Table 2. 1 Number s r epr esented in sign-magnitude notation in a descending or der
2. 3. 2 Two' s Complement Repr esentation

Table 2. 2 Number s r epr esented in two' s complement notation in descending or der

Example 2. 6

Example 2. 7

2. 3. 3 Motivation for the Two' s Complement System

2

2. 3. 4 One' s Complement Repr esentation

2

Table 2. 3 Number s r epr esented in one' s complement notation in descending or der
Example 2. 8

2. 4 Binar y Addition / Subtr action
2. 4. 1 Sign-Magnitude Addition / Subtr action

2

Example 2. 9

2. 4. 2 Two' s Complement Addition / Subtr action

2

Table 2. 4 The cases of the sign and car r y bits in two' s complement addition / subtr action

Example 2. 10

Example 2. 11

2. 4. 3 One' s Complement Addition / Subtr action

Example 2. 12

2. 5 Other Code Systems Using Bit Str ings
2. 5. 1 Gr ay Codes

Table 2. 5 Gr ay code

2. 5. 2 Decimal Codes

Table 2. 6 Decimal codes

if
then

else
if
then
else

2. 5. 3 Char acter Codes

Table 2. 7 ASCII codeb6 b5 b4 b3 b2 b1 b0

2. 6 Summar y
Exer cises
Pr oblem 2. 1

2

Table 2. 8 Table of answer s to Pr oblem 2. 1
Note

Pr oblem 2. 2


Pr oblem 2. 3

Pr oblem 2. 4

Pr oblem 2. 5

Pr oblem 2. 6

Pr oblem 2. 7

Pr oblem 2. 8

2

Pr oblem 2. 9

Pr oblem 2. 10

Pr oblem 2. 11

Pr oblem 2. 12

Pr oblem 2. 13

Pr oblem 2. 14

Note
LOGIC DESIGN OF
COMBINATIONAL CIRCUITS
3. 1 Combinational Logic Functions and Expr essions
3. 1. 1 Using Tr uth Table to Define a Combinational Logic Function

Table 3. 1 The tr uth tables of 16 two-var iable and one-var iablelogic functions

3. 1. 2 Pr imitive Combinational Functions and Basic Logic Oper ations

3

Table 3. 2 Tr uth tables for defining 16 pr imitive logic functions and basic logic oper ations

AND

OR

XOR

NOT

XNOR

NAND

NOR

AND NAND
OR NOR
XOR XNOR

3. 1. 3 Boolean Algebr a and Logic Expr ession

3

3. 1. 4 Canonical Logic Expr essions

1. Sum-of-pr oducts SOPfor m wr itten fr om the output values ' 1' of the function

Example 3. 1

Table 3. 3 Der iving the canonical SOP expr ession for the Exclusive-OR function

2. Pr oduct-of-sums POSfor m wr itten fr om the output values ' 0' of the function

Example 3. 2

Table 3. 4 Der iving the canonical POS expr ession for the Exclusive-OR function

2n - 1
F = fi mi
i =0
2n - 1
F = fi + Mi
i =0
3. 2 Kar naugh Maps for Simplification of Logic Functions

1. Cor r espondence with the Tr uth Table or the Canonical SOP Expr ession

2. Labeling Rule

3. Simplification Rule

4. Wr iting the Maximally Simplified Expr ession

Example 3. 3

Example 3. 4

5. Don' t Car e Conditions

Example 3. 5

3

3. 3 Implementation of Combinational Logic Functions
3. 3. 1 ANDORand NOT Gates

Example 3. 6

Table 3. 5 Mapping a physical table to a logic table using positive logic

Table 3. 6 Mapping a physical table to a logic table using negative logic

3. 3. 2 NAND and NOR Gates

Example 3. 7

Example 3. 8

3

3. 3. 3 XOR and XNOR Gates

3. 4 Design of Combinational Logic Cir cuits
3. 4. 1 Design of a Full Adder

Table 3. 7 The tr uth table of a full adder

3. 4. 2 Ripple-Car r y Adder / Subtr actor with Exter nal Logic for

Subtr action

3

Table 3. 8 The function table of a par allel adder / subtr actor

Table 3. 9 The tr uth table of a par allel adder

3. 4. 3 Double Pr ecision Addition / Subtr action

3

Step 1

Step 2

Step 3

Step 4
Step 5

Example 3. 9

3. 4. 4 Ripple-Car r y Adder For Sign-Magnitude Repr esentation

Table 3. 10 Deter mining the oper ation on the magnitude par ts of A and B
3. 5 Dynamic Char acter istics of Combinational Logic

Cir cuits
3. 5. 1 Pr opagation Delay of Combinational Logic Cir cuits

3. 5. 2 Wavefor m Diagr am of Combinational Logic Cir cuits

3

Example 3. 10

Table 3. 11 The output changes and delays for the input tr ansitions in a binar y sequence

3. 5. 3 Hazar ds in Combinational Logic Cir cuits

3

Example 3. 11

Example 3. 12

3

3. 6 Combinational MSI Modules
3. 6. 1 Multiplexer
Table 3. 12 The tr uth table of a 8 1 multiplexer
Example 3. 13

m

Table 3. 13 The tr uth table of a function implemented by a multiplexer
3. 6. 2 Decoder / Demultiplexer
Table 3. 14 The tr uth table of a 3 8 decoder
3. 6. 3 Encoder
Table 3. 15 The tr uth table of an 8 3 encoder
Table 3. 16 The tr uth table of an 8 3 pr ior ity encoder

3. 7 Pr ogr ammable Logic Devices
3. 7. 1 Pr ogr ammable Logic Ar r ay PLA

Example 3. 14

3. 7. 2 Read-Only Memor y ROM

3

Example 3. 15

3. 7. 3 Pr ogr ammable Ar r ay Logic PAL

Example 3. 16

3. 7. 4 Complex Pr ogr ammable Logic Devices CPLDs

Table 3. 17 The function table of the macr ocell in Figur e 3. 32
Example 3. 17

3. 7. 5 Field-Pr ogr ammable Gate Ar r ays FPGAs

3. 8 Summar y
Exer cises
Pr oblem 3. 1

Pr oblem 3. 2

Pr oblem 3. 3

3

Pr oblem 3. 4

Pr oblem 3. 5

Pr oblem 3. 6

Pr oblem 3. 7

Pr oblem 3. 8

Pr oblem 3. 9

Pr oblem 3. 10

Pr oblem 3. 11

Pr oblem 3. 12

3

Pr oblem 3. 13

Pr oblem 3. 14

Pr oblem 3. 15

Note

Pr oblem 3. 16

Pr oblem 3. 17

Pr oblem 3. 18

Pr oblem 3. 19

Pr oblem 3. 20

Pr oblem 3. 21

Pr oblem 3. 22

3

Pr oblem 3. 23

Pr oblem 3. 24

Pr oblem 3. 25

LOGIC DESIGN OF
SEQUENTIAL CIRCUITS
4. 1 Gener al Model of Sequential Cir cuits

A

4

4. 2 Flip ?
Flops
?

?

?
?

?

4. 2. 1 Analysis of A Simple SR Latch

?
?

?

?

?

?

Table 4. 1 The state tr ansition table of an SR latch

?

?

Table 4. 2 The r educed state tr ansition table of an SR latch

? ?
?
? ? ?
4. 2. 2 SR Flip ?
Flop
?

?
?

?

?

?

?

?

4

Table 4. 3 The excitation table of an SR flip?
flop

?
?
4. 2. 3 J K Flip ?
Flop
?
?

?
?

?

?

?

?

?

?

Table 4. 4 The state tr ansition table of a J K flip?
flop
Table 4. 5 The r educed state tr ansition table of a J K flip?

flop

Table 4. 6 The excitation table of a J K flip?

flop
?

4

4. 2. 4 T Flip ?
Flop
?
?

?

?

?

?

Table 4. 7 The state tr ansition table of a T flip?
flop
Table 4. 8 The r educed state tr ansition table of a T flip?

flop

Table 4. 9 The excitation table of a T flip?

flop
4. 2. 5 D Flip ?
Flop
?
?

?

?

?

?
?

Table 4. 10 The state tr ansition table of a D flip?
flop

Table 4. 11 The r educed state tr ansition table of a D flip?

flop

Table 4. 12 The excitation table of a D flip?
flop

?

4

4. 2. 6 Pr actical Flip ?
Flop Cir cuits
?
?

?

?

?

?
?

?
?
?

?
?
?
?

?

? ?

?
?
?
?

?
?

?
?
?
?

?
? ?

?

?
?

?

?
?
?

?

?
?

?

?

?

4

?

?

?

?

?

?
?

? ?

?

?
?

S e tup time

Hold time

P ropa ga tion de la y time
?
?

?
?

?

?
?

?
?

?

?
?

? ?
? ?

?
?

?
?

?
?

4

?
?

4. 3 Analysis of Sequential Logic Cir cuits
4. 3. 1 Fr om Cir cuit to State?

Tr ansition Diagr am

?

?

?

?

Example 4. 1

?
?

Table 4. 13 The state tr ansition table for Example 4. 1

?
?

?

?

4. 3. 2 Fr om State ?
Tr ansition Diagr am to Finite State Machine

?

?

?

Table 4. 14 The state tr ansition table after state assignment

?

?

?
?

4. 4 Synthesis of Sequential Logic Cir cuits

?

?

?

4

?

?

?

?

?

?

Example 4. 2 ?

?

?

?

Table 4. 15 The state tr ansition table of Example 4. 2

Table 4. 16 The excitation table of Example 4. 2

?
?
?

?

?

?

4

4. 5 Sequential MSI Modules
4. 5. 1 Register
?

?
?

?

?
?

?
?

?
?

4

4. 5. 2 Shift Register

?

?

? ?

?

4. 5. 3 Counter

?
?

4

?

Table 4. 17 The state tr ansition tables of the up?
counter and the down?
counter
?
?

?
?
?

? ?
?
? ? ?

?

?
?

?

?
?

?

?
?
?

?
?

?
?

? ?

?
?

? ?
?
? ?

?
4

4. 6 Design of a Finite?
State Machine

?

?

?

?

?

?

? ?

?

?

?

?

?

?

?

Example 4. 3 ?

?

?

Step 1

4

?
?

Table 4. 18 State tr ansition table of Example 4. 3

Step 2

Table 4. 19 Minimal state tr ansition table of Example 4. 3

Step 3

?

?
?

?

?

Table 4. 20 The binar y?

coded minimal state tr ansition table of Example 4. 3
Step 4
?

Step 5

4

4. 7 Summar y

?

?

?

?

Exer cises
Pr oblem 4. 1
?

?
?

?
?

?

Pr oblem 4. 2
?
?
?

?

Pr oblem 4. 3
?
?

?
?

?
?

?

?
?

Pr oblem 4. 4

? ?

?

Pr oblem 4. 5
?

4

Pr oblem 4. 6

?

Pr oblem 4. 7
?

Pr oblem 4. 8
?

?
?
?

?
?

Pr oblem 4. 9
?

Table 4. 21 The function table for Pr oblem 4. 9

?
?

Pr oblem 4. 10
?
?


4

Pr oblem 4. 11
?
?

?

?

?

Pr oblem 4. 12
?

?

?

Pr oblem 4. 13
?
?

Note ?

Pr oblem 4. 14
?
?
?

?


Pr oblem 4. 15
?
?

?

?

Pr oblem 4. 16

?
?

?

Pr oblem 4. 17
?
?
?

4

Pr oblem 4. 18
?

THE ARITHMETIC LOGIC UNIT
5. 1 The von Neumann Computer Model

T

5

5. 2 Par allel Fast Adder s
5. 2. 1 The Natur e of Car r y Pr opagation

5. 2. 2 The Ripple-Car r y Par allel Adder Revisited

5

5. 2. 3 The Four -bit Car r y Look-ahead Adder

5. 2. 4 The Block Car r y Look-ahead Cir cuit

5. 3 Analysis of the Design of a Commer cial ALU Chip
5. 3. 1 Or ganization of an ALU Based on an Adder

5

5. 3. 2 Design of the Input Cir cuit for Logic Oper ations

Table 5. 1 Tr uth table for the logic oper ations per for med by an SN74181 ALU when M = 1

Table 5. 2 Reduced tr uth table for X
i Ai Bi Table 5. 3 Reduced tr uth table for Y
i Ai Bi
as functions of s1 and s0 as functions of s3 and s2
5. 3. 3 Analysis of the ALU for Ar ithmetic Oper ations

5

Table 5. 4 Tr uth table for the ar ithmetic oper ations per for med by SN74181 ALU chip when M = 0

111

111

5. 4 Methods for Designing Ar ithmetic-Logic Units
5. 4. 1 Designing the ALU Using Exter nal Gates for Logic Oper ations

Example 5. 1

Table 5. 5 Function table of an ALU for Example 5. 1
Example 5. 2

Table 5. 6 The subtable cr eated for the ar ithmetic oper ations in Example 5. 2
5. 4. 2 Designing an ALU Based on Standar d ALU Chips

Example 5. 3

5

Table 5. 7 The tr uth table of the ALU using SN74181 chips
5. 4. 3 Redesigning the Input Cir cuit for the ALU

5

Example 5. 4

Table 5. 8 Tr uth table of Example 5. 4 for r edesigning the input cir cuit
5. 4. 4 Designing an ALU Using the Inter nal Cir cuit of an Adder

Example 5. 5

5

Table 5. 9 The tr uth table for the synthesis of the ALU in Example 5. 5

5. 4. 5 Redesigning the Output Cir cuit of the Adder

Table 5. 10 Function table of the ALU with the output contr olled by abcand M
Example 5. 6

Table 5. 11 The tr uth table for the ALU with a modified output cir cuit of an adder
5. 4. 6 Compar ison of Differ ent Methods of Designing an ALU

Table 5. 12 Compar ison of the six methods of designing ALUs
5. 5 Incor por ating a Shifter in an ALU

!"#$ %& &()$ *)#$+
5

!%(,-. %& -&$)/"$, *)#$

0%1 ,2,., %& ,2,., *)#$

3%$-$" 4$) %& 4$)%5$ ,-&&2 *$-$5* 16%.6"7

5. 5. 1 Design of a Built-in Shifter in an ALU

Example 5. 7

Table 5. 13 The function table of a simple ALU with a built-in shifter

Table 5. 14 Tr uth table of the simple ALU with a built-in shifter

5

Example 5. 8

5

Table 5. 15 The function table of a simple ALU with a built-in shifter

Table 5. 16 The tr uth table for the design of the input par ameter s of the adder

5. 5. 2 Design of the Shifter as an Independent Unit

5

Example 5. 9

Table 5. 17 The function table of a multifunction shifter for Example 5. 9

5. 5. 3 Design of a Bar r el Shifter

5

Table 5. 18 Inter connections of multiplexer s in a bar r el shifter for a left r otate oper ation
5. 6 Summar y
Exer cises
Pr oblem 5. 1

Note

Pr oblem 5. 2

Pr oblem 5. 3

Note

Pr oblem 5. 4

Pr oblem 5. 5

5


Pr oblem 5. 6

Table 5. 20 The function table of the ALU for Pr oblem 5. 6

Pr oblem 5. 7


Pr oblem 5. 8

5


Pr oblem 5. 9

Pr oblem 5. 10


Pr oblem 5. 11

5


Pr oblem 5. 12


Pr oblem 5. 13


Pr oblem 5. 14

5


Pr oblem 5. 15


Pr oblem 5. 16

5

Table 5. 30 The function table of a logic unit on a J K flip-flop for Pr oblem 5. 16
COMPLEX ARITHMETIC OPERATIONS
6. 1 Single-Pr ecision Multiplication
6. 1. 1 The Basic Algor ithm for Two' s Complement Multiplication

6

Step 1

Step 2

Step 3

Step 4

Step 5

Example 6. 1

6

6. 1. 2 Fast Multiplication

6. 1. 2. 1 The Booth Algor ithm

6

Step 1

Step 2

Step 3

Example 6. 2
6

Example 6. 3

6. 1. 2. 2 Bit-Pair wise Multiplication

?

?
6

Table 6. 1 Recoding bit pair s of Y for the numer ical par t

Table 6. 2 Recoding bit pair s of Y for the sign bit

Step 1

6

Step 2

Step 3

Example 6. 4

6. 2 Double-Pr ecision Multiplication
6. 2. 1 Special Requir ement for the Algor ithm

6

6. 2. 2 The Algor ithm for Double-Pr ecision Multiplication of

Positive Number s

Step 1
Step 2

Step 2'
Step 3

Step 4

6. 2. 3 The Algor ithm for Double-Pr ecision Multiplication of

Two' s Complement Number s

6

Step 1

Step 2

Step 3

Step 4
Example 6. 5

Step 1

Step 2

Step 3

Step 4

Example 6. 6

Step 1

Step 2

Step 3

Step 4
6

6. 3 Single-Pr ecision Division

Step 1

Step 2

Step 3

Step 1

Step 2
Step 3

Example 6. 7

6

Example 6. 8

6. 4 Double-Pr ecision Division
6. 4. 1 Special Requir ements of the Algor ithm

6

6. 4. 2 The Algor ithm for Double-Pr ecision Division of

Fr actional Number s

Example 6. 9

6

6. 4. 3 The Algor ithm for Double-Pr ecision Division of Integer

Number s

Example 6. 10

(

) (

)
6

(

)
(
) (

)

Example 6. 11

6. 5 Floating-Point Oper ations
6. 5. 1 The Repr esentation of Floating-Point Number s

6

?

?

Table 6. 3 2 3 code vs. 4?bit two' s complement code
Excess?

Table 6. 4 Evaluating biased exponents of an IEEE standar d floating-point oper and
Example 6. 12

6. 5. 2 The Algor ithms for Floating-Point Oper ations

Floating-point addition / subtr action
A B ma ea mb eb ma mb eb ea ea if ea eb
A B ma ea mb eb ma mb ea or ma mb eb if ea eb
A B ma ea mb eb ma ea eb mb eb if ea eb
6

Floating-point multiplication
A B ma ea mb eb ma mb ea eb .
Floating-point division
A B ma ea mb eb ma mb ea eb .
From the above expressionssome common principles can be summarized
The exponent and mantissa are treated separately. The exponents need only addition /
subtraction. The mantissa need fixed-point addition / subtractionmultiplicationand
division. The results of the two parts are combined together as the floating-point result.
The operations are usually defined as normalized operations. The initial operands are al-
ways normalizedand the result should also be normalized by shifting the mantissa and
adjusting the exponent correspondingly. Left normalization is needed for removing the
leading zeros from the mantissaand right normalization is needed if the operation on
the mantissa has caused overflow. The final result has an overflow only when the expo-
nent part has an overflow after right normalization.
Floating-point addition / subtraction is more complicated than its fixed-point counterpart.
It requires exponent equalization before the two mantissa can perform addition / subtrac-
tion. A compare operation is needed by the exponentsand a right shift operation is
needed by the mantissa. Detailed implementation of the floating-point addition / subtrac-
tion will be described next.
6. 5. 3 A Complete Algor ithm for Floating-Point

Addition / Subtr action
From Expression. we can derive the following steps for floating-point addition / subtraction
Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Example 6. 13

Example 6. 14

Example 6. 15

6

6. 5. 4 Implementation of Floating-Point Addition / Subtr action by

Sequential Logic

6. 6 Summar y
Exer cises
Pr oblem 6. 1

6

Pr oblem 6. 2

Pr oblem 6. 3

Pr oblem 6. 4

Pr oblem 6. 5

Pr oblem 6. 6

Pr oblem 6. 7

Pr oblem 6. 8

Pr oblem 6. 9

6

Pr oblem 6. 10

Pr oblem 6. 11

Note

Pr oblem 6. 12

Pr oblem 6. 13

Pr oblem 6. 14

Note

Pr oblem 6. 15

6

Note

Pr oblem 6. 16

INSTRUCTION SET ARCHITECTURE
7. 1 The Instr uction For mat
Example 7. 1

7

7. 2 The Addr essing Modes
7. 2. 1 Specifying the Oper and in the Instr uction Code

7. 2. 2 Specifying the Oper and in a Register

7. 2. 3 Specifying the Oper and in Memor y

1. Memor y Dir ect Addr essing Mode

2. Register Indir ect or Register Defer r ed Addr essing Mode

3. Memor y Indir ect or Memor y Defer r ed Addr essing Mode

4. Displacement Addr essing Mode

5. Indexed Addr essing Mode

7

6. Autoincr ement and Autodecr ement Addr essing Modes

7. Scaled Addr essing Mode

7

7. 2. 4 Specifying a Location Inside the Assembly-Language

Pr ogr am Code

?
?

7. 2. 5 A Case Study of Addr essing Modes

Example 7. 2

Table 7. 1 Selecting the Intel 80x86 / Pentium CPU r egister s using the REG and W fields

Table 7. 2 The Pentium-II addr essing modes for an oper and in either memor y or a r egister
7. 3 Instr uction Set Design

!"# $%&%())#% %#*+,%#)#-./

!"# ,)$0#)#-.(.,&- .#1"-&0&2

!"# &3#%(00 $#%4&%)(-1# &4 ."# 1&)$+.#%

5(167(%8 1&)$(.,9,0,.2 ,- ."# 1&)$+.#% 4(),02

7. 3. 1 Data Movement Instr uctions

7

7. 3. 2 Ar ithmetic-Logic Instr uctions

?

Example 7. 3

7

7. 3. 3 Contr ol Instr uctions

?

7

Example 7. 4

:(.( ;&3#)#-.

<%,.")#.,1

5&&0#(-

=",4.

!#/.>?&)$(%#

Note

!%(-/4#% &4 1&-.%&0

5,-(%21&8#8 8#1,)(0

=.%,-/

?&-8,.,&- 1&8#/ ,- ."# @AB<C= %#,/.#%

7

7. 4 Reduced Instr uction Set Computer s RISC

?

7

Example 7. 5
B&(8>=.&%#

=",4.
5&&0#(-

<%,.")#.,1

D+)$>5%(-1"

Example 7. 6
B&(8>=.&%#

7

<BE ,))#8,(.#

<BE 4+-1.,&-/

=",4.

;+0.,$02>:,3,8#

D+)$>5%(-1"

=$#1,(0
7. 5 Summar y
Exer cises
Pr oblem 7. 1

7

Pr oblem 7. 2

Note

Pr oblem 7. 3

Pr oblem 7. 4

Note
7

Pr oblem 7. 5

Pr oblem 7. 6

Note
Pr oblem 7. 7

Table 7. 3 The instr uctions available for use in Pr oblem 7. 7

Pr oblem 7. 8

<11+)+0(.&%

;#)&%2)#)&%2
=.(16

B&(8 /.&%#

7

Pr oblem 7. 9

THE CENTRAL PROCESSING UNIT
8. 1 The Functions and Functional Par ts of a CPU
8. 2 The Basic Or ganization of the CPU
8. 2. 1 CPU Or ganization Based on Gener al-Pur pose Register s

8

8. 2. 2 CPU Or ganization Based on an Accumulator

8. 2. 3 CPU Or ganization Based on a Pr ocessor Stack

8

8. 3 The Str uctur e of a CPU Based on an Accumulator

!"#"$% &()%"&

*+"&,-)#" &()%"&

!"#./ 01)+"& &()%"&

*+-2 &()%"&

3#% &()%"&

4&1(&#, .1$+"&
*+%"&$.")1+ &()%"&
8

5,1&6 #--&%% &()%"&

5,1&6 7$88& &()%"&

8. 3. 1 Design of an Accumulator -Based CPU Built on a Single Bus

?

5,1&6 -)&." #--&%%)+( ,1-

*+-2- #--&%%)+( ,1-

49 &:#"); #--&%%)+( ,1-

8

5,1&6 )+-)&." #--&%%)+( ,1-

8. 3. 2 Design of a Two-Bus or Thr ee-Bus Accumulator -Based CPU

8

8. 3. 3 Design of an Accumulator -Based CPU Built on an ALU

8

1. Update the Pr ogr am Counter

2. Calculate the Effective Addr ess

3. Per for m Special Contr ol Functions

4. Pr ovide a Common Datapath for Communication between Register s

Table 8. 1 The tr uth table for designing the datapaths of a simple CPU
8. 4 The Str uctur e of a CPU Based on Gener al-Pur pose

Register s
8. 4. 1 The Str uctur e of a Gener al-Pur pose Register Set

8. 4. 2 Design of a CPU Based on Gener al-Pur pose Register s

8. 5 CPU Bit-Slice DeviceA Case Study
1. 16-wor d by 4-bit two-por t gener al-pur pose r egister set

2. Car r y look-ahead ALU

3. ALU function decode cir cuit

4. Q r egister

5. ALU sour ce oper and decode cir cuit

6. RAM-shifter and Q-shifter

7. ALU destination decode cir cuit

8

Table 8. 2 The function table for the ALU destination selection of the Am2901

8. 6 Summar y
Exer cises
Pr oblem 8. 1

Pr oblem 8. 2

Note
Pr oblem 8. 3

Note
Pr oblem 8. 4

Note
Pr oblem 8. 5

Note

Pr oblem 8. 6

Pr oblem 8. 7

Pr oblem 8. 8

8

Table 8. 3 The instr uction set for Pr oblem 8. 8

THE CONTROL UNIT
9. 1 Functions and General Organization of a Control Unit

T

9

9. 2 Pr eliminar ies of Designing Contr ol Cir cuits
9. 2. 1 Contr ol Voltage Signals vs. Contr ol Pulse Signals

9

9. 2. 2 Design of a Signal Gener ator Based on a Counter

Example 9. 1

9. 2. 3 Synchr onous Contr ol vs. Asynchr onous Contr ol

9

9. 2. 4 Asynchr onous Cir cuits of Signal Gener ator s

!"#$"%!"& (&)*

!+,-.* !"* (&)*

/&,"+,0&01 (&)*

!+,-.* 1*20*,3* (&)*

40."+ 1*20*,3* (&)*

/&,"+,0&01 (&)*

Example 9. 2

9

Example 9. 3

Table 9. 1 Decoding of individual codes or combinations of codes in a J ohnson counter
9. 3 Design of the Sequential Control of Arithmetic Operations
9. 3. 1 Design of a Bit-Ser ial Adder

!"#"* 5
!"#"* 6
!"#"* 7
!"#"* 8

9. 3. 2 Design of a Sequential Two' s Complement Multiplier

9

9330(0.#"&$ 9

:*-+1"*$ ;

:*-+1"*$ 4

Table 9. 2 The contr ol pr ocess of an 8-bit multiplication
9. 4 Design of Har dwir ed Contr ol of a Simple Computer
9. 4. 1 Specification of a Simple RISC Pr ocessor

</
=:
49:

4>:

9

Table 9. 3 The instr uction set of a simple MIPS-like RISC computer
9. 4. 2 The Basic Instr uction Cycle

9

=,1"$03"+&, ?*"3@
=,1"$03"+&, )*3&)+,-
:*-+1"*$ $*#)
A*$#"+&, *B*30"+&,

4*(&$C $*#)%D$+"*
:*10." 1"&$#-*

9. 4. 3 Design of the Oper ation Char t for the Instr uction Set

9

?

9

9. 4. 4 Design and Implementation of the Contr ol Signals

?

?

?

9

9. 4. 5 Design and Implementation of the Datapath and Timing Signals

9

?

?

?

9

Table 9. 4 State-tr ansition table for designing the timing signals

9. 5 Design of the Micr opr ogr ammed Contr ol of

a Simple Computer
9. 5. 1 Gener al Consider ations for Micr opr ogr ammed Contr ol
9. 5. 1. 1 Micr opr ogr ammed Contr ol vs. Har dwir ed Contr ol

9

Step 1

Step 2

Step 3

?

9. 5. 1. 2 Hor izontal Micr opr ogr amming vs. Ver tical Micr opr ogr amming

1. Hor izontal Micr opr ogr amming

2. Ver tical Micr opr ogr amming

9. 5. 2 Design of the Datapath for Microprogrammed Control

56 ?&$ +,1"$03"+&, ?*"3@

65 ?&$ )#"# D$+"*

66 ?&$ )#"# $*#)

55 ?&$ ,& (*(&$C &*$#"+&,

9. 5. 3 Design of the Micr oinstr uction For mat for

Micr opr ogr ammed Contr ol

9

9. 5. 4 Design of the Flowchar t for Micr opr ogr ammed Contr ol

9. 5. 5 Obtaining the Micr opr ogr am List

Table 9. 5 The micr opr ogr am list for a simple RISC computer
9. 6 Summar y
Exer cises
Pr oblem 9. 1

Table 9. 6 The given two-addr ess instr uction set for Pr oblems 9. 1-9. 2

?
?

Notes

Pr oblem 9. 2

Pr oblem 9. 3

9

Table 9. 7 The given one-addr ess instr uction set for Pr oblems 9. 3-9. 4

?

?
?

Pr oblem 9. 4

Pr oblem 9. 5

9

Table 9. 8 The instr uction set par tlyfor Pr oblems 9. 5-9. 6
Note

9

Pr oblem 9. 6

Note

Pr oblem 9. 7

Table 9. 9 The instr uction set for Pr oblems 9. 7-9. 9

9

Pr oblem 9. 8

Pr oblem 9. 9

PRIMARY MEMORY
10. 1 The Memor y Hier ar chy
10. 1. 1 The Hier ar chical Or ganization of a Memor y System

10

10. 1. 2 Functionality and Per for mance of a Memor y Hier ar chy

10

10. 2 The Or ganization of Main Memor y
10. 2. 1 Functions and Char acter istics of RAM Chips

10. 2. 2 Inter nal Or ganization of a RAM Chip

10

!" !##$%&&"( )%*+,"&)

?

-%).$/ *%00 ,$$,/ ,"# &%"&%12$3% ,)405%$&

6,3, "1.73 0,3*+%& ,"# *."3$.0 0.(*

80.*9 (%"%$,3.$&

10. 2. 3 Basic Oper ations for Accessing RAM

10

10. 2. 4 Inter connection of RAM Chips for Lar ger Capacity

10

10. 3 RAM Techniques for Enhanced Per for mance

10

10. 3. 1 Asynchr onous DRAM

10. 3. 2 FPM and EDO

10

10. 3. 3 Synchr onous DRAM SDRAM

10

10. 3. 4 Rambus DRAM RDRAM

10. 3. 5 Flash Memor y vs. EEPROM

10

10. 3. 6 Split Bus

?

10. 4 Cache Memor y

10

10. 4. 1 Locality of Memor y Refer ences

10. 4. 2 Mapping Functions

10. 4. 2. 1 Dir ect ?

Mapped Cache

10

Example 10. 1

10

10. 4. 2. 2 Fully Associative Cache

Example 10. 2

10. 4. 2. 3 Set Associative Cache

10

Example 10. 3

10

10. 4. 3 Wr ite Policies

10. 4. 4 Replacement Algor ithms

10

10. 4. 5 Cache Or ganization and Per for mance

Example 10. 4

10

10. 5 Over all Pr imar y Memor y Or ganization
10. 5. 1 Ser ial-Memor y Nar r ow-Bus Or ganization

?

10. 5. 2 Par allel-Memor y Wide-Bus Or ganization

10

10. 5. 3 Par allel-Memor y Nar r ow-Bus Or ganization

10

10. 5. 4 Inter leaved-Memor y Nar r ow-Bus Or ganization

10

(

)

(

)
Example 10. 5

(
)

(

)

(
)

(

)

( )

Table 10. 1 The speedups for thr ee par allel pr imar y memor y or ganizations

? ?
? ?
?
?
10

10. 6 Summar y
Exer cises
Pr oblem 10. 1

Pr oblem 10. 2

Pr oblem 10. 3

Pr oblem 10. 4

Pr oblem 10. 5

10

Pr oblem 10. 6

Pr oblem 10. 7

Pr oblem 10. 8

Table 10. 2 The fr equencies of usage of load / stor e LW / SWand other

instr uctions for Pr oblem 10. 8

Pr oblem 10. 9

INPUT / OUTPUT
11. 1 Functions and Char acter istics of I / O Subsystem

11

!"# $%&& &()*&$

+&),- $%&& &()*&$

.)/0 $%&& &()*&$

123 &()*&$

4&()*& *"567"88&7$

123 )56&79:*&$

11. 2 Secondar y Stor age

11

11. 2. 1 Magnetic Disk

11

11. 2. 2 Redundant Ar r ay of Independent Disks RAID

11

;<14 !&(&8 =

;<14 !&(&8 >

;<14 !&(&8 ?

11

;<14 !&(&8 @

;<14 !&(&8 A

;<14 !&(&8 B

;<14 !&(&8 C

;<14 !&(&8 >=
;<14 !&(&8 >B

11. 2. 3 Optical Disks

11

11. 2. 4 Magnetic Tapes

11

11. 3 Input / Output Accessing
11. 3. 1 Addr essing I / O Register s

1. Memor y-Mapped I / O

2. Dir ect I / O

11

11. 3. 2 Pr ogr ammed I / O

11

Example 11. 1

11. 3. 3 Inter r upt-Dr iven I / O

?

11

?

?

? ?

?
?

?
?

?

11. 3. 4 Dir ect Memor y Access

?
?

?
?
? ?
11

?
?

4:6: D,99&7 7&/)$6&7 E4F;G

4+< :7&$$ 7&/)$6&7 E4<;G

H"7 *",56&7 EHIG

I"567"82$6:6,$ 7&/)$6&7 EIJ;G

?

?

?

?

?
? ?
11

?

?
?
?

?
?

?
?

?

?

11. 4 Exception and Exception Handling

?

?

?

?

11. 4. 1 Inter r upt Request and Inter r upt Acknowledge

?

?

11. 4. 2 Inter r upt Identification

11

11. 4. 2. 1 Softwar e Polling

11. 4. 2. 2 Vector ed Inter r upt

1. Vector ed Inter r upt by Daisy-Chaining

11

156&77,%6 7&K,&$6)5/ *)7*,)6

4:)$L *0:)5 *)7*,)6

156&77,%6 (&*6"7 /&5&7:6)"5 *)7*,)6

2. Vector ed Inter r upt by a Pr ior ity Encoder

11. 4. 2. 3 Distr ibuted Inter r upt Identification

11

Example 11. 2

11. 4. 3 Inter r upt Ser vicing and Inter r upt Retur ning

M"5 %7&&-%6)(& )56&77,%6

N7&&-%6)(& )56&77,%6

11

11. 5 The I / O Inter faces
11. 5. 1 I / O Bus Pr otocol

11. 5. 1. 1 Synchr onous Bus

11

11. 5. 1. 2 Asynchr onous Bus

11. 5. 2 Par allel I / O Por ts

11

11. 6 Ser ial I / O Data Communication
11. 6. 1 Timing Synchr onization of Ser ial Tr ansmission

11

11

11. 6. 2 Er r or Detection and Cor r ection Codes

11. 6. 2. 1 Par ity Check

Example 11. 3

11

1 1

0

1

11. 6. 2. 2 Hamming Code

11

11

Table 11. 1 Deter mining the Hamming code length r elative to the length of data bits
11. 6. 2. 3 Block Checksum

Example 11. 4

11

11. 6. 2. 4 Cyclic Redundancy Check CRC

11

11

?

?

?

?

?
? ? ?
?
?

11

11. 6. 3 Ser ial Inter faces and I / O Por ts

11

11

11. 7 Bus Standar ds

11

11. 7. 1 PCI Per ipher al Component Inter connectBus

11

11. 7. 2 SCSI Small Computer System Inter facePar allel Inter face

11

11

F,$ O7&&
<7D)67:6)"5

J&8&*6)"5
;&$&8&*6)"5

159"7-:6)"5 67:5$9&7
I"--:5
4:6:

J6:6,$

+&$$:/&

1. Ar bitr ation

11

2. Selection

3. Infor mation Tr ansfer

4. Reselection

11. 7. 3 The USB Ser ial Bus

11

11. 7. 3. 1 Hub-Tr ee Ar chitectur e

11. 7. 3. 2 Data Flow Model on USB

11

I"567"8

1$"*07"5",$

F,8P
156&77,%6

11. 7. 3. 3 Plug-and-Play

11. 7. 3. 4 USB Pr otocol

I"567"8 %:*P&6

4:6: %:*P&6

11

11. 7. 3. 5 The Isochr onous Tr ansfer Mode on USB

11

11. 7. 4 The Fir eWir e Ser ial Bus

O:)7 :7D)67:6)"5

Q7/&56 :7D)67:6)"5

<$L5*07"5",$ 67:5$-)$$)"5

11

1$"*07"5",$ 67:5$-)$$)"5

11. 7. 5 Switched-Fabr ic Ar chitectur e and InfiniBand

11

11. 8 Summar y
Exer cises
Pr oblem 11. 1

Pr oblem 11. 2

11

Pr oblem 11. 3

Pr oblem 11. 4

Pr oblem 11. 5

Pr oblem 11. 6

Table 11. 2 The list of I / O addr ess mapping for Pr oblem 11. 6

11

Table 11. 3 The instr uctions used in Pr oblem 11. 6
Pr oblem 11. 7

Pr oblem 11. 8

Pr oblem 11. 9

Table 11. 4 The instr uction usage for Pr oblem 11. 9

PIPELINING

I ?

?
?

?

?

12. 1 The Basic Concept of Pipelining

?

?
12. 1. 1 Par allelism in Time vs. Par allelism in Space

?

?

? ?

?

12

12. 1. 2 Tempor al Par allelism in Pipelining

?

Example 12. 1

12

Example 12. 2
?
?
?

?

?

?

?

?

?

Example 12. 3 ?
?

?

12

?

?

?

?
?

?

Example 12. 4 ?

?

?
?

?

?

?
?
12. 1. 3 Per for mance of the Pipeline

?

?

12

12. 2 Gener al Or ganization of a Pipeline
12. 2. 1 Synchr onous Pipeline

?

12

12. 2. 2 Asynchr onous Pipeline

?
?

?

?

12

?
?

?

12. 3 Design of a Pipeline by Way of Functional

Decomposition

?

?

12. 3. 1 Special Pr oper ties of Instr uction Pipelines

?

12

12. 3. 2 The Mapping of the Dataflow Patter n to the Pipeline

?

?

ALU Gr oup

LW / SW Gr oup

12

Br anch Gr oup

Table 12. 1 Mapping the execution steps of the instr uctions in Table 9. 3 to a pipeline
J ump Gr oup

12. 3. 3 Design of the Basic Datapath of the Pipeline

?

?

?

12

?
?

?

12

12. 4 The Design of the Pipeline fr om Hazar d Analysis
12. 4. 1 Str uctur al Hazar ds

?

?

?

12. 4. 2 Data Hazar dsA Gener al Discussion

12

12. 4. 3 Data Hazar d Analysis

12. 4. 3. 1 Data Hazar d Resolved by For war ding fr om ALU Output to ALU Input

12

12. 4. 3. 2 Data Hazar d Resolved by For war ding fr om ALU Output to Br anch Input

12

12. 4. 3. 3 Data Hazar d Resolved by For war ding fr om ALU Output to Memor y Input

12. 4. 3. 4 Data Hazar d Resolved by For war ding fr om Memor y Output to

Memor y Input

12

12. 4. 3. 5 Load Inter lock

?

?

?

??

?
?

?
?

12

?
?

12. 4. 4 Contr ol Hazar ds

?
?

?

?

12

1. Pipeline Stall

?
2. Br anch Pr ediction

3. Delayed Br anch

4. Multiple Str eams

5. Loop Buffer

12. 4. 4. 1 Pipeline Stall Due to Br anch Inter lock

12

?
?

12. 4. 4. 2 Flushing the Pipeline Dur ing a Br anch Taken

?

12. 4. 4. 3 Delayed Br anch

12

Example 12. 5 ?

12. 4. 5 The Complete Datapath of the Pipeline

12

12. 5 Super scalar Pr ocessor
12. 5. 1 Special Featur es of a Super scalar Pr ocessor

?

?

?

?

?

?
?

?
??

? ??
12

12. 5. 2 Conceptual Str uctur e of a Super scalar Pr ocessor

1. Instr uction Fetching
?
?

?

2. Instr uction Decoding

?

3. Instr uction Dispatching

4. Instr uction Execution

5. Instr uction Completion and Instr uction Retir ing

? ? ? ?

12. 5. 3 Instr uction ?Issue and Instr uction ?Execute Policies

?

?
?

12

12. 5. 3. 1 In ?or der Issue with In ?or der Completion

?
?

?
?

12. 5. 3. 2 In ?or der Issue with Out ?of?or der Completion

? ?

? ?
? ??
12. 5. 3. 3 Out ?of?or der Issue with Out ?of?or der Completion
??

?

12

?? ??
12. 6 Summar y

?

?

?
?

?
?
?
?

Exer cises
Pr oblem 12. 1

12

Pr oblem 12. 2
?

?
?

?
?

Pr oblem 12. 3
?

?

?

Pr oblem 12. 4

12

?
?

?

?

Pr oblem 12. 5

Table 12. 2 The instr uction set for Pr oblem 12. 5

?

12

Pr oblem 12. 6

?

REFERENCES

4

68000

?

?

?
?

68000

Computer Organization (Jin, Hatfield)

Uploaded by

Copyright:

Available Formats

You might also like

Computer Organization (Jin, Hatfield)

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Computer Organization (Jin, Hatfield)

Uploaded by

Copyright:

Available Formats

COMPUTER ORGANIZATION

COMPUTER ORGANIZATIONPRINCIPLESANALYSISAND DESIGN/

Use of the Book

CHAPTER 2 THE REPRESENTATION OF INFORMATION IN A COMPUTER

CHAPTER 3 LOGIC DESIGN OF COMBINATIONAL CIRCUITS

CHAPTER 4 LOGIC DESIGN OF SEQUENTIAL CIRCUITS

CHAPTER 5 THE ARITHMETIC LOGIC UNIT

CHAPTER 6 COMPLEX ARITHMETIC OPERATIONS

CHAPTER 7 INSTRUCTION SET ARCHITECTURE

CHAPTER 8 THE CENTRAL PROCESSING UNIT

CHAPTER 9 THE CONTROL UNIT

CHAPTER 10 PRIMARY MEMORY

CHAPTER 11 INPUT / OUTPUT

1. 1 The Scope of Computer Architecture and Organization

1. 2 Modeling Computer Or ganization

1. 2. 1 The Layer ed Str uctur e of Computer Design Pr ocess

1. 2. 2 The RTL Model of Computer Or ganization

1. 2. 3 The Per for mance Model of a Computer System

1. 3 A Histor ical Sketch of Computer Evolution

1. 4 Repr esentative Computer Families

1. 4. 1 The Pentium Family

1. 4. 2 The SPARC Family

1. 4. 3 The Power PC Family

1. 5 Per spectives of the Computer Evolution

1. 5. 1 The Challenges of a Billion-Tr ansistor IC

1. 5. 2 The New Role of the Next-Gener ation PC

2. 1 Data Types Representing Information in a Computer

2. 2 Repr esentation of Fixed-Point Unsigned Number s

2. 2. 1 The Gener al Positional Number System

2. 2. 2 The Repr esentation of Fr actional Number s

2. 2. 3 Conver sion Between Number s of Differ ent Repr esentations

2. 3 Repr esentation of Fixed-Point Signed Number s

2. 3. 1 Sign-Magnitude Repr esentation

2. 3. 2 Two' s Complement Repr esentation

Table 2. 2 Number s r epr esented in two' s complement notation in descending or der

2. 3. 3 Motivation for the Two' s Complement System

2. 3. 4 One' s Complement Repr esentation

2. 4 Binar y Addition / Subtr action

2. 4. 1 Sign-Magnitude Addition / Subtr action

2. 4. 2 Two' s Complement Addition / Subtr action

2. 4. 3 One' s Complement Addition / Subtr action

2. 5 Other Code Systems Using Bit Str ings

Table 2. 6 Decimal codes

2. 5. 3 Char acter Codes

Table 2. 8 Table of answer s to Pr oblem 2. 1

3. 1 Combinational Logic Functions and Expr essions

3. 1. 1 Using Tr uth Table to Define a Combinational Logic Function

3. 1. 2 Pr imitive Combinational Functions and Basic Logic Oper ations

3. 1. 3 Boolean Algebr a and Logic Expr ession

3. 1. 4 Canonical Logic Expr essions

3. 2 Kar naugh Maps for Simplification of Logic Functions

5. Don' t Car e Conditions

3. 3 Implementation of Combinational Logic Functions

3. 3. 1 ANDORand NOT Gates

Table 3. 6 Mapping a physical table to a logic table using negative logic

3. 3. 2 NAND and NOR Gates

3. 3. 3 XOR and XNOR Gates

3. 4 Design of Combinational Logic Cir cuits

3. 4. 1 Design of a Full Adder