TABLE OF CONTENTS

S.No Name of the Chapter Page No.

Certificate
Declaration
Acknowledgement
Abstract
Table of Contents
List of Figures i
List of Tables iii
List of Acronyms iv

1. INTRODUCTION 01-03
1.1 Basics of Pattern Matching 02
1.2 Motivation 02
1.3 Need of The Work 03

2. NETWORK INTRUSION DETECTION SYSTEM 04-09

2.1 Passive Versus Reactive IDSs 05
2.2 Misuse-Based Versus Anomaly-Based IDSs 06
2.3 Host-Based Versus Network-Based IDSs 08

3. PATTERN MATCHING ALGORITHMS LITERATURE 10-15

3.1 Single-Keyword Pattern Matching Algorithms 10
3.2 Brute Force Algorithm 12
3.3 Karp-Rabin Algorithm 12
4. FINITE STATE MACHINE 16-26
4.1 Finite State Machine 16
4.2 Communicating Finite State Machines 20
4.3 Formal Description 23
4.4 Minimization of Machines 24
5. PROPOSED ALGORITHM 27-33
5.1 Review of AC Algorithm 27
5.2 Proposed Algorithm (AC_Algorithm+Merg_FSM) 29
6. VHDL DESCRIPTION AND FPGA OVERVIEW 34-55
6.1 VHDL Description 34
6.2 FPGA Overview 35
6.2.1 Why do we need FPGAs? 37
6.2.2 Evaluation of FPGA 38
6.3 FPGA Structural Classification 41
6.3.1 Symmetrical arrays 41
6.3.2 Row based architecture 41
6.3.3 Hierarchical PLDs 41
6.4 FPGA Classification on user programmable switch technologies 42
6.4.1 SRAM Based 42
6.4.2 Antifuse Based 43
6.4.3 EEPROM Based 44
6.5 Virtex-5 Families 44
6.6 System Blocks Common to All Virtex-5 Families 44
6.6.1 Configurable Logic Blocks 44
6.6.2 LUT 45
6.6.3 Multiplexers 46
6.6.4 Storage Elements 46
6.6.5 Carry Logic 47
6.7 Xilinx Virtex- 5 LX50T 47
6.7.1 IX50T Overview 47
6.7.2 Features 48
6.7.3 Configuration 48
6.7.4 Adept System 50
6.7.5 Power Supplies 50
6.7.6 DDR2 Memory 51
6.7.7 Flash Memory 52
6.7.8 Ethernet PHY 53
6.7.9 USB Host 54
6.7.10 Video Output 54
7. OVERVIEW OF MODEL-SIM SIMULATOR 56-71
7.1 Simulation(Model-SIM) 56
7.2 Basic Simulation Flow 56
7.3 Project Flow 57
7.4 Multiple Library Flow 58
7.5 Debugging Flow 59
7.6 Create the Working Design Library 60
7.7 Compile The Design 62
7.8 Load The Design 63
7.9 Set Break Points And Step Through The source 67
7.10 Navigating The Interface 70
8. SIMULATION RESULTS 72-75
CONCLUSION 76
FUTURE SCOPE 77
REFERENCES 78
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