Term End Examination - November 2011

Course : ITE305 - Embedded Systems Slot: C1

Time : Three Hours Max.Marks:100

PART A (8 X 5 = 40 Marks)
Answer ALL the Questions

1. (a) Compare and contrast between Microprocessors and Microcontrollers. [3]

(b) Illustrate the burst read transaction of a CPU bus. [2]

2. Classify the cache misses and derive the average access time for a two level cache
system.

3. Construct CDFG for a conditional loop

if (a>b)
{
x =5;
y = c+d;
}
else
x = c-d;

4. Explain the scheduling states of a process in real-time operating system.

5. Define voltage drops, toggling and leakage in CMOS power consumption.

6. Elaborate the architecture of a CAN controller.

7. Design the distributed embedded architecture for an elevator system.

8. Explain the ARM code for a procedure call.

PART B (6 X 10 = 60 Marks)
Answer any SIX Questions

9. Enumerate the UML sequence diagram of a CPU activity with the DMA transfer.

10. Illustrate the vectored interrupt mechanism to handle multiple devices by CPU.

11. Explain the role of assembling and linking in the compilation process. Give suitable
examples.

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12. Implement the shared memory and message passing communication on a common bus
system.

13. Explain the power saving modes of the StrongARM SA-1100.

14. Elaborate the bus transactions on the I2C bus system.

15. Explain the IP packet structure for an internet protocol.

16. Write short notes on:

(a) ARM data instructions [5]

(b) C switch statements in ARM. [5]

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